LTC5569 – 300MHz to 4GHz 3.3V Dual Active …

LTC5569

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For more information www.linear.com/LTC5569

TYPICAL APPLICATION

FEATURES DESCRIPTION

300MHz to 4GHz 3.3V Dual Active

Downconverting Mixer

The LTC®5569 dual active downconverting mixer is opti-mized for diversity and MIMO receiver applications that require low power and small size. Each mixer includes an independent LO buffer amplifier, active mixer core, and bias circuit with enable pin. The symmetry of the IC as-sures that a phase and amplitude coherent LO is applied to each mixer.

The RF inputs are 50Ω matched from 1.4GHz to 3.3GHz, and easily matched for higher or lower RF frequencies with simple external matching. The LO input is 50Ω matched from 1GHz to 3.5GHz, even when one or both mixers are disabled. The LO input is easily matched for higher or lower frequencies, as low as 350MHz, with simple external matching. The low capacitance differential IF outputs are usable up to 1.6GHz.

APPLICATIONS

n High IIP3: 26.8dBm at 1950MHzn 2dB Conversion Gainn Low Noise Figure: 11.7dB at 1950MHzn 17dB NF Under 5dBm Blockingn 44dB Channel Isolationn Low Power: 3.3V/600mW Totaln Very Small Solution Sizen Enable Pins for Each Mixern Wide IF Frequency Rangen LO Input 50Ω Matched in All Modesn –40°C to 105°C Operationn 16-Lead (4mm × 4mm) QFN package

n Wireless Infrastructure Diversity Receiversn MIMO Infrastructure Receiversn Remote Radio Units

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

RFA

RFB

ENA

ENB

10nF

1nF10nF

1nF

2.7pFRF

MAIN

1nF

3.3V10nF

3.9pF LOLO

BPF

DUALIF VGA

DUALADC

3.3V10nF

ENA

ENB

VCCA

VCCB

IFA+

LTC5569

IFA–

IFB+ IFB–

1nF 190MHz

190MHz

270nH 270nH

270nH 270nH

2.7pFRF

DIVERSITY

BIASRF

BIAS

LO

LO

RF

BPF

5569 TA01a

Diversity Receiver with 190MHz Bandpass IF Matching

Mixer Conversion Gain, IIP3 and NF vs IF Output Frequency

IF OUTPUT FREQUENCY (MHz)140

0.5

G C (d

B)

IIP3 (dBm), SSB NF (dB)

1.0

2.0

2.5

3.0

200 210 220 230

5.0

5560 TA01b

1.5

150 160 170 180 190 240

3.5

4.0

4.5

12

10

14

18

20

22

28

16

24

26IIP3

GC

NF

±30MHz

RF = 1950 ±50MHzLO = 1760MHzPLO = 0dBmZRF = 50ΩZIF = 50ΩTC = 25°CTEST CIRCUIT IN FIGURE 1

http://www.linear.com/LTC5569


LTC5569

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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage VCCA, VCCB, IFA+, IFA–, IFB+, IFB– ........................4.0VEnable Input Voltage (ENA, ENB) .....–0.3V to VCC + 0.3VMixer Bias Voltage (BIASA, BIASB) ..–0.3V to VCC + 0.3VLO Input Power (350MHz to 4.5GHz) ...................10dBmLO Input DC Voltage ............................................... ±0.1VRFA, RFB Input Power (300MHz to 4GHz) ...........20dBmRFA, RFB Input DC Voltage .................................... ±0.1VOperating Temperature Range (TC) ........ –40°C to 105°CJunction Temperature (TJ) .................................... 150°CStorage Temperature Range .................. –65°C to 150°C

(Note 1)

16 15 14 13

5 6 7 8

TOP VIEW

17GND

UF PACKAGE16-LEAD (4mm × 4mm) PLASTIC QFN

9

10

11

12

4

3

2

1RFA

GND

GND

RFB

ENA

LO

GND

ENB

BIAS

A

IFA+

IFA–

V CCA

BIAS

B

IFB+

IFB–

V CCB

TJMAX = 150°C, θJC = 8°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION CASE TEMPERATURE RANGE

LTC5569IUF#PBF LTC5569IUF#TRPBF 5569 16-Lead (4mm × 4mm) Plastic QFN –40°C to 105°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

AC ELECTRICAL CHARACTERISTICS VCC = 3.3V, ENA, ENB = High. Test circuit shown in Figure 1. (Notes 2, 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

RF Input Frequency Range 300 to 4000 MHz

LO Input Frequency Range 350 to 4500 MHz

IF Output Frequency Range External Matching Required LF to 1600 MHz

RF Input Return Loss ZO = 50Ω, 1400MHz to 3300MHz >12 dB

LO Input Return Loss ZO = 50Ω, 1000MHz to 3500MHz >12 dB

IF Output Impedance Differential at 190MHz 530Ω ||1.3pF R||C

LO Input Power –6 0 6 dBm


LTC5569

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AC ELECTRICAL CHARACTERISTICS VCC = 3.3V, ENA, ENB = High. TC = 25°C, PLO = 0dBm, IF = 190MHz, PRF = –6dBm (–6dBm/tone for 2-tone tests), unless otherwise noted. Test circuit shown in Figure 1. (Notes 2, 3, 4)


Power Conversion Gain RF = 450MHz, High Side LO RF = 850MHz, High Side LO RF = 1950MHz, Low Side LO RF = 2550MHz, Low Side LO RF = 3500MHz, Low Side LO

0.5

1.5 2.0 2.0 1.8 1.4

dB dB dB dB dB

Conversion Gain Flatness RF = 1950 ±30MHz, LO = 1760MHz, IF = 190 ±30MHz ±0.05 dB

Conversion Gain vs Temperature TC = –40°C to 105ºC, RF = 1950MHz, Low Side LO –0.014 dB/°C

2-Tone Input 3rd Order Intercept (∆f = 2MHz) RF = 450MHz, High Side LO RF = 850MHz, High Side LO RF = 1950MHz, Low Side LO RF = 2550MHz, Low Side LO RF = 3500MHz, Low Side LO

24.0

26.0 27.1 26.8 26.0 25.2

dBm dBm dBm dBm dBm

2-Tone Input 2nd Order Intercept (∆f = 190MHz, fSPUR = fRF1 – fRF2)

fRF1 = 945MHz, fRF2 = 755MHz, fLO = 1040MHz fRF1 = 2045MHz, fRF2 = 1855MHz, fLO = 1760MHz

62.3 63.1

dBm dBm

SSB Noise Figure RF = 450MHz, High Side LO RF = 850MHz, High Side LO RF = 1950MHz, Low Side LO RF = 2550MHz, Low Side LO RF = 3500MHz, Low Side LO

11.9 11.7 11.7 12.1 14.3

dB dB dB dB dB

SSB Noise Figure Under Blocking RF = 850MHz, High Side LO, 750MHz Blocker at 5dBm RF = 1950MHz, Low Side LO, 2050MHz Blocker at 5dBm

17.5 17.0

dB dB

LO to RF Leakage LO = 350MHz to 1000MHz LO = 1000MHz to 2900MHz LO = 2900MHz to 4500MHz

<–58 <–50 <–42

dBm dBm dBm

LO to IF Leakage LO = 350MHz to 1000MHz LO = 1000MHz to 2900MHz LO = 2900MHz to 4500MHz

<–38 <–35 <–33

dBm dBm dBm

RF to LO Isolation RF = 300MHz to 2500MHz RF = 2500MHz to 4000MHz

>57 >50

dB dB

RF to IF Isolation RF = 300MHz to 1400MHz RF = 1400MHz to 3000MHz RF = 3000MHz to 4000MHz

>28 >30 >31

dB dB dB

1/2IF Output Spurious Product (fRF Offset to Produce Spur at fIF = 190MHz)

850MHz: fRF = 945MHz at –10dBm, fLO = 1040MHz 1950MHz: fRF = 1855MHz at –10dBm, fLO = 1760MHz

–75 –71

dBc dBc

1/3IF Output Spurious Product (fRF Offset to Produce Spur at fIF = 190MHz)

850MHz: fRF = 976.67MHz at –10dBm, fLO = 1040MHz 1950MHz: fRF = 1823.33MHz at –10dBm, fLO = 1760MHz

–88 –84

dBc dBc

Input 1dB Compression RF = 450MHz, High Side LO RF = 850MHz, High Side LO RF = 1950MHz, Low Side LO RF = 2550MHz, Low Side LO RF = 3500MHz, Low Side LO

11.1 10.4 10.2 10.4 10.2

dBm dBm dBm dBm dBm

Channel-to-Channel Isolation RF = 300MHz to 1000MHz RF = 1000MHz to 2700MHz RF = 2700MHz to 3000MHz RF = 3000MHz to 3300MHz RF = 3300MHz to 3800MHz

>44 >44 >42 >36 >34

dB dB dB dB dB


LTC5569

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The LTC5569 is guaranteed functional over the –40°C to 105°C case temperature range (θJC = 8°C/W).

Note 3: SSB Noise Figure measured with a small-signal noise source, bandpass filter and 2dB matching pad on RF input, and bandpass filter on the LO input.Note 4: Channel A to channel B isolation is measured as the relative IF output power of channel B to channel A, with the RF input signal applied to channel A. The RF input of channel B is 50Ω terminated, and both mixers are enabled.

TYPICAL DC PERFORMANCE CHARACTERISTICS

Supply Current vs Supply Voltage (One Mixer Enabled)

Supply Current vs Supply Voltage (Both Mixers Enabled)

Test circuit shown in Figure 1.

DC ELECTRICAL CHARACTERISTICS VCC = 3.3V, TC = 25°C. Test circuit shown in Figure 1. (Note 2)


Supply Voltage (VCC) 3.0 3.3 3.6 V

Supply Current One Mixer Enabled Both Mixers Enabled

ENA or ENB = High ENA and ENB = High

90 180

106 212

mA mA

Shutdown Current—Both Mixers Disabled ENA and ENB = Low 200 µA

Enable Logic Inputs (ENA, ENB)

ENA, ENB Input High Voltage (On) 2.5 V

ENA, ENB Input Low Voltage (Off) 0.3 V

ENA, ENB Input Current –0.3V to VCC + 0.3V 100 µA

Turn-On Time 0.6 µs

Turn-Off Time 0.5 µs

Mixer DC Bias Adjust (BIASA, BIASB)

Open-Circuit DC Voltage 2.2 V

Short-Circuit DC Current Pin Shorted to Ground 1.8 mA

VCC SUPPLY VOLTAGE (V)3.0

98

TC = 105°C

85°C

55°C

25°C

–10°C

–40°C

96

94

92

90

88

86

843.3 3.5

5569 G01

3.1 3.2 3.4 3.6

SUPP

LY C

URRE

NT (m

A)


165

SUPP

LY C

URRE

NT (m

A)

170

175

180

185

195

TC = 105°C

85°C

55°C

25°C

–40°C

3.1 3.2 3.3 3.4

5569 G02

3.5 3.6

190

–10°C


LTC5569

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Conversion Gain, IIP3 and NF vs RF Frequency (High Side LO)

RF Isolation vs RF Frequency LO Leakage vs LO FrequencyChannel Isolation vs RF Frequency

Conversion Gain, IIP3 and NF vs RF Frequency (Low Side LO)

1950MHz Conversion Gain, IIP3 and NF vs LO Power (Low Side LO)

1950MHz Conversion Gain, IIP3 and NF vs LO Power (High Side LO)

2550MHz Conversion Gain, IIP3 and NF vs LO Power (Low Side LO)

2550MHz Conversion Gain, IIP3 and NF vs LO Power (High Side LO)

TYPICAL PERFORMANCE CHARACTERISTICS 1400MHz to 3000MHz application. Test circuit shown in Figure 1. VCC = 3.3V, TC = 25°C, PLO = 0dBm, PRF = –6dBm (–6dBm/tone for 2-tone IIP3 tests, ∆f = 2MHz), IF = 190MHz unless otherwise noted.

RF FREQUENCY (GHz)1.4

10

IIP3

(dBm

), SS

B NF

(dB)

GC (dB)

12

16

18

20

30

24

1.8 2.2 2.4

5569 G03

14

26

28

22

0

2

5

1

4

3

1.6 2.0 2.6 2.8 3.0

IIP3

GC

NF

LO INPUT POWER (dBm)–6

0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

4

8

12

28

NF

20

–2 2 4

24

16

2

6

10

26

18

22

14

–4 0 6

5569 G04

85°C25°C–40°C

IIP3

GC


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

4

8

12

28

20

–2 2 4

24

16

2

6

10

26

18

22

14

–4 0 6

5569 G05

85°C25°C–40°C

IIP3

GC

NF


10

IIP3

(dBm

), SS

B NF

(dB)

GC (dB)

12

16

18

20

30

24

1.8 2.2 2.4

5569 G06

14

26

28

22

0

2

5

1

4

3

1.6 2.0 2.6 2.8 3.0

IIP3

GC

NF


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

4

8

12

28

NF

20

–2 2 4

24

16

2

6

10

26

18

22

14

–4 0 6

5569 G07

85°C25°C–40°C

IIP3

GC


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

4

8

12

28

20

–2 2 4

24

16

2

6

10

26

18

22

14

–4 0 6

5569 G08

85°C25°C–40°C

IIP3

GC

NF


ISOL

ATIO

N (d

B)

45

55

3.0

5569 G09

35

251.8 2.2 2.61.6 2.0 2.4 2.8

65

40

50

30

60RF-LO

RF-IF

LO FREQUENCY (GHz)1.2

LO L

EAKA

GE (d

Bm)

–40

–30

–20

2.8

5569 G10

–50

–60

–701.6 2.0

LO-IF

LO-RF

2.4 3.2RF FREQUENCY (GHz)

1.4

ISOL

ATIO

N (d

B) 44

46

48

2.0 2.4 3.0

5569 G11

42

40

381.6 1.8 2.2 2.6 2.8

105°C25°C–40°C


LTC5569

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SSB Noise Figure vs RF Blocker Level

1950MHz Conversion Gain Histogram

Conversion Gain, IIP3, NF and RF Input P1dB vs Temperature

1950MHz IIP3 Histogram

Conversion Gain, IIP3 and NF vs Supply Voltage

1950MHz SSB NF Histogram

2-Tone IF Output Power, IM3 and IM5 vs RF Input Power

Single Tone IF Output Power, 2 × 2 and 3 × 3 Spurs vs RF Input Power

2 × 2 and 3 × 3 Spur Suppression vs LO Power


RF INPUT POWER (dBm/TONE)–12

–90

OUTP

UT P

OWER

/TON

E (d

Bm)

–70

–50

IM3

IM5

–30

–9 –6 –3 0

5569 G12

3

–10

10

–80

–60

–40

–20

0

6

IFOUT

RF1 = 1949MHzRF2 = 1951MHzLO = 1760MHz

RF INPUT POWER (dBm)–15

–85

OUTP

UT P

OWER

(dBm

)

–75

–55

–45

–35

15

–15

–9 –3 0 12

5569 G13

–65

–5

5

–25

–12 –6 3 6 9

IFOUT(RF = 1950MHz)

2RF-2LO(RF = 1855MHz)

3RF-3LO(RF = 1823.33MHz)

LO = 1760MHz


–90

RELA

TIVE

SPU

R LE

VEL

(dBc

)

–85

–80

–75

–70

–60

–4 –2 0 2

5569 G14

4 6

–652RF-2LO

(RF = 1855MHz)

3RF-3LO(RF = 1823.33MHz)

RF = 1950MHzPRF = –10dBmLO = 1760MHz

RF BLOCKER POWER (dBm)–25

SSB

NF (d

B)

14

20

21

22

–15 –5 0

5569 G15

12

18

16

13

19

11

17

15

–20 –10 5 10

RF = 1950MHzBLOCKER = 2050MHzLO = 1760MHz

PLO = –3dBm

PLO = 3dBm

PLO = 0dBm

CASE TEMPERATURE (°C)–45

0

G C A

ND S

SB N

F (d

B), I

IP3

AND

P1dB

(dBm

)

4

8

12

28

20

–15 15

24

16

2

6

10

26

18

22

14

45 75 105

5569 G16

IIP3

NF

P1dB

GC

RF = 1950MHzLOW SIDE LO


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

6

12

18

3.1 3.2 3.3 3.4

5569 G17

3.5

24

30IIP3

NF

GC3

9

15

21

27

3.6

85°C25°C–40°C


CONVERSION GAIN (dB)1.0

DIST

RIBU

TION

(%)

30

40

50

1.5

5569 G18

20

10

25

35

45

15

5

02.0 2.5 3.0

85°C25°C–40°C

RF = 1950MHz, LOW SIDE LO

IIP3 (dBm)24.5

DIST

RIBU

TION

(%)

30

40

25.5

5569 G19

20

10

25

35

15

5

026.5 27.5 28.5

RF = 1950MHz, LOW SIDE LO

85°C25°C–40°C

SSB NOISE FIGURE (dB)9.9

DIST

RIBU

TION

(%)

30

40

10.4 10.9 11.4 11.9 12.4 12.9

5569 G20

20

10

25

35

15

5

013.4


85°C25°C–40°C


LTC5569

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Conversion Gain, IIP3 and NF vs RF Frequency

850MHz Conversion Gain, IIP3 and NF vs LO Power

850MHz Conversion Gain, IIP3 and NF vs Supply Voltage

2-Tone IF Output Power, IM3 and IM5 vs RF Input Power

Single Tone IF Output Power 2 × 2 and 3 × 3 Spurs vs RF Input Power

2 × 2 and 3 × 3 Spur Suppression vs LO Power

Channel Isolation, RF Isolation and LO Leakage vs Frequency

Conversion Gain, IIP3, NF and RF Input P1dB vs Temperature

SSB Noise Figure vs RF Blocker Level


RF FREQUENCY (MHz)700

0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

4

8

12

28

20

750 800 950

24

16

2

6

10

26

18

22

14

850 900 1000

5569 G21

IIP3

NF

GC

HIGH SIDE LO


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

4

8

12

28

20

–2 2 4

24

16

2

6

10

26

18

22

14

–4 0 6

5569 G22

85°C25°C–40°C

IIP3

GC

NF

HIGH SIDE LO


1

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

4

10

13

16

3.4

28

5569 G23

7

3.23.1 3.53.3 3.6

19

22

25

85°C25°C–40°C

HIGH SIDE LO

IIP3

GC

NF

RF/LO FREQUENCY (MHz)700

10

ISOL

ATIO

N (d

B)

LO LEAKAGE (dBm)

20

30

40

50

60

70

–60

–50

–40

–30

–20

–10

0

800 900 1000 1100

5569 G24

1200

RF-LOISO

LO-IF

LO-RF

RF-IFISO

CHANNELISO


0

G C, N

F (d

B), I

IP3,

P1d

B (d

Bm)

4

8

12

28

20

15 75

24

16

2

6

10

26

18

22

14

–15 45 105

5569 G25

IIP3

GC

NF

P1dB

RF = 850MHzHIGH SIDE LO

RF BLOCKER POWER (dBm)–25

SSB

NF (d

B)

14

20

21

22

–15 –5 0

5569 G26

12

18

16

13

19

11

17

15

–20 –10 5 10

RF = 850MHzBLOCKER = 750MHzLO = 1040MHz

PLO = –3dBm

PLO = 3dBm

PLO = 0dBm

RF INPUT POWER (dBm/TONE)–12

–80

OUTP

UT P

OWER

/TON

E (d

Bm)

–60

–40

–20

–9 –6 –3 0

5569 G27

3

0

20

–70

–50

–30

–10

10

6

IFOUT

IM3 IM5

RF1 = 849MHzRF2 = 851MHzLO = 1040MHz

RF INPUT POWER (dBm)–15

–85

OUTP

UT P

OWER

(dBm

)

–75

–55

–45

–35

15

–15

–9 –3 0 12

5569 G28

–65

–5

5

–25

–12 –6 3 6 9

IFOUT(RF = 850MHz)

2LO-2RF(RF = 945MHz)

3LO-3RF(RF = 976.67MHz)

LO = 1040MHz


–90

RELA

TIVE

SPU

R LE

VEL

(dBc

)

–85

–80

–75

–70

–60

–4 –2 0 2

5569 G29

4 6

–65

2LO-2RF(RF = 945MHz)

3LO-3RF(RF = 976.67MHz)

RF = 850MHzPRF = –10dBmLO = 1040MHz


LTC5569

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3GHz to 4GHz application. Test circuit shown in Figure 1.

Conversion Gain, IIP3, NF and Channel Isolation vs RF Frequency

Conversion Gain, IIP3 and NF vs RF Frequency

RF Isolation and LO leakage vs RF and LO Frequency



Conversion Gain, IIP3 and RF Input P1dB vs Temperature

3500MHz Conversion Gain, IIP3 and NF vs Supply Voltage

Channel Isolation vs RF Frequency

RF Isolation and LO Leakage vs RF and LO Frequency


RF FREQUENCY (MHz)400

1

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB) CHANNEL ISOLATION (dB)

3

79

11

21232527

15

425 450

5569 G30

5

1719

13

05

152025

50556065

35

10

4045

30

475 500

IIP3

NF

GC

CH. ISO


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

3

9

12

15

2

27

5569 G31

6

–2–4 40 6

18

21

24

85°C25°C–40°C

IIP3

GC

NF

HIGH SIDE LO

RF/LO FREQUENCY (MHz)400

RF IS

OLAT

ION

(dB)

LO LEAKAGE (dBm)

45

50

55

550 650

5569 G32

40

35

30450 500 600

60

65

70

–50

–40

–30

–60

–70

–80

–20

–10

0

700

RF-LO

LO-IF

LO-RF

RF-IF


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

2

68

10

20222426

14

3.2 3.4

5569 G33

4

1618

12

3.6 4.03.8

IIP3

NF

GC

LOW SIDE LO


0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

3

9

12

15

2

27

5569 G34

6

–2–4 40 6

18

21

24

85°C25°C–40°C

IIP3

GC

NF

RF = 3.5GHzLOW SIDE LO

VCC SUPPLY VOLTAGE3.0

0

G C (d

B), I

IP3

(dBm

), SS

B NF

(dB)

3

9

12

15

3.4

27

5569 G35

6

3.23.1 3.53.3 3.6

18

21

24

85°C25°C–40°C

IIP3

GC

NF

RF = 3.5GHzLOW SIDE LO

RF/LO FREQUENCY (GHz)2.6

0

RF IS

OLAT

ION

(dB)

LO LEAKAGE (dBm)

10

20

30

40

60

RF-LO

RF-IF

LO-IF

LO-RF

2.9 3.2 3.5 3.8

5569 G36

4.1 4.4

50

–60

–50

–40

–30

–20

0

–10


0

G C (d

B), I

IP3,

P1d

B (d

Bm)

4

8

12

28

20

15 75

24

16

2

6

10

26

18

22

14

–15 45 105

5569 G37

IIP3

GC

NF

P1dB



ISOL

ATIO

N (d

B)

36

38

40

3.8

5569 G38

34

32

303.2 3.4 3.6 4.0

105°C25°C–40°C


LTC5569

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PIN FUNCTIONSRFA/RFB (Pin 1/Pin 4): Single-Ended RF Inputs for the A and B Mixers, Respectively. These pins are internally connected to the primary winding of the integrated RF transformers, which have low DC resistance to ground. Series DC-blocking capacitors must be used if the RF sources have DC voltage present. The RF inputs are 50Ω impedance matched from 1.4GHz to 3.3GHz, as long as the mixer is enabled. Operation down to 300MHz or up to 4GHz is possible with external matching.

GND (Pins 2, 3, 10, Exposed Pad Pin 17): Ground. These pins must be soldered to the RF ground plane on the circuit board. The exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board.

LO (Pin 11): Single-Ended Local Oscillator Input. This pin is internally connected to the primary winding of an integrated transformer, which has low DC resistance to ground. A series DC-blocking capacitor must be used to avoid damage to the internal transformer. This input is 50Ω impedance matched from 1GHz to 3.5GHz, even when one or both mixers are disabled. Operation down to 350MHz or up to 4500MHz is possible with external matching.

ENA/ENB (Pin 12/Pin 9): Enable Pins for the A and B Mixers, Respectively. When the input voltage is greater than 2.5V, the mixer is enabled. When the input voltage is less than 0.3V, the mixer is disabled. Typical input current is less than 30µA. These pins have internal pull-down resistors.

VCCA/VCCB (Pin 13/Pin 8): Power Supply Pins for the A and B Mixers, Respectively. These pins must be connected to a regulated 3.3V supply, with bypass capacitors located close to the pins. Typical DC current consumption is 34mA, each.

IFA+/IFA– (Pin 15/Pin 14), IFB+/IFB– (Pin 6/Pin 7): Open-Collector Differential IF Outputs for the A and B Mixers, Respectively. These pins must be connected to the VCC supply through impedance-matching inductors or a transformer center tap. Typical DC current consumption is 28mA into each pin.

BIASA/BIASB (Pin 16/Pin 5): These pins allow adjustment of the mixer DC supply currents for mixers A and B, respec-tively. Typical, open-circuit DC voltage is 2.2V. These pins should be left open circuited for optimum performance.

BLOCK DIAGRAM

RFA

GND

GND

RFB

ENA

ENB

5569 BD

VCCABIASA

BIASB VCCB

IFA–IFA+

IFB+ IFB–

BIASRF

BIAS

LO

LO

RF

1

13

12

LO11

9

8

16 1415

5 76

2

3 GND 10

4


LTC5569

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TEST CIRCUIT

LOIN50Ω

1516

1

2

3

14 13

65

4

12

11

10

9

7 8

C6

IFAOUT190MHz50Ω

RFAIN50Ω

L1

L5BIASA

RF0.015"

0.062"0.015"

GNDBIASGND

RFA

GND

C1

DC1719AEVALUATION BOARD

LAYER STACK-UP(NELCO N4000-13)

C3

GND

RFB

BIASB IFB+ IFB–

ENB

GND

LO

ENA ENA

C11

VCC3.3V

ENB

VCCB

IFA+

17GND

IFA– VCCA

T18:1

LTC5569

T28:1

L3

L2 L4

C9

IFBOUT190MHz50Ω

C8

C5

RFBIN50Ω

L6C2

C4

C10

5569 F01

C7

APPLICATION RF MATCH LO MATCHRF (MHz) LO C1, C2 C3, C4 L5, L6 C5 C6300 to 400 HS 120pF 18pF 3.3nH 1nF 10pF400 to 500 HS 120pF 12pF 2nH 27pF 6.8pF700 to 1000 HS 68pF 4.7pF — 6.8pF 2.2pF1400 to 3000 LS, HS 2.7pF — — 3.9pF —3000 to 4000 LS 3.9pF 0.7pF — 3.9pF 0.3pF

LS = Low side, HS = High side

REF DES VALUE SIZE VENDOR REF DES VALUE SIZE VENDORC1, C2 See Table 0402 AVX C11 2.2µF 0603 AVXC3, C4 See Table 0402 AVX T1, T2 8:1 — Mini-Circuits TC8-1-10LN+

C5 See Table 0402 AVX L1- L4 180nH 0603 Coilcraft 0603HPC6 See Table 0402 AVX L5, L6 See Table 0402 Coilcraft 0402HP

C7-C10 10nF 0402 AVX

Figure 1. Standard Downmixer Test Circuit Schematic (190MHz Bandpass IF Matching)


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APPLICATIONS INFORMATIONIntroduction

The LTC5569 incorporates two identical, symmetric double-balanced active mixers with a common LO input, separate RF inputs and separate IF outputs. See the Pin Functions and Block Diagram sections for a description of each pin. A test circuit schematic showing all external components required for the data sheet specified performance is shown in Figure 1. A few additional components may be used to modify the DC supply current or frequency response, which will be discussed in the following sections.

The LO and RF inputs are single ended. The IF outputs are differential. Low side or high side LO injection may be used. The test circuit, shown in Figure 1, utilizes bandpass IF output matching and 8:1 IF transformers to realize 50Ω single-ended IF outputs. The evaluation board layout is shown in Figure 2.

RF Inputs

A simplified schematic of the A-channel mixer’s RF input is shown in Figure 3. The B-channel is identical, and not shown for clarity. As shown, one terminal of the integrated RF transformer’s primary winding is connected to Pin 1, while the other terminal is DC-grounded internally. For this reason, a series DC-blocking capacitor (C1) is needed if the RF source has DC voltage present. The DC resistance of the primary winding is approximately 4Ω. The secondary winding of the RF transformer is internally connected to the RF buffer amplifier.

The RF inputs are 50Ω matched from 1400MHz to 3300MHz with a single 2.7pF series capacitor on each input. Matching to RF frequencies above or below this frequency range is easily accomplished by adding shunt capacitor C3, shown in Figure 3. For RF frequencies below 500MHz, series

Figure 2. Evaluation Board Layout


LTC5569

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APPLICATIONS INFORMATION

inductor L5 is also needed. The evaluation board does not include pads for the series inductors, so the 50Ω RF input traces need to be cut to install these in series. The RF input matching element values for each application are tabulated in Figure 1. Measured RF input return losses are shown in Figure 4. The RF input impedance and input reflection coefficient, versus frequency are listed in Table 1.

Table 1. RF Input Impedance and S11 (At Pin 1, No External Matching, Mixer Enabled)

FREQUENCY (MHz)

INPUT IMPEDANCE

S11

MAG ANGLE

350 9.0 + j11.9 0.71 152.5

450 11.0 + j13.8 0.66 147.7

575 13.1 + j15.7 0.62 143.0

700 15.2 + j17.3 0.58 138.6

900 18.1 + j20.0 0.53 131.6

1100 21.3 + j22.4 0.49 124.6

1400 27.0 + j25.3 0.42 114.1

1700 33.4 + j26.8 0.36 103.9

1950 39.1 + j25.6 0.30 97.1

2200 43.4 + j21.5 0.23 94.2

2450 44.3 + j15.9 0.18 100.2

2700 40.8 + j9.9 0.15 126.5

3000 33.1 + j6.4 0.22 154.7

3300 24.3 + j6.8 0.36 159.9

3600 17.6 + j9.6 0.49 155.4

3900 12.9 + j12.7 0.61 149.6

LO Input

A simplified schematic of the LO input, with external components is shown in Figure 5. Similar to the RF in-puts, the integrated LO transformer’s primary winding is DC-grounded internally, and therefore requires an external

DC-blocking capacitor. Capacitor C5 provides the necessary DC-blocking, and optimizes the LO input match over the 1GHz to 3.5GHz frequency range. The nominal LO input level is 0dBm although the limiting amplifiers will deliver excellent performance over a ±5dB input power range. LO input power greater than +6dBm may cause conduction of the internal ESD diodes.

To optimize the LO input match for frequencies below 1GHz, the value of C5 is increased and shunt capacitor C6 is added. A summary of values for C5 and C6, versus LO frequency range is listed in Table 2. Measured LO input

LOBUFFER

LOBUFFER

LO

C6

5569 F05

LTC5569

11

C5 LOIN

Figure 5. LO Input Schematic

RFBUFFER

RFA

C3

5569 F03

L5

LTC5569

1

C1RFAIN

Figure 3. RF Input Schematic

Figure 4. RF Input Return Loss

FREQUENCY (GHz)0.2

RETU

RN L

OSS

(dB)

–15

–10

–5

3.2

5569 F04

–20

–25

1.2 2.20.7 3.71.7 2.7 4.2

–30

–35

0

400MHz TO 500MHz APP.700MHz TO 1000MHz APP.1400MHz TO 3000MHz APP.3GHz TO 4GHz APP.

TC = 25°C


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APPLICATIONS INFORMATIONreturn losses are shown in Figure 6. Finally, LO input im-pedance and input reflection coefficient, versus frequency is shown in Table 3.

Table 2. LO Input Matching Values vs LO Frequency RangeFREQUENCY (MHz) C5 (pF) C6 (pF)

350 to 430 390 22

480 to 630 68 12

576 to 722 27 6.8

720 to 980 15 4.7

814 to 1155 6.8 2.2

1000 to 3500 3.9 —

2200 to 4000 3.9 0.3

The LO buffers have been designed such that the LO input

Figure 6. LO Input Return Loss

Figure 7. LO Input Return Loss for Three Operating States

FREQUENCY (GHz)0.2

RETU

RN L

OSS

(dB)

–10

–5

0

1.7 2.7 4.25569 F06

–15

–20

–250.7 1.2 2.2 3.2 3.7

C5 = 27pF, C6 = 6.8pFC5 = 6.8pF, C6 = 2.2pFC5 = 3.9pFC5 = 3.9pF, C6 = 0.3pF

TC = 25°C

FREQUENCY (GHz)0.2

RETU

RN L

OSS

(dB)

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–204.2

5569 F07

1.2 2.2 3.2 3.70.7 1.7 2.7

TC = 25°CC5 = 3.9pF

BOTH MIXERS DISABLEDONE MIXER ENABLEDBOTH MIXERS ENABLED

Table 3. LO Input Impedance and S11 (At Pin 11, No External Matching, Both Mixers Enabled)

FREQUENCY (MHz)

INPUT IMPEDANCE

S11

MAG ANGLE

350 5.5 + j15.1 0.82 146.1

400 6.0 + j17.3 0.81 141.3

450 6.9 + j19.5 0.79 136.7

500 8.0 + j21.8 0.77 131.9

600 10.3 + j26.5 0.73 122.6

800 17.6 + j35.7 0.63 104.5

1000 29.5 + j43.6 0.53 86.5

1500 70.8 + j28.3 0.28 40.5

2000 60.1 – j4.2 0.10 –20.2

2500 41.8 – j3.2 0.10 –156.6

3000 33.1 + j7.4 0.22 151.3

3500 29.8 + j19.2 0.34 122.9

4000 29.5 + j29.9 0.43 103.7

4500 32.0 + j37.6 0.46 90.9

impedance does not change significantly when one or both mixers are disabled. This feature only requires that supply voltage is applied to both mixers. The actual performance of this feature is shown in Figure 7, where LO input return loss versus frequency is shown for the following three operating conditions: both mixers enabled, one mixer enabled, and both mixers disabled. As shown, the LO input return loss is better than 12dB over the 1000MHz to 3500MHz frequency range for all three operating states.

IF Outputs

The A-channel IF output schematic with external match-ing components is shown in Figure 8. The B-channel is identical, and not shown for clarity. As shown, the outputs are differential open collector. Each IF output pin must


LTC5569

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APPLICATIONS INFORMATIONbe biased at the supply voltage (VCC), which is applied through the external matching inductors (L1 and L3) shown in Figure 8. Alternatively, the IF outputs can be biased through the center tap of the IF transformer. Each IF output pin on the IC draws approximately 28mA of DC supply current (56mA total per mixer).

The differential IF output impedance can be modeled as a parallel R-C circuit. These R-C values are listed in Table 4, versus IF frequency. This data is referenced to the pack-age pins (with no external components) and includes the effects of the IC and package parasitics. The values of L1 and L3 are calculated to resonate with the internal capacitance (CIF) at the desired IF center frequency, using the following equation:

L1, L3=

12•π • fIF( )2 •2•CIF

For IF frequencies below 130MHz, the matching inductors are not needed due to the low IF output capacitance. The evaluation board has the transformer center tap connected to the matching inductor center node, thus allowing the cir-cuit to be used without matching inductors. The measured IF output return loss for this case is shown in Figure 9.

Table 4 summarizes the optimum IF matching inductor val-ues, versus IF center frequency, to be used in the standard downmixer test circuit shown in Figure 1. The inductor values listed are less than the ideal calculated values due to the additional capacitance of the 8:1 transformer. For differential IF output applications where the 8:1 transformer is eliminated, the ideal calculated values should be used. Measured IF output return losses are shown in Figure 9. Table 4. IF Output Impedance and Bandpass Matching Element Values vs IF Frequency.

IF FREQUENCY (MHz)

DIFFERENTIAL IF OUTPUT IMPEDANCE

(RIF || CIF)

BANDPASS MATCHING

L1, L3 (A) L2, L4 (B)

50 540Ω||1.3pF Open

140 532Ω||1.3pF 330nH

190 530Ω ||1.3pF 180nH

240 525Ω ||1.3pF 110nH

300 519Ω ||1.3pF 72nH

380 511Ω ||1.3pF 43nH

456 502Ω ||1.3pF 30nH

580 490Ω ||1.33pF

810 477Ω ||1.35pF

1000 450Ω ||1.4pF

Figure 9. IF Output Return Loss—Bandpass Matching with 8:1 Transformer

FREQUENCY (MHz)

–30

RETU

RN L

OSS

(dB)

–20

–10

0

–25

–15

–5

150 250 350 4505569 F09

55010050 200 300 400 500

NO INDUCTORS330nH180nH110nH68nH43nH30nH

1415LTC5569

5569 F08

L1 L3

T18:1

C7

VCC

IFAOUT50Ω

IFA+ IFA–

VCC

Figure 8. IF Output Schematic with Bandpass Matching and 8:1 Transformer


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Figure 11. Conversion Gain and IF Output Return Loss vs IF Frequency—Wideband Matching with 4:1 Transformer

Wideband IF Using Load Resistor and 4:1 Transformer

Wide IF bandwidth and high input 1dB compression can be obtained by reducing the IF output resistance with a shunt resistor (R3), as shown in Figure 10. This will reduce the mixer’s conversion gain, but will not degrade the IIP3 or noise figure. The evaluation board includes pads for R3 (and R4 for the B-channel). To accommodate the lower total IF resistance, transformer T1 should be changed from an 8:1 impedance ratio to a 4:1 ratio. The value of the external matching inductors L1 and L3 needs to be adjusted to ac-count for the differences in the IF transformer parasitics.

Table 5 summarizes the measured conversion gain, IIP3, noise figure, RF input P1dB and IF bandwidth for three values of load resistor. Inductors L1 and L3 have been increased from 180nH to 270nH to keep the IF match centered at 190MHz (the 8:1 transformer has higher ca-pacitance). Also shown, for comparison, is the measured performance using an 8:1 IF transformer and no load resis-tor. Measured conversion gain and IF output return loss versus IF frequency are shown for each case in Figure 11.

Table 5. Measured Performance Using IF Load Resistor (R3) and 4:1 Transformer (RF = 1950MHz, Low-Side LO, IF = 190MHz, VCC = 3.3V, TC = 25°C)

IF XFMR R3 (Ω) GC (dB)

IIP3 (dBm)

SSB NF (dB)

INPUT P1dB (dBm)

0.5dB IF BANDWIDTH

(MHz)

8:1 — 2.0 26.8 11.7 10.2 –55/+85

4:1

1210 0.9 26.8 11.7 12.8 –90/+110

604 0.0 26.8 11.7 13.0 –100/+120

374 -1.1 26.8 11.8 13.3 –115/+120

IF FREQUENCY (MHz)50

–1

0

2

170 250

5569 F11

–2

–3

90 130 210 290 330

–4

–5

1

5

15

35

–5

–15

–25

–35

25

CONV

ERSI

ON G

AIN

(dB) IF RETURN LOSS (dB)

8:1

1210Ω

604Ω

374Ω

374Ω

604Ω

1210Ω

8:1

1415LTC5569

5569 F10

L1 L3

T14:1

C710nF

R3

VCC

IFAOUT50Ω

IFA+ IFA–VCC

Figure 10. IF Output Schematic with Wideband Matching and 4:1 Transformer

Discrete IF Balun Matching

For narrowband IF applications, it is possible to replace the IF transformer with the discrete IF balun shown in Figure 12 (only the A-channel is shown for clarity). The values of L3, L7, C13 and C15 are calculated to realize a 180° phase shift at the desired IF frequency, and provide a 50Ω single-ended output, using the equations listed below. Inductor L1 is calculated to cancel the internal IF capacitance (CIF from Table 4). L1 and L3 also supply DC bias to the IF output pins. R5 and R7 are used to reduce the differential output resistance (RS), which increases


LTC5569

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Figure 13. IF Output Return Losses with Discrete IF Balun Matching

the IF bandwidth, but reduces the conversion gain. C17 is a DC-blocking capacitor.

RS =2•R5•RIF2•R5+RIF

R5=R7( )

L1=1

2•CIF • ωIF( )2

L7=RS •RLωIF

L3=L1•L7L1+L7

C13, C15=1

ωIF RS •RL

These equations give a good starting point, but it is usually necessary to adjust the component values after building and testing the circuit. The final solution can be achieved with less iteration by considering the parasit-ics of L1 and L3 in the above calculations. Specifically, the effective parallel resistance of L1 and L3 (calculated from the manufacturers Q data) will reduce the value of RS , which in turn influences the calculated values of L7, C13 and C15. Also, the effective parallel capacitance of L1

15 14 13

IFA– VCCA

L1 L3

LTC5569

5569 F12

C710nF

R5

C13

C171nF

C15

VCC

C910nF

IFAOUTRL = 50Ω

L7

IFA+

R7

Figure 12. Discrete IF Balun Matching

and L3 (taken from the manufacturers SRF data) must be considered, since it is in parallel with CIF . Frequently, the calculated value for L7 does not fall on a standard value for the desired IF. In this case, a simple solution is to vary the value of R5 (R7), which changes the value of RS , until L7 is a standard value.

Discrete IF balun element values for five common IF fre-quencies are listed in Table 6. Measured IF output return losses are shown in Figure 13. Measured conversion gain, IIP3 and noise figure versus IF output frequency is shown in Figure 14.

Compared to the transformer-based IF matching technique, the most significant performance difference, as shown in Figure 14, is the limited IF bandwidth. For low IF frequen-cies, the passband bandwidth is small, whereas higher IF frequencies offer wider bandwidth.

Table 6. Discrete IF Balun Element Values (RL = 50Ω) (Values Shown for the A Channel and B Channel

IF (MHz)

R5, R7 (A) R6, R8 (B)

(Ω)

L1 (A) L2 (B) (nH)

L3 (A) L4 (B) (nH)

L7 (A) L8 (B) (nH)

C13, C15 (A) C14, C16 (B)

(pF)

170 475 330 91 120 7

190 750 270 82 120 6

240 332 180 56 82 5.6

300 604 110 43 72 3.9

380 475 68 30 56 3.3


RETU

RN L

OSS

(dB)

–15

–10

–5

390

5569 F13

–20

–25

190 290140 440240 340 490

–30

–35

0

170MHz

240MHz380MHz


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Figure 14. Conversion Gain, IIP3 and SSB NF vs IF Output Frequency Using Discrete IF Balun Matching

15 14

IFA– VCCA

VCCA

16

BIASA

54mABIAS

3mABIAS

R1

LTC5569

5569 F12

IFA+13

Figure 15. BIASA Interface (BIASB is Identical)

Mixer Bias Current Reduction

The BIASA and BIASB pins (Pins 16 and 5) are available for reducing the mixer core DC current consumption, of the A- and B-channels, respectively, at the expense of linearity and P1dB. For the highest performance, these pins should be left open circuit. As shown in Figure 15, an internal bias circuit produces a 3mA reference current for each mixer core. If a resistor is connected to Pin 16, as shown in Figure 15, a portion of the reference current can be shunted to ground, resulting in reduced mixer core current. For example, R1 = 1k will shunt away 1mA from Pin 16 and reduce the mixer core current by 33%. The nominal, open-circuit DC voltage at the BIASA and BIASB pins is 2.2V. Table 7 lists DC supply current and RF performance at 1950MHz for various values of R1.

Table 7. Mixer Performance with Reduced Current (RF = 1950MHz, Low Side LO, IF = 190MHz)

R1 (Ω) ICC (mA) GC (dB)IIP3

(dBm)P1dB (dBm) NF (dB)

Open 90.0 2.0 26.8 10.2 11.7

10k 85.2 1.9 25.6 10.2 11.4

1k 71.0 1.6 21.4 10.1 10.4

100 58.6 1.1 17.9 8.9 10.0

11

13

CLAMP

300k

500Ω

LTC5569 VCCA

ENAENA

5569 F16

Figure 16. Enable Input Circuit

Enable Interfaces

Figure 16 shows a simplified schematic of the A-chan-nel enable interface. The B-channel is identical, and not shown for clarity. To enable the A-channel mixer, the ENA voltage must be higher than 2.5V. If the enable function is not required, the pin should be connected directly to VCC. The voltage at the ENA pin should never exceed the power supply voltage (VCC) by more than 0.3V. If this should oc-cur, the supply current could be sourced through the ESD diode, potentially damaging the IC.

The ENA and ENB pins have internal 300k pull-down resis-tors. Therefore, an unused mixer will be disabled with its corresponding enable pin left floating.


G C (d

B), S

SB N

F (d

B), I

IP3

(dBm

)

14

22

18

26

320

5569 F14

10

6

2

–2

16

24

20

28

12

8

4

0

140 200 260 380 440

170MHz240MHz380MHz

IIP3

GC

NF

RF = 1950MHzLOW SIDE LOPLO = 0dBmZRF = 50ΩZIF = 50ΩTC = 25°C


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Supply Voltage Ramping

Fast ramping of the supply voltage can cause a current glitch in the internal ESD clamp circuits connected to the VCCA and VCCB pins. Depending on the supply inductance, this could result in a supply voltage transient that exceeds the 4.0V maximum rating. A supply voltage ramp time greater than 1ms is recommended.

APPLICATIONS INFORMATIONSpurious Output Levels

Mixer spurious output levels versus harmonics of the RF and LO are tabulated in Table 8. The spur levels were measured on a standard evaluation board using the test circuit shown in Figure 1. The spur frequencies can be calculated using the following equation:

fSPUR = (M • fRF) – (N • fLO)

Table 8. IF Output Spur Levels (dBm) (RF = 1950MHz, PRF = –2dBm, PIF = 0dBm at 190MHz, Low Side LO, PLO = 0dBm, VCC = 3.3V, TC = 25°C)

N

M

0 1 2 3 4 5 6 7 8 9

0 –56 –24 –58 –36 –51 –44 –58 –49 –80

1 –32 0 –56 –57 –68 –41 –69 –52 –75 –58

2 –59 –56 –67 –65 –76 –85 –71 –85 –80 *

3 * –88 –89 –74 * * * * –89 *

4 * * –85 * * * * * –85 *

5 * * * * * * * * * *

6 * * * * * * * * *

7 * * *

*Less than –90dBc


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TYPICAL APPLICATION

Voltage Conversion Gain, IIP3 and NF vs IF Frequency


6.5

VOLT

AGE

CONV

ERSI

ON G

AIN

(dB)

SSB NF (dB), IIP3 (dBm)

7.0

8.0

8.5

9.0

200 210 220 230

11.0

5569 TA03b

7.5

150 160 170 180 190 240

9.5

10.0

10.5

10

12

16

18

20

28

IIP3

NF

GV14

22

24

26RF = 1950 ±50MHzLO = 1760MHzPLO = 0dBmZRF = 50ΩZIF = 200ΩTC = 25°C

RFA

ENA

10nF

3.3pF 3.3pF

2.7pFRF

MAIN

3.3V

IFAOUT200Ω

10nF

3.9pF LOLO

ENA

5569 TA03a

VCCAIFA+

LTC5569

CHANNEL B NOT SHOWN

IFA–

3300pF

390nH

82nH 82nH

681Ω

390nH

BIASRF

LO

3300pF

681Ω

200Ω Differential Lowpass IF Output Matching (Element Values Shown for 190MHz IF)


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UF Package16-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1692)

4.00 ± 0.10(4 SIDES)

NOTE:1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1TOP MARK(NOTE 6)

0.55 ± 0.20

1615

1

2

BOTTOM VIEW—EXPOSED PAD

2.15 ± 0.10(4-SIDES)

0.75 ± 0.05 R = 0.115TYP

0.30 ± 0.05

0.65 BSC

0.200 REF

0.00 – 0.05

(UF16) QFN 10-04

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.72 ±0.05

0.30 ±0.050.65 BSC

2.15 ± 0.05(4 SIDES)2.90 ± 0.05

4.35 ± 0.05

PACKAGE OUTLINE

PIN 1 NOTCH R = 0.20 TYPOR 0.35 × 45° CHAMFER

PACKAGE DESCRIPTIONPlease refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.


LTC5569

215569fb


REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 10/11 Revised Turn-On Time and Turn-Off Time Typical values in DC Electrical Characteristics 4

B 11/14 Increase RF Input Absolute Maximum power ratingCorrect (increase) LO Input Power Absolute Maximum Frequency rangeClarify Case Temperature range in Order InformationExtend IF Output Frequency range down to low frequencyClarify Case Temperature on Supply Current graphsCorrect x-axis label on graph G25

222247

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.


LTC5569

225569fb

LINEAR TECHNOLOGY CORPORATION 2011

LT 1114 REV B • PRINTED IN USA


RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTSInfrastructureLTC559x 600MHz to 4.5GHz Dual Downconverting Mixer

Family8.5dB Gain, 26.5dBm IIP3, 9.9dB NF, 3.3V/380mA Supply

LT5527 400MHz to 3.7GHz, 5V Downconverting Mixer 2.3dB Gain, 23.5dBm IIP3 and 12.5dB NF at 1900MHz, 5V/78mA SupplyLT5557 400MHz to 3.8GHz, 3.3V Downconverting Mixer 2.9dB Gain, 24.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/82mA SupplyLTC6400-X 300MHz Low Distortion IF Amp/ADC Driver Fixed Gain of 8dB, 14dB, 20dB and 26dB; >36dBm OIP3 at 300MHz, Differential I/OLTC6416 2GHz 16-Bit ADC Buffer 40dBm OIP3 to 300MHz, Programmable Fast Recovery Output ClampingLTC6412 31dB Linear Analog VGA 35dBm OIP3 at 240MHz, Continuous Gain Range –14dB to 17dBLT5554 Ultralow Distort IF Digital VGA 48dBm OIP3 at 200MHz, 2dB to 18dB Gain Range, 0.125dB Gain StepsLT5575 700MHz to 2.7GHz I/Q Demodulator 28dBm IIP3, 13dBm P1dB, 0.03dB I/Q Amplitude Match, 0.4° Phase MatchLT5578 400MHz to 2.7GHz Upconverting Mixer 27dBm OIP3 at 900MHz, 24.2dBm at 1.95GHz, Integrated RF TransformerLT5579 1.5GHz to 3.8GHz Upconverting Mixer 27.3dBm OIP3 at 2.14GHz, NF = 9.9dB, 3.3V Supply, Single-Ended LO and RF PortsLTC5588-1 200MHz to 6GHz I/Q Modulator 31dBm OIP3 at 2.14GHz, –160.6dBm/Hz Noise FloorRF Power DetectorsLT5538 40MHz to 3.8GHz Log Detector ±0.8dB Accuracy Over Temperature, –72dBm Sensitivity, 75dB Dynamic RangeLT5581 6GHz Low Power RMS Detector 40dB Dynamic Range, ±1dB Accuracy Over Temperature, 1.5mA Supply CurrentLTC5582 40MHz to 10GHz RMS Detector ±0.5dB Accuracy Over Temperature, ±0.2dB Linearity Error, 57dB DynamicLTC5583 Dual 6GHz RMS Power Detector Up to 60dB Dynamic Range, ±0.5dB Accuracy Over Temperature, >50dB IsolationADCsLTC2208 16-Bit, 130Msps ADC 78dBFS Noise Floor, >83dB SFDR at 250MHzLTC2285 Dual 14-Bit, 125Msps Low Power ADC 72.4dB SNR, 88dB SFDR, 790mW Power ConsumptionLTC2268-14 Dual 14-Bit, 125Msps Serial Output ADC 73.1dB SNR, 88dB SFDR, 299mW Power Consumption

200Ω Differential Highpass IF Output Matching (Element Values Shown for 190MHz IF)

RFA

RFB

ENA

ENB

10nF

8.2pF10nF

8.2pF

2.7pFRF

MAIN

8.2pF

3.3V

IFAOUT200Ω

10nF

3.9pF LOLO

3.3V10nF

ENA

ENB

VCCA

VCCB

IFA+

LTC5569

IFA–

IFB+ IFB–

8.2pF

100nH

665Ω

100nH

100nH 100nH

2.7pFRF

DIVERSITY

BIASRF

BIAS

LO

LO

RF

5569 TA02a

IFBOUT200Ω

665Ω

665Ω 665Ω


6.5

VOLT

AGE

CONV

ERSI

ON G

AIN

(dB)

SSB NF (dB), IIP3 (dBm)

7.0

8.0

8.5

9.0

200

11.0

5569 TA02b

7.5

180170 210190 220

9.5

10.0

10.5

10

12

16

18

20

28

14

22

24

26IIP3

GV

NF

RF = 1950 ±30MHzLO = 1760MHzPLO = 0dBmZRF = 50ΩZIF = 200ΩTC = 25°C

Voltage Conversion Gain, IIP3 and NF vs IF Frequency

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC5569



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LTC5569 – 300MHz to 4GHz 3.3V Dual Active …