LTC1666/LTC1667/LTC1668 - 12-Bit, 14-Bit, 16-Bit, 50Msps DACs · directly to external resistors to produce a differential out-put voltage without degrading the converter’s linearity

1

LTC1666/LTC1667/LTC1668

APPLICATIO SU

FEATURES DESCRIPTIO

U

TYPICAL APPLICATION

U

12-Bit, 14-Bit, 16-Bit,50Msps DACs

50Msps Update Rate Pin Compatible 12-Bit, 14-Bit and 16-Bit Devices High Spectral Purity: 87dB SFDR at 1MHz fOUT 5pV-s Glitch Impulse Differential Current Outputs 20ns Settling Time Low Power: 180mW from ±5V Supplies TTL/CMOS (3.3V or 5V) Inputs Small Package: 28-Pin SSOP

The LTC®1666/LTC1667/LTC1668 are 12-/14-/16-bit,50Msps differential current output DACs implemented ona high performance BiCMOS process with laser trimmed,thin-film resistors. The combination of a novel current-steering architecture and a high performance processproduces DACs with exceptional AC and DC performance.The LTC1668 is the first 16-bit DAC in the marketplace toexhibit an SFDR (spurious free dynamic range) of 87dBfor an output signal frequency of 1MHz.

Operating from ±5V supplies, the LTC1666/LTC1667/LTC1668 can be configured to provide full-scale outputcurrents up to 10mA. The differential current outputs ofthe DACs allow single-ended or true differential operation.The –1V to 1V output compliance of the LTC1666/LTC1667/LTC1668 allows the outputs to be connecteddirectly to external resistors to produce a differential out-put voltage without degrading the converter’s linearity. Al-ternatively, the outputs can be connected to the summingjunction of a high speed operational amplifier, or to atransformer.

The LTC1666/LTC1667/LTC1668 are pin compatible andare available in a 28-pin SSOP and are fully specified overthe industrial temperature range.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Cellular Base Stations Multicarrier Base Stations Wireless Communication Direct Digital Synthesis (DDS) xDSL Modems Arbitrary Waveform Generation Automated Test Equipment Instrumentation

LTC1668, 16-Bit, 50Msps DAC

–

+

VSS

VDD

–5V

CLOCKINPUT

16-BIT DATAINPUT

LADCOM

AGND DGND CLK DB15 DB0

1666/7/8 TA01

IOUT A

0.1µF

LTC1668

5V

52.3Ω

IREFIN

REFOUT

COMP1

COMP2

C20.1µF

0.1µF

C10.1µF

RSET2k

IOUT B52.3Ω VOUT

1VP-PDIFFERENTIAL

+

–

0.1µF

16-BITHIGH SPEED

DAC

2.5VREFERENCE

LTC1668 SFDR vs fOUT and fCLOCK

fOUT (MHz)0.1

SFDR

(dB)

100

90

80

70

60

501.0 10 100

1666/7/8 G05

5MSPS

25MSPS

50MSPS

DIGITAL AMPLITUDE = 0dBFS

2

LTC1666/LTC1667/LTC1668

LTC1666CGLTC1666IG

TJMAX = 110°C, θJA = 100°C/W

ORDER PARTNUMBER

Consult LTC Marketing for parts specified with wider operating temperature ranges.

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TOP VIEW

G PACKAGE28-LEAD PLASTIC SSOP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

DB14

DB15 (MSB)

CLK

VDD

DGND

VSS

COMP2

COMP1

IOUT A

IOUT B

LADCOM

AGND

IREFIN

REFOUT

Supply Voltage (VDD) ................................................ 6VNegative Supply Voltage (VSS) ............................... –6VTotal Supply Voltage (VDD to VSS) .......................... 12VDigital Input Voltage .................... –0.3V to (VDD + 0.3V)Analog Output Voltage

(IOUT A and IOUT B) ........ (VSS – 0.3V) to (VDD + 0.3V)

PACKAGE/ORDER I FOR ATIOU UW

ABSOLUTE AXI U RATI GS

W WW U

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TOP VIEW


28

27

26

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15

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

NC

NC

NC

NC

DB10

DB11 (MSB)

CLK

VDD

DGND

VSS

COMP2

COMP1

IOUT A

IOUT B

LADCOM

AGND

IREFIN

REFOUT

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TOP VIEW


28

27

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DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

NC

NC

DB12

DB13 (MSB)

CLK

VDD

DGND

VSS

COMP2

COMP1

IOUT A

IOUT B

LADCOM

AGND

IREFIN

REFOUT

Power Dissipation ............................................. 500mWOperating Temperature Range

LTC1666C/LTC1667C/LTC1668C ........... 0°C to 70°CLTC1666I/LTC1667I/LTC1668I .......... –40°C to 85°C

Storage Temperature Range ................ – 65°C to 150°CLead Temperature (Soldering, 10 sec).................. 300°C

(Note 1)

TJMAX = 110°C, θJA = 100°C/W TJMAX = 110°C, θJA = 100°C/W

LTC1668CGLTC1668IG

ORDER PARTNUMBER

LTC1667CGLTC1667IG

ORDER PARTNUMBER

3

LTC1666/LTC1667/LTC1668

The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.ELECTRICAL CHARACTERISTICS

LTC1666 LTC1667 LTC1668SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

DC Accuracy (Measured at IOUT A, Driving a Virtual Ground)

Resolution 12 14 16 Bits

Monotonicity 12 14 14 Bits

INL Integral Nonlinearity (Note 2) ±1 ±2 ±8 LSB

DNL Differential Nonlinearity (Note 2) ±1 ±1 ±1 ±4 LSB

Offset Error 0.1 ±0.2 0.1 ±0.2 0.1 ±0.2 % FSR

Offset Error Drift 5 5 5 ppm/°C

GE Gain Error Internal Reference, RIREFIN = 2k 2 2 2 % FSRExternal Reference, 1 1 1 % FSRVREF = 2.5V, RIREFIN = 2k

Gain Error Drift Internal Reference 50 50 50 ppm/°CExternal Reference 30 30 30 ppm/°C

PSRR Power Supply VDD = 5V ±5% ±0.1 ±0.1 ±0.1 % FSR/VRejection Ratio VSS = –5V ±5% ±0.2 ±0.2 ±0.2 % FSR/V

AC Linearity

SFDR Spurious Free Dynamic fCLK = 25Msps, fOUT = 1MHzRange to Nyquist 0dB FS Output 76 78 78 87 dB

–6dB FS Output 87 dB –12dB FS Output 83 dB

fCLK = 50Msps, fOUT = 1MHz 85 dB

fCLK = 50Msps, fOUT = 2.5MHz 81 dB



Spurious Free Dynamic fCLK = 25Msps, 85 86 86 96 dBRange Within a Window fOUT = 1MHz, 2MHz Span

fCLK = 50Msps, 88 dBfOUT = 5MHz, 4MHz Span

THD Total Harmonic Distortion fCLK = 25Msps, fOUT = 1MHz –75 –77 – 84 – 77 dBfCLK = 50Msps, fOUT = 5MHz – 78 dB

4

LTC1666/LTC1667/LTC1668

The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.ELECTRICAL CHARACTERISTICS

LTC1666/LTC1667/LTC1668SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Analog Output

IOUTFS Full-Scale Output Current 1 10 mA

Output Compliance Range IFS = 10mA –1 1 V

Output Resistance; RIOUT A, RIOUT B IOUT A, B to LADCOM 0.7 1.1 1.5 kΩOutput Capacitance 5 pF

Reference Output

Reference Voltage REFOUT Tied to IREFIN Through 2kΩ 2.475 2.5 2.525 V

Reference Output Drift 25 ppm/°C

Reference Output Load Regulation ILOAD = 0mA to 5mA 6 mV/mA

Reference Input

Reference Small-Signal Bandwidth IFS = 10mA, CCOMP1 = 0.1µF 20 kHz

Power Supply

VDD Positive Supply Voltage 4.75 5 5.25 V

VSS Negative Supply Voltage –4.75 –5 –5.25 V

IDD Positive Supply Current IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz 3 5 mA

ISS Negative Supply Current IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz 33 40 mA

PDIS Power Dissipation IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz 180 mWIFS = 1mA, fCLK = 25Msps, fOUT = 1MHz 85 mW

Dynamic Performance (Differential Transformer Coupled Output, 50Ω Double Terminated, Unless Otherwise Noted)

fCLOCK Maximum Update Rate 50 75 Msps

tS Output Settling Time To 0.1% FSR 20 ns

tPD Output Propagation Delay 8 ns

Glitch Impulse Single Ended 15 pV-sDifferential 5 pV-s

tr Output Rise Time 4 ns

tf Output Fall Time 4 ns

iNO Output Noise 50 pA/√Hz

Digital Inputs

VIH Digital High Input Voltage 2.4 V

VIL Digital Low Input Voltage 0.8 V

IIN Digital Input Current ±10 µA

CIN Digital Input Capacitance 5 pF

tDS Input Setup Time 8 ns

tDH Input Hold Time 4 ns

tCLKH Clock High Time 5 ns

tCLKL Clock Low Time 8 ns

Note 1: Absolute Maximum Ratings are those values beyond which the lifeof the device may be impaired.

Note 2: For the LTC1666, ±1LSB = ±0.024% of full scale;for the LTC1667, ±1LSB = ±0.006% of full scale = ±61ppm of full scale;for the LTC1668, ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale.

5

LTC1666/LTC1667/LTC1668

FREQUENCY (MHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

SIGN

AL A

MPL

ITUD

E (d

BFS)

1666/7/8 G01

0 5 10 15 20 25

SFDR = 87dBfCLOCK = 50MSPSfOUT = 1.002MHzAMPL = 0dBFS

= –8.25dBm

TYPICAL PERFOR A CE CHARACTERISTICS

UW

Single Tone SFDR at 50MSPS 2-Tone SFDR

FREQUENCY (MHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

SIGN

AL A

MPL

ITUD

E (d

BFS)

1666/7/8 G02

4.5 5.0 5.5

SFDR > 86dBfCLOCK = 50MSPSfOUT1 = 4.9MHzfOUT2 = 5.09MHzAMPL = 0dBFS

4-Tone SFDR, fCLOCK = 50MSPS

4-Tone SFDR, fCLOCK = 5MSPSSFDR vs fOUT and Digital Amplitude(dBFS) at fCLOCK = 5MSPSSFDR vs fOUT and fCLOCK

FREQUENCY (MHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

SIGN

AL A

MPL

ITUD

E (d

BFS)

1666/7/8 G03

1 4.6 8.2 11.8 15.4 19

SFDR > 74dBfCLOCK = 50MSPSfOUT1 = 5.02MHzfOUT2 = 6.51MHzfOUT3 = 11.02MHzfOUT4 = 12.51MHzAMPL = 0dBFS

FREQUENCY (MHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

SIGN

AL A

MPL

ITUD

E (d

BFS)

1666/7/8 G04

0.1 0.46 0.82 1.18 1.54 1.9

SFDR > 82dBfCLOCK = 5MSPSfOUT1 = 0.5MHzfOUT2 = 0.65MHzfOUT3 = 1.10MHzfOUT4 = 1.25MHzAMPL = 0dBFS

fOUT (MHz)0.1

SFDR

(dB)

100

90

80

70

60

501.0 10 100

1666/7/8 G05

5MSPS

25MSPS

50MSPS


fOUT (MHz)

100

95

90

85

80

75

70

65

60

55

50

SFDR

(dB)

1666/7/8 G06

0 0.4 0.8 1.2 1.6 2.0

–12dBFS

–6dBFS

0dBFS

(LTC1668)

fOUT (MHz)0

SFDR

(dB)

4 8 10

95

90

85

80

75

70

65

60

55

50

1666/7/8 G07

2 6

–12dBFS

–6dBFS

0dBFS

fOUT (MHz)0

SFDR

(dB)

10 20

90

85

80

75

70

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60

55

50

1666/7/8 G08

5 15

–12dBFS –6dBFS

0dBFS

fOUT (MHz)0

SFDR

(dB)

10

95

90

85

80

75

70

65

60

55

50

1666/7/8 G09

2.5 5 7.5


IOUTFS = 2.5mA

IOUTFS = 5mA

IOUTFS = 10mA

SFDR vs fOUT and Digital Amplitude(dBFS) at fCLOCK = 25MSPS

SFDR vs fOUT and Digital Amplitude(dBFS) at fCLOCK = 50MSPS

SFDR vs fOUT and IOUTFS atfCLOCK = 25MSPS

6

LTC1666/LTC1667/LTC1668

Integral Nonlinearity

DIGITAL INPUT CODE

–5

INTE

GRAL

NON

LINE

ARIT

Y (L

SB)

–4

–2

–1

0

5

2

16384 32768

1666/7/8 G18

–3

3

4

1

49152 65535


UW

SFDR vs Digital Amplitude (dBFS)and fCLOCK at fOUT = fCLOCK/11

Single-Ended OutputsFull-Scale Transition

Differential OutputFull-Scale Transition

Single-Ended OutputFull-Scale Transition

Differential OutputFull-Scale Transition

Differential MidscaleGlitch Impulse

Single-Ended MidscaleGlitch Impulse

DIGITAL AMPLITUDE (dBFS)

100

95

90

85

80

75

70

65

60

55

50

SFDR

(dB)

1666/7/8 G10

–20 –15 –10 –5 0

455kHz AT 5MSPS

4.55MHz AT 50MSPS

2.277MHz AT 25MSPS

DIGITAL AMPLITUDE (dBFS)

100

95

90

85

80

75

70

65

60

55

50

SFDR

(dB)

1666/7/8 G11

–20 –15 –10 –5 0

1MHz AT 5MSPS

10MHz AT 50MSPS

5MHz AT 25MSPS

100mV/DIV

CLK IN5V/DIV

1666/7/8 G12

5ns/DIV

V(IOUTB)

V(IOUTA)

FFFF0000

CLOCK INPUT

SFDR vs Digital Amplitude (dBFS)and fCLOCK at fOUT = fCLOCK/5

100mV/DIV

CLK IN5V/DIV

1666/7/8 G13

5ns/DIV

V(IOUTA) – V(IOUTB)

FFFF0000 100mV/DIV

CLK IN5V/DIV

1666/7/8 G14

5ns/DIV

V(IOUTA)

V(IOUTB)

FFFF 0000

CLOCK INPUT

100mV/DIV

CLK IN5V/DIV

1666/7/8 G15

5ns/DIV


FFFF 0000

1mV/DIV

CLK IN5V/DIV

1666/7/8 G16

5ns/DIV

V(IOUTA), V(IOUTB)

7FFF 8000

1mV/DIV

CLK IN5V/DIV

1666/7/8 G17

5ns/DIV


7FFF 8000

(LTC1668)

7

LTC1666/LTC1667/LTC1668


UW

Differential Nonlinearity

DIGITAL INPUT CODE0

DIFF

EREN

TIAL

NON

LINE

ARIT

Y (L

SB)

0

1.0

65535

1666/7/8 G19

–1.0

–2.016384 32768 49152

2.0

–0.5

0.5

–1.5

1.5

(LTC1668)

UUU

PI FU CTIO SLTC1666

REFOUT (Pin 15): Internal Reference Voltage Output.Nominal value is 2.5V. Requires a 0.1µF bypass capacitorto AGND.

IREFIN (Pin 16): Reference Input Current. Nominal value is1.25mA for IFS = 10mA. IFS = IREFIN • 8.

AGND (Pin 17): Analog Ground.

LADCOM (Pin 18): Attenuator Ladder Common. Normallytied to GND.

IOUT B (Pin 19): Complementary DAC Output Current. Full-scale output current occurs when all data bits are 0s.

IOUT A (Pin 20): DAC Output Current. Full-scale outputcurrent occurs when all data bits are 1s.

COMP1 (Pin 21): Current Source Control Amplifier Com-pensation. Bypass to VSS with 0.1µF.

COMP2 (Pin 22): Internal Bypass Point. Bypass to VSSwith 0.1µF.

VSS (Pin 23): Negative Supply Voltage. Nominal value is–5V.

DGND (Pin 24): Digital Ground.

VDD (Pin 25): Positive Supply Voltage. Nominal value is 5V.

CLK (Pin 26): Clock Input. Data is latched and the outputis updated on positive edge of clock.

DB11 to DB0 (Pins 27, 28, 1 to 10 ): Digital Input Data Bits.

8

LTC1666/LTC1667/LTC1668

LTC1667














LTC1668














UUU

PI FU CTIO S

9

LTC1666/LTC1667/LTC1668

BLOCK DIAGRA

W

–

+

IFS/8IREFIN

IINT

RSET2k

0.1µF

0.1µF

0.1µF–5V

0.1µF

REFOUT

VDD

VREF 15

16

COMP121

COMP2

VSS

22

23

2.5VREFERENCE

ATTENUATORLADDER

LSB SWITCHES

INPUT LATCHES

CLOCKINPUT 12-BIT

DATA INPUT

SEGMENTED SWITCHESFOR DB15–DB12

CURRENT SOURCE ARRAY

AGND

17

DGND

24

CLK DB0DB11 • • •

• • •

• • • • • •

26 27 10 1666 BD

18LADCOM

20IOUT A

19IOUT B

52.3Ω 52.3ΩVOUT1VP-PDIFFERENTIAL

+

–

0.1µF

25

5V

–

+

IFS/8IREFIN

IINT

RSET2k

0.1µF

0.1µF

0.1µF–5V

0.1µF

REFOUTVREF 15

16

COMP121

COMP2

VSS

22

23

2.5VREFERENCE

ATTENUATORLADDER

LSB SWITCHES

INPUT LATCHES

CLOCKINPUT 14-BIT

DATA INPUT



AGND

17

DGND

24


• • •

• • • • • •

26 27 12 1667 BD

18LADCOM

20IOUT A

19IOUT B


+

–

0.1µF

25

5V

VDD

LTC1666

LTC1667

10

LTC1666/LTC1667/LTC1668

BLOCK DIAGRA

W

TI I G DIAGRAUW W

1666/7/8 TD

tDS tDH

CLK

N – 1

N – 1 N

N N + 1DATAINPUT

IOUT A/IOUT B

tCLKL tCLKH

tPD

0.1%

tST

–

+

IFS/8IREFIN

IINT

RSET2k

0.1µF

0.1µF

0.1µF–5V

0.1µF

REFOUTVREF 15

16

COMP121

COMP2

VSS

22

23

2.5VREFERENCE

ATTENUATORLADDER

LSB SWITCHES

INPUT LATCHES

CLOCKINPUT 16-BIT

DATA INPUT



AGND

17

DGND

24


• • •

• • • • • •

26 27 14 1668 BD

18LADCOM

20IOUT A

19IOUT B


+

–

0.1µF

25

5V

VDD

LTC1668

11

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

WU UU

Theory of Operation

The LTC1666/LTC1667/LTC1668 are high speed currentsteering 12-/14-/16-bit DACs made on an advancedBiCMOS process. Precision thin film resistors and wellmatched bipolar transistors result in excellent DC linearityand stability. A low glitch current switching design givesexcellent AC performance at sample rates up to 50Msps.The devices are complete with a 2.5V internal bandgapreference and edge triggered latches, and set a newstandard for DAC applications requiring very high dy-namic range at output frequencies up to several mega-hertz.

Referring to the Block Diagrams, the DACs contain anarray of current sources that are steered to IOUTA or IOUTBwith NMOS differential current switches. The four mostsignificant bits are made up of 15 current segments ofequal weight. The remaining lower bits are binary weighted,using a combination of current scaling and a differentialresistive attenuator ladder. All bits and segments areprecisely matched, both in current weight for DC linearity,and in switch timing for low glitch impulse and lowspurious tone AC performance.

Setting the Full-Scale Current, IOUTFS

The full-scale DAC output current, IOUTFS, is nominally10mA, and can be adjusted down to 1mA. Placing aresistor, RSET, between the REFOUT pin, and the IREFIN pinsets IOUTFS as follows.

The internal reference control loop amplifier maintains avirtual ground at IREFIN by servoing the internal currentsource, IINT, to sink the exact current flowing into IREFIN.IINT is a scaled replica of the DAC current sources andIOUTFS = 8 • (IINT), therefore:

IOUTFS = 8 • (IREFIN) = 8 • (VREF/RSET) (1)

For example, if RSET = 2k and is tied to VREF = REFOUT =2.5V, IREFIN = 2.5/2k = 1.25mA and IOUTFS = 8 • (1.25mA)= 10mA.

The reference control loop requires a capacitor on theCOMP1 pin for compensation. For optimal AC perfor-mance, CCOMP1 should be connected to VSS and be placedvery close to the package (less than 0.1").

For fixed reference voltage applications, CCOMP1 shouldbe 0.1µF or more. The reference control loop small-signalbandwidth is approximately 1/(2π) • CCOMP1 • 80 or 20kHzfor CCOMP1 = 0.1µF.

Reference Operation

The onboard 2.5V bandgap voltage reference drives theREFOUT pin. It is trimmed and specified to drive a 2kresistor tied from REFOUT to IREFIN, corresponding to a1.25mA load (IOUTFS = 10mA). REFOUT has nominaloutput impedance of 6Ω, or 0.24% per mA, so it must bebuffered to drive any additional external load. A 0.1µFcapacitor is required on the REFOUT pin for compensa-tion. Note that this capacitor is required for stability, evenif the internal reference is not being used.

External Reference Operation

Figure 1, shows how to use an external reference to controlthe LTC1666/LTC1667/LTC1668 full-scale current.

Figure 1. Using the LTC1666/LTC1667/LTC1668with an External Reference

REFOUT

+

–

IREFIN

2.5VREFERENCE

RSET

0.1µF5V

1666/7/8 F02

EXTERNALREFERENCE

LTC1666/LTC1667/LTC1668

12

LTC1666/LTC1667/LTC1668

Adjusting the Full-Scale Output

In Figure 2, a serial interfaced DAC is used to set IOUTFS.The LTC1661 is a dual 10-bit VOUT DAC with a bufferedvoltage output that swings from 0V to VREF.

DAC Transfer Function

The LTC1666/LTC1667/LTC1668 use straight binary digitalcoding. The complementary current outputs, IOUT A and IOUTB, sink current from 0 to IOUTFS. For IOUTFS = 10mA (nomi-nal), IOUT A swings from 0mA when all bits are low (e.g.,Code = 0) to 10mA when all bits are high (e.g., Code = 65535for LTC1668) (decimal representation). IOUT B is comple-mentary to IOUT A. IOUT A and IOUT B are given by the followingformulas:

LTC1666:

IOUT A = IOUTFS • (DAC Code/4096) (2)

IOUT B = IOUTFS • (4095 – DAC Code)/4096 (3)

LTC1667:



LTC1668:



In typical applications, the LTC1666/LTC1667/LTC1668differential output currents either drive a resistive loaddirectly or drive an equivalent resistive load through atransformer, or as the feedback resistor of an I-to-Vconverter. The voltage outputs generated by the IOUT A andIOUT B output currents are then:

Figure 2. Adjusting the Full-Scale Current ofthe LTC1666/LTC1667/LTC1668 with a DAC


WU UU

VOUT A = IOUT A • RLOAD (8)

VOUT B = IOUT B • RLOAD (9)

The differential voltage is:

VDIFF = VOUT A – VOUT B (10) = (IOUT A – IOUT B) • (RLOAD)

Substituting the values found earlier for IOUT A, IOUT B andIOUTFS (LTC1668):

VDIFF = 2 • DAC Code – 65535)/65536 • 8 •(RLOAD/RSET) • (VREF) (11)

From these equations some of the advantages of differen-tial mode operation can be seen. First, any common modenoise or error on IOUT A and IOUT B is cancelled. Second, thesignal power is twice as large as in the single-ended case.Third, any errors and noise that multiply times IOUT A andIOUT B, such as reference or IOUTFS noise, cancel nearmidscale, where AC signal waveforms tend to spend themost time. Fourth, this transfer function is bipolar; e.g. theoutput swings positive and negative around a zero outputat mid-scale input, which is more convenient for ACapplications.

Note that the term (RLOAD/RSET) appears in both thedifferential and single-ended transfer functions. This meansthat the Gain Error of the DAC depends on the ratio ofRLOAD to RSET, and the Gain Error tempco is affected by thetemperature tracking of RLOAD with RSET. Note also thatthe absolute tempco of RLOAD is very critical for DCnonlinearity. As the DAC output changes from 0mA to10mA the RLOAD resistor will heat up slightly, and even avery low tempco can produce enough INL bowing to besignificant at the 16-bit level. This effect disappears withmedium to high frequency AC signals due to the slowthermal time constant of the load resistor.

Analog Outputs

The LTC1666/LTC1667/LTC1668 have two complemen-tary current outputs, IOUT A and IOUT B (see DAC TransferFunction). The output impedance of IOUT A and IOUT B(RIOUT A and RIOUT B) is typically 1.1kΩ to LADCOM. (SeeFigure 3.)

+

–

IREFIN

2.5VREFERENCE

RSET1.9k

REF0.1µF

1/2 LTC1661

5V

1666/7/8 F03

LTC1666/LTC1667/LTC1668

13

LTC1666/LTC1667/LTC1668


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LADCOM

The LADCOM pin is the common connection for theinternal DAC attenuator ladder. It usually is tied to analogground, but more generally it should connect to the samepotential as the load resistors on IOUT A and IOUT B. TheLADCOM pin carries a constant current to VSS of approxi-mately 0.32 • (IOUTFS), plus any current that flows fromIOUT A and IOUT B through the RIOUT A and RIOUT B resistors.

Output Compliance

The specified output compliance voltage range is ±1V. TheDC linearity specifications, INL and DNL, are trimmed andguaranteed on IOUT A into the virtual ground of anI-to-V converter, but are typically very good over the fulloutput compliance range. Above 1V the output current willstart to increase as the DAC current steering switchimpedance decreases, degrading both DC and AC linear-ity. Below –1V, the DAC switches will start to approach thetransition from saturation to linear region. This will de-grade AC performance first, due to nonlinear capacitanceand increased glitch impulse. AC distortion performanceis optimal at amplitudes less than ±0.5VP-P on IOUT A andIOUT B due to nonlinear capacitance and other large-signaleffects. At first glance, it may seem counter-intuitive todecrease the signal amplitude when trying to optimizeSFDR. However, the error sources that affect AC perfor-mance generally behave as additive currents, so decreas-ing the load impedance to reduce signal voltage amplitudewill reduce most spurious signals by the same amount.

Figure 4. AC Characterization Setup (LTC1668)

–

+ 16-BITHIGH SPEED

DAC

HP1663EALOGIC ANALYZER WITHPATTERN GENERATOR

VSS

VDD

–5V

LADCOM

AGND DGND CLK DB15 DB0

16

DIGITALDATA

CLKIN

1666/7/8 F05

IOUT A

0.1µF

LTC1668

5V

IREFIN

REFOUT

COMP1

COMP2

C20.1µF

0.1µF

OUT 1 OUT 2

C10.1µF

RSET2k

IOUT B

HP8110A DUALPULSE GENERATOR

LOW JITTERCLOCK SOURCE

CLKIN

50Ω

0.1µF

50Ω

TO HP3589ASPECTRUMANALYZER50Ω INPUT

110Ω

MINI-CIRCUITST1–1T

2.5VREFERENCE

Figure 3. Equivalent Analog Output Circuit

20

19

23

18RIOUT B

1.1k

5pF 5pF

–5V1666/7/8 F04

RIOUT A1.1k

LADCOM

IOUT A

IOUT B

VSS

52.3Ω

52.3Ω

LTC1666/LTC1667/LTC1668

14

LTC1666/LTC1667/LTC1668


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Operating with Reduced Output Currents

The LTC1666/LTC1667/LTC1668 are specified to operatewith full-scale output current, IOUTFS, from the nominal10mA down to 1mA. This can be useful to reduce powerdissipation or to adjust full-scale value. However, the DCand AC accuracy is specified only at IOUTFS = 10mA, andDC and AC accuracy will fall off significantly at lower IOUTFSvalues. At IOUTFS = 1mA, the LTC1668 INL and DNLtypically degrade to the 14-bit to 13-bit level, compared to16-bit to 15-bit typical accuracy at 10mA IOUTFS. Increas-ing IOUTFS from 1mA, the accuracy improves rapidly,roughly in proportion to 1/IOUTFS. Note that the AC perfor-mance (SFDR) is affected much more by reduced IOUTFSthan it is by reduced digital amplitude (see Typical Perfor-mance Characteristics). Therefore it is usually better tomake large gain adjustments digitally, keeping IOUTFSequal to 10mA.

Output Configurations

Based on the specific application requirements, theLTC1666/LTC1667/LTC1668 allow a choice of the best ofseveral output configurations. Voltage outputs can begenerated by external load resistors, transformer couplingor with an op amp I-to-V converter. Single-ended DACoutput configurations use only one of the outputs, prefer-ably IOUT A, to produce a single-ended voltage output.Differential mode configurations use the difference be-tween IOUT A and IOUT B to generate an output voltage,VDIFF, as shown in equation 11. Differential mode givesmuch better accuracy in most AC applications. Becausethe DAC chip is the point of interface between the digitalinput signals and the analog output, some small amountof noise coupling to IOUT A and IOUT B is unavoidable. Mostof that digital noise is common mode and is canceled bythe differential mode circuit. Other significant digital noisecomponents can be modeled as VREF or IOUTFS noise. Insingle-ended mode, IOUTFS noise is gone at zero scale andis fully present at full scale. In differential mode, IOUTFSnoise is cancelled at midscale input, corresponding to zeroanalog output. Many AC signals, including broadband andmultitone communications signals with high peak to aver-age ratios, stay mostly near midscale.

Differential Transformer-Coupled Outputs

Differential transformer-coupled output configurationsusually give the best AC performance. An example isshown in Figure 5. The advantages of transformer cou-pling include excellent rejection of common mode distor-tion and noise over a broad frequency range and conve-nient differential-to-single-ended conversion with isola-tion or level shifting. Also, as much as twice the power canbe delivered to the load, and impedance matching can beaccomplished by selecting the appropriate transformerturns ratio. The center tap on the primary side of thetransformer is tied to ground to provide the DC currentpath for IOUT A and IOUT B. For low distortion, the DCaverage of the IOUT A and IOUT B currents must be exactlyequal to avoid biasing the core. This is especially impor-tant for compact RF transformers with small cores. Thecircuit in Figure 5 uses a Mini-Circuits T1-1T RF trans-former with a 1:1 turns ratio. The load resistance onIOUT A and IOUT B is equivalent to a single differentialresistor of 50Ω, and the 1:1 turns ratio means the outputimpedance from the transformer is 50Ω. Note that theload resistors are optional, and they dissipate half of theoutput power. However, in lab environments or whendriving long transmission lines it is very desirable to havea 50Ω output impedance. This could also be done with a50Ω resistor at the transformer secondary, but puttingthe load resistors on IOUT A and IOUT B is preferred sinceit reduces the current through the transformer. At signalfrequencies lower than about 1MHz, the transformer coresize required to maintain low distortion gets larger, and atsome lower frequencies this becomes impractical.

Figure 5. Differential Transformer-Coupled Outputs

IOUT B

IOUT A

50Ω

50Ω

110Ω

MINI-CIRCUITST1-1T

RLOAD

1666/7/8 F06

LTC1666/LTC1667/LTC1668

15

LTC1666/LTC1667/LTC1668


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Resistor Loaded Outputs

A differential resistor loaded output configuration is shownin Figure 6. It is simple and economical, but it can driveonly differential loads with impedance levels and ampli-tudes appropriate for the DAC outputs.

The recommended single-ended resistor loaded configu-ration is essentially the same circuit as the differentialresistor loaded, case—simply use the IOUT A output,referred to ground. Rather than tying the unused IOUT Boutput to ground, it is preferred to load it with the equiva-lent RLOAD of IOUT A. Then IOUT B will still swing with awaveform complementary to IOUT A.

helps reduce distortion by limiting the high frequencysignal amplitude at the op amp inputs. The circuit swings±1V around ground.

Figure 8 shows a simplified circuit for a single-endedoutput using I-to-V converter to produce a unipolarbuffered voltage output. This configuration typically hasthe best DC linearity performance, but its AC distortion athigher frequencies is limited by U1’s slewing capabilities.

Digital Interface

The LTC1666/LTC1667/LTC1668 have parallel inputs thatare latched on the rising edge of the clock input. Theyaccept CMOS levels from either 5V or 3.3V logic and canaccept clock rates of up to 50MHz.

Referring to the Timing Diagram and Block Diagram, thedata inputs go to master-slave latches that update on therising edge of the clock. The input logic thresholds, VIH =2.4V min, VIL = 0.8V max, work with 3.3V or 5V CMOSlevels over temperature. The guaranteed setup time, tDS,is 8ns minimum and the hold time, tDH, is 4ns minimum.The minimum clock high and low times are guaranteed at6ns and 8ns, respectively. These specifications allow theLTC1666/LTC1667/LTC1668 to be clocked at up to 50Mspsminimum.

For best AC performance, the data and clock waveformsneed to be clean and free of undershoot and overshoot.Clock and data interconnect lines should be twisted pair,coax or microstrip, and proper line termination is impor-tant. If the digital input signals to the DAC are consideredas analog AC voltage signals, they are rich in spectralcomponents over a broad frequency range, usually in-

Op Amp I to V Converter Outputs

Adding an op amp differential to single-ended convertercircuit to the differential resistor loaded output gives thecircuit of Figure 7.

This circuit complements the capabilities of the trans-former-coupled application at lower frequencies, sinceavailable op amps can deliver good AC distortion perfor-mance at signal frequencies of a few MHz down to DC. Theoptional capacitor adds a single real pole of filtering, and

Figure 6. Differential Resistor-Loaded Output

IOUT B

IOUT A

52.3Ω52.3Ω

1666/7/8 F07

LTC1666/LTC1667/LTC1668

Figure 8. Single-Ended Op Amp I to V Converter

200Ω

1666/7/8 F09

IOUT A

IOUT B

LADCOM

RFB200Ω

VOUT0V TO 2V

IOUTFS10mA

COUT

–

+U1

LT®1812LTC1666/LTC1667/LTC1668

IOUT B

IOUT A

52.3Ω 500Ω52.3Ω

1666/7/8 F08

–

+

200Ω

500Ω

200Ω

60pF LT1809±1V

10dBm

VOUT

LTC1666/LTC1667/LTC1668

Figure 7. Differential to Single-Ended Op Amp I-V Converter

16

LTC1666/LTC1667/LTC1668


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cluding the output signal band of interest. Therefore, anydirect coupling of the digital signals to the analog outputwill produce spurious tones that vary with the exact digitalinput pattern.

Clock jitter should be minimized to avoid degrading thenoise floor of the device in AC applications, especiallywhere high output frequencies are being generated. Anynoise coupling from the digital inputs to the clock input willcause phase modulation of the clock signal and the DACwaveform, and can produce spurious tones. It is normallybest to place the digital data transitions near the fallingclock edge, well away from the active rising clock edge.Because the clock signal contains spectral componentsonly at the sampling frequency and its multiples, it isusually not a source of in band spurious tones. Overall, itis better to treat the clock as you would an analog signaland route it separately from the digital data input signals.The clock trace should be routed either over the analogground plane or over its own section of the ground plane.The clock line needs to have accurately controlled imped-ance and should be well terminated near the LTC1666/LTC1667/LTC1668.

Printed Circuit Board Layout Considerations—Grounding, Bypassing and Output Signal Routing

The close proximity of high frequency digital data lines andhigh dynamic range, wide-band analog signals makesclean printed circuit board design and layout an absolute

necessity. Figures 11 to 15 are the printed circuit boardlayers for an AC evaluation circuit for the LTC1668. Groundplanes should be split between digital and analog sectionsas shown. All bypass capacitors should have minimumtrace length and be ceramic 0.1µF or larger with low ESR.

Bypass capacitors are required on VSS, VDD and REFOUT,and all connected to the AGND plane. The COMP2 pin tiesto a node in the output current switching circuitry, and itrequires a 0.1µF bypass capacitor. It should be bypassedto VSS along with COMP1. The AGND and DGND pinsshould both tie directly to the AGND plane, and the tie pointbetween the AGND and DGND planes should nominally benear the DGND pin. LADCOM should either be tied directlyto the AGND plane or be bypassed to AGND. The IOUT A andIOUT B traces should be close together, short, and wellmatched for good AC CMRR. The transformer outputground should be capable of optionally being isolated orbeing tied to the AGND plane, depending on which givesbetter performance in the system.

Suggested Evaluation Circuit

Figure 10 is the schematic and Figures 11 to 15 are thecircuit board layouts for a suggested evaluation circuit,DC245A. The circuit can be programmed with componentselection and jumpers for a variety of differentially coupledtransformer output and differential and single-ended re-sistor loaded output configurations.

REFOUT LADCOMIOUT A

VOUT

IOUT BIREFIN CLK

LTC1668U2

Q-CHANNEL

REFOUT LADCOMIOUT A

IOUT BIREFIN CLK

LTC1668U1

I-CHANNEL

52.3Ω

52.3Ω52.3Ω

52.3Ω

LOW-PASSFILTER

LOW-PASSFILTER

CLOCKINPUT

REF

1/2 LTC1661U3

SERIALINPUT

2k

2.1k

21k

0.1µF

0.1µF

90° ∑

LOCALOSCILLATOR

QAMOUTPUT

QUADRATUREMODULATOR

±5%RELATIVE GAIN

ADJUSTMENT RANGE

1666/7/8 F10

Figure 9. QAM Modulation Using LTC1668 withDigitally Controlled I vs Q Channel Gain Adjustment

17

LTC1666/LTC1667/LTC1668


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Figu

re 1

0. S

ugge

sted

Eva

luat

ion

Circ

uit

J4 V OUT

J5 I OUT

B

J6 EXTC

LK

JP9

12

3

1516

R3 1.91

k0.

1%R2 200Ω

JP1

C17

0.1µ

FLT

C166

8

20 19 21 22 2318

C7 0.1µ

F

5V–5

V

TP5

TEST

POIN

T W

HT

C3 0.1µ

FC1

80.

1µF

25 17 24

C10

0.1µ

FC1

10.

1µF

R9 50Ω

0.1%

R12

49.9

Ω 1%

JP6

R10

50Ω

0.1%

C12

22pF

C12

22pF

C90.

1µF

C8 0.1µ

F

C8 0.1µ

F

JP5

TP3

TEST

POIN

T W

HT

JP7

JP3

R5R6

R7 110Ω

JP4

JP2

5V

REFO

UTRE

FIN

27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 26

DB15

(MSB

)DB

14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

(LSB

)

CLK

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

I OUT

A

I OUT

B

COM

P1

COM

P2 V SS

LADC

OM V DD

AGND

DGND

R4

J2 I OUT

A

C4R8

3 2 1

4T1 MIN

I- CI

RCUI

TST1

–1T6

C5

JP8

TP4

TEST

POIN

TW

HT

2 4 6

1 3 5

RN5

+5VD

22Ω

+5VD

J7 J10

TP6

TEST

POIN

T RE

D4

2

5V

6

LT14

60DC

S8-2

.5

AMP

1021

59-9

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

RN6

22Ω

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

TP2

TEST

POIN

T W

HT2.

5VRE

F

TP10

TEST

POIN

T BL

KTP

1

V IN

V OUT

GND

C20.

1µF

C1 0.1µ

F

J1EX

TREF

R1 10Ω

+C1

90.

1µF

C14

10µF

25V

–5V

AGND

DGND

J9

TP8

TEST

POIN

T RE

D

GROU

ND P

LANE

TIE

POIN

T

+

C20

0.1µ

F

C16

10µF

25V

1666

/7/8

F11

C22

0.1µ

F

+5VA

J8 J11

TP7

TEST

POIN

T RE

D

TP9

TEST

POIN

T BL

K

+C2

30.

1µF

C15

10µF

25V

C21

0.1µ

F

OPTI

ONAL

SIP

PULL

-UP/

PULL

-DOW

NRE

SIST

ORS

(NOT

IN

STAL

LED)

OPTI

ONAL

SIP

PULL

-UP/

PULL

-DOW

NRE

SIST

ORS

(NOT

IN

STAL

LED)

+5VD

R16

0ΩR15

0ΩR14

0ΩR13

0Ω

18

LTC1666/LTC1667/LTC1668


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Figure 11. Suggested Evaluation Circuit Board—Silkscreen

19

LTC1666/LTC1667/LTC1668

Figure 12. Suggested Evaluation Circuit Board—Component Side


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20

LTC1666/LTC1667/LTC1668


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Figure 13. Suggested Evaluation Circuit Board—GND Plane

21

LTC1666/LTC1667/LTC1668


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Figure 14. Suggested Evaluation Circuit Board—Power Plane

22

LTC1666/LTC1667/LTC1668

Figure 15. Suggested Evaluation Circuit Board—Solder Side


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23

LTC1666/LTC1667/LTC1668

U

PACKAGE DESCRIPTIO

G28 SSOP 0501

.13 – .22(.005 – .009)

0° – 8°

.55 – .95(.022 – .037)

5.20 – 5.38**(.205 – .212)

7.65 – 7.90(.301 – .311)

1 2 3 4 5 6 7 8 9 10 11 12 1413

10.07 – 10.33*(.397 – .407)

2526 22 21 20 19 18 17 16 1523242728

1.73 – 1.99(.068 – .078)

.05 – .21(.002 – .008)

.65(.0256)

BSC.25 – .38

(.010 – .015)

MILLIMETERS(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

*

**

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

G Package28-Lead Plastic SSOP (5.3mm)(Reference LTC DWG # 05-08-1640)

24

LTC1666/LTC1667/LTC1668

LINEAR TECHNOLOGY CORPORATION 2000

166678f LT/TP 0701 2K • PRINTED IN USALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com

RELATED PARTS

TYPICAL APPLICATIO

U

Figure 16. Arbitrary Waveform Generator Has ±10V Output Swing, 50Msps DAC Update Rate

REFOUT LADCOM

IOUT A

IOUT B

IREFIN LTC1668

52.3Ω 52.3Ω

RSET2k –

+

VSS AGND DGND CLK DB15-DB0

COMP1COMP2

0.1µF

0.1µF

0.1µF

–5V

5V

CLOCKINPUT

18-BITDATAINPUT

VDD

100pF LT1227

1k

VOUT±10V

1666/7/8 F17

1k

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC1406 8-Bit, 20Msps ADC Undersampling Capability Up to 70MHz Input

LTC1411 14-Bit, 2.5Msps ADC

LTC1420 12-Bit, 10Msps ADC 72dB SINAD at 5MHz fINLTC1604/LTC1608 16-Bit, 333ksps/500ksps ADCs 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD

DACs

LTC1591/LTC1597 Parallel 14/16-Bit Current Output DACs On-Chip 4-Quadrant Resistors

LTC1595/LTC1596 Serial 16-Bit Current Output DACs Low Glitch, ±1LSB Maximum INL, DNL

LTC1650 Serial 16-Bit Voltage Output DAC Low Power, Deglitched, 4-Quadrant Multiplying VOUT DAC,±4.5V Output Swing, 4µs Settling Time

LTC1655(L) Single 16-Bit VOUT DAC with Serial Interface in SO-8 5V (3V) Single Supply, Rail-to-Rail Output Swing

LTC1657(L) 16-Bit Parallel Voltage Output DAC 5V (3V) Low Power, 16-Bit Monotonic Over Temp., Multiplying Capability

AMPLIFIERs

LT1809/LT1810 Single/Dual 180MHz, 350V/µs Op Amp Rail-to-Rail Input and Output, Low Distortion

LT1812/LT1813 Single/Dual 100MHz, 750V/µs Op Amp 3.6mA Supply Current, 8nV/√Hz Input Noise Voltage

Documents

LTC1666/LTC1667/LTC1668 - 12-Bit, 14-Bit, 16-Bit, 50Msps DACs · directly to external resistors to produce a differential out-put voltage without degrading the converter’s linearity