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Lou Ternullo – Product Marketing Director - Cadence Design SystemsOctober 15, 2014
LPDDR4 – It’s not just for mobile anymore
2 © 2014 Cadence Design Systems, Inc. All rights reserved.
Storage
• RAID
• SSD
Networking
• Network Storage
• Network Processors
Consumer
• HDTV
• Camera
• Display
Industrial, Medical, Instrumentation, FPGAs• Tester equipment
• FPGAs
Mobile
• Tablets/ cell phones
• Wearables
DRAM Consumption by Application
DDR3 ->DDR4
DDR3 -> DDR4
DDR3 -> DDR4
DDR3 -> DDR4
LPDDR3 -> LPDDR4
1. Density
2. Performance
3. Power
1. Density
2. Performance
3. Power
1. Cost
2. Performance
3. Power
1. Reliability
2. Power
3. Cost
1. Power
2. Performance
3. Cost
ApplicationProtocol
Transition Requirements
3 © 2014 Cadence Design Systems, Inc. All rights reserved.
• Typical Consumer products– HDTV
– Set top Box
– Blue ray players
– Printers…..
• Typical off chip memory (DRAM) requirements – Cost – cost competitive markets
– Performance – continuous increasing performance requirements
– Density - ~ 1GB DRAM density
– Interface/bandwidth: typical interfaces are 32 bits wide
Typical Consumer Product DRAM Requirements
4 © 2014 Cadence Design Systems, Inc. All rights reserved.
DRAM Cost Requirements for Consumer Products
5 © 2014 Cadence Design Systems, Inc. All rights reserved.
DRAM Industry TrendsSupply and demand impacts cost
• Increase in mobile DRAM bit consumption
• IHS: “Mobile devices to surpass PCs in DRAM consumption by 2015”
• Introduction of Uni-DIMM at IDF- LP DRAM on a DIMM
DDR3DDR4
Mobile DRAM • Mobile DRAM growthDDR2
DDR
SDR
Graphics
Source:IHS
Potential Path to Lower Cost LP-DRAM
6 © 2014 Cadence Design Systems, Inc. All rights reserved.
DRAM Density Requirements for Consumer Products
7 © 2014 Cadence Design Systems, Inc. All rights reserved.
• Density requirements drive selection of x16 DRAM
• Typical system density requirements ~ 1GB
DDR4 Consumer Product System ScenariosTypical 32 bit DRAM interface
SoC
DDR PHY
DDR
Controller
DDR4 x16
DDR4 x16PCB
SoC
DDR PHY
DDR
Controller
DDR4 x8PCB
Protocol Density/ DRAM # DRAMs Total DRAM
Density
DDR4 X8 4Gb – 8 Gb 4 2 GB – 4GB
DDR4x16 4Gb – 8Gb 2 1 GB – 2 GB
DDR4 x8
DDR4 x8
DDR4 x8
8 © 2014 Cadence Design Systems, Inc. All rights reserved.
• LPDDR4 x32 DRAM is an option to meet density requirements
• LPDDR4 DRAM satisfy typical system density requirements ~ 1GB
Alternate Consumer Product System Scenarios
SoC
DDR PHY
DDR
Controller
DDR4 x16
DDR4 x16PCB
Protocol Density/ DRAM # DRAMs Total DRAM
Density
DDR4x16 4Gb – 8Gb 2 1 GB – 2 GB
LPDDR4x32 6Gb – 8Gb 1 0.75 GB – 1 GB
LPDDR4x32 2 rank 12Gb – 16Gb 2 (stacked) 1.5 GB – 2 GB
SoC
DDR PHY
DDR
Controller
LPDDR4 x32PCB LPDDR4
x32
1 or 2 ranks
9 © 2014 Cadence Design Systems, Inc. All rights reserved.
DRAM Performance Requirements for Consumer Products
10 © 2014 Cadence Design Systems, Inc. All rights reserved.
LPDDR4 DRAM performance out pacing DDR4
2.4 Gbps
2.6 Gbps
11 © 2014 Cadence Design Systems, Inc. All rights reserved.
DDR4 DRAM Timing ComparisonNumber of Clock Cycles
Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2667(1)
nRRDSx8 4 4 4 4 4
x16 5 5 6 7 8
nRRDLx8 5 5 6 6 7
x16 6 6 7 8 9
tCCD_S (min) 4 4 4 4 4
tCCD_L (min) 5 5 6 6 7
• tRRD_S: ACTIVATE to ACTIVATE Command delay to a different bank group
• tRRD_L: ACTIVATE to ACTIVATE Command delay to same bank group
• tCCD_S: CAS_n to CAS_n command delay for different bank group
• tCCD_L: CAS_n to CAS_n command delay for the same bank group
• Optimal DDR4 tCCD is 4 clock cycles to align with BL 8(1) Projected timings for DDR4-2667
12 © 2014 Cadence Design Systems, Inc. All rights reserved.
Introduction to DDR4 Bank GroupsDDR4 X8 DRAM Devices
• DDR4 DRAMs are architected
with Banks and Bank Groups
• X8 DRAM devices have 2 Bank
address bits and 2 Bank group
bits
• Timing differences exist across
banks accesses
− Longer timing within the same bank
group. IE B0 to B1 – tCCD_L
− Shorter time across bank groups. IE
BG0 to BG1 – tCCD_S
• DDR controller address
mechanism must take Bank
Group restrictions into account
B0 B1
B2 B3
B0 B1
B2 B3
B0 B1
B2 B3
B0 B1
B2 B3
BG0 BG1
BG2 BG3
tCCD_S
tCCD_S
tCC
D_L
13 © 2014 Cadence Design Systems, Inc. All rights reserved.
DDR4 Bank GroupsDDR4 X16 DRAM Devices
• X16 DRAM devices have 3 bank
address bits and 1 bank group
bit
• X16 devices increase the
probability of back to back
commands in the same bank
group
B0 B1
B2 B3
B0 B1
B2 B3
B4 B5
B6 B7
B4 B5
B6 B7
BG0 BG1tCCD_S
tCCD_S
tCC
D_L
14 © 2014 Cadence Design Systems, Inc. All rights reserved.
DDR4 tCCD_S vs tCCD_L Comparison
tCCD_S (min): 4 CK cycles tCCD_L(min): 6 CK cycles2 dead cycles
• tCCD_S: 4 DRAM clock cycles aligns well with DDR4 BL8
• tCCD_L: 6 DRAM clock cycles is two more clock cycles than BL8 leaving 2 dead cycles
• Random traffic to DDR4 x8 devices with 4 bank groups will have some efficiency challenges
• Random traffic to DDR4 x16 devices with only 2 bank groups will have much more efficiency challenges
15 © 2014 Cadence Design Systems, Inc. All rights reserved.
LPDDR4 DRAM Timing ComparisonNumber of Clock Cycles
Symbol LPDDR4-
1600 - 3200
tRRD 4
tCCD 8
• tRRD: ACTIVATE bank A to ACTIVATE bank B command delay
• tCCD: CAS to CAS command delay
• Optimal LPDDR4 tCCD is less than or equal to 8 clock cycle to align with BL 16
No dead cycles
Example LDDR4 timing diagram
16 © 2014 Cadence Design Systems, Inc. All rights reserved.
• Random addressing with BG disabled
• DDR4 X16 has worse timings than X8
• DDR4 timing worse at higher data rates
Estimated Data Throughput EfficiencyExample DRAM System Scenarios
• Random addressing with DDR4 BG enabled
• No change in LPDDR4 throughput
0
25
50
75
100
DDR4 X8 DDR4 x16 LPDDR4
1600 Mb/s
2667 Mb/s
0
25
50
75
100
DDR4 X8 DDR4 x16 LPDDR4
1600 Mb/s
2667 Mb/s
17 © 2014 Cadence Design Systems, Inc. All rights reserved.
LPDDR4/DDR4 Device Comparison Summary
Symbol LPDDR4 x32 DDR4 x8 DDR4 x16
tRRD 4 4 - 6 5 - 8
tCCD 8 4 - 6 4 - 6
BL 16 or 32 8 8
density 6Gb – 8Gb 4Gb – 8Gb 4Gb – 8Gb
Data rate Up to 3200Mb/s
Roadmap to 4267
Up to 3200Mb/s Up to 3200Mb/s
# devices - 32 bit 1 4 2
Package type Discrete & POP Discrete Discrete
Command/Address
Pin count
12 22 22
LPDDR4 Devices May Be Ideal for Low Density High
Performance Consumer Applications
18 © 2014 Cadence Design Systems, Inc. All rights reserved.
• Consumer products must be competitive on cost and performance
• Consumer products use lower cost PC DRAM today
• Trends in the DRAM device market are driving the demand to consider LPDDR4 DRAMs in consumer products
• LPDDR4 DRAM devices have potential to replace DDR4 devices in consumer products– LPDDR4 is higher performance than DDR4
– Potential for lower cost BOM with LPDDR4
• DRAM performance trend is driving consumer product developers to investigate LPDDR4/DDR4 combination IP
Summary