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PPT PRESENTATION ON LOW POWER UART
Citation preview
LOW POWER UART DEVICE FOR
SERIAL DATA COMMUNICATION
PARNAB CHAKRABORTY
COMPUTER SCIENCE amp ENGG
A G E N D A
What is an UART
Block Diagram
Receiver
Transmitter
Register set overview
Applications
HISTORY OF UART
1048708 Need A mean to connect peripherals
RS-232 1048708 Serial Port 1048708 UART
1048708 First Applications Teletypes or Visual Display Units (VDU) Printers and Modems1048708 8250 The first ldquoPCrdquo UART made by National1048708 UART Evolution1048708 8250 16450 16550 16C650A 16C8501048708 Driven by Modem speeds later by other
applications 1048708 Currently sophisticated devices with numerous
features
What is an UART
Universal Asynchronous Receiver amp Transmitter
UART is an important device for serial data communication which helps to communicate CPU with low speed peripherals like keyboards mouse etc
without synchronizing
TYPES OF U A R T
UART 1 Channel UART Dual UARTDUART 2 Channel UART Quad UARTQUART 4 Channel UART Octal UART 8 Channel UART
SERIAL TO CPU INTERFACE
Parallel to Serial conversion Serial to Parallel conversion
BLOCK DIAGRAM
SERIAL PORT INTERFACE
IO PORTS
3 OUTPUTS 5 INPUTS
SERIAL INTERFACE
TXD amp RXD for data transfer RTS amp CTS for flow control or general purpose output and
input respectively DTR or general purpose output DSRDCD amp RI or general purpose input
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
A G E N D A
What is an UART
Block Diagram
Receiver
Transmitter
Register set overview
Applications
HISTORY OF UART
1048708 Need A mean to connect peripherals
RS-232 1048708 Serial Port 1048708 UART
1048708 First Applications Teletypes or Visual Display Units (VDU) Printers and Modems1048708 8250 The first ldquoPCrdquo UART made by National1048708 UART Evolution1048708 8250 16450 16550 16C650A 16C8501048708 Driven by Modem speeds later by other
applications 1048708 Currently sophisticated devices with numerous
features
What is an UART
Universal Asynchronous Receiver amp Transmitter
UART is an important device for serial data communication which helps to communicate CPU with low speed peripherals like keyboards mouse etc
without synchronizing
TYPES OF U A R T
UART 1 Channel UART Dual UARTDUART 2 Channel UART Quad UARTQUART 4 Channel UART Octal UART 8 Channel UART
SERIAL TO CPU INTERFACE
Parallel to Serial conversion Serial to Parallel conversion
BLOCK DIAGRAM
SERIAL PORT INTERFACE
IO PORTS
3 OUTPUTS 5 INPUTS
SERIAL INTERFACE
TXD amp RXD for data transfer RTS amp CTS for flow control or general purpose output and
input respectively DTR or general purpose output DSRDCD amp RI or general purpose input
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
HISTORY OF UART
1048708 Need A mean to connect peripherals
RS-232 1048708 Serial Port 1048708 UART
1048708 First Applications Teletypes or Visual Display Units (VDU) Printers and Modems1048708 8250 The first ldquoPCrdquo UART made by National1048708 UART Evolution1048708 8250 16450 16550 16C650A 16C8501048708 Driven by Modem speeds later by other
applications 1048708 Currently sophisticated devices with numerous
features
What is an UART
Universal Asynchronous Receiver amp Transmitter
UART is an important device for serial data communication which helps to communicate CPU with low speed peripherals like keyboards mouse etc
without synchronizing
TYPES OF U A R T
UART 1 Channel UART Dual UARTDUART 2 Channel UART Quad UARTQUART 4 Channel UART Octal UART 8 Channel UART
SERIAL TO CPU INTERFACE
Parallel to Serial conversion Serial to Parallel conversion
BLOCK DIAGRAM
SERIAL PORT INTERFACE
IO PORTS
3 OUTPUTS 5 INPUTS
SERIAL INTERFACE
TXD amp RXD for data transfer RTS amp CTS for flow control or general purpose output and
input respectively DTR or general purpose output DSRDCD amp RI or general purpose input
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
What is an UART
Universal Asynchronous Receiver amp Transmitter
UART is an important device for serial data communication which helps to communicate CPU with low speed peripherals like keyboards mouse etc
without synchronizing
TYPES OF U A R T
UART 1 Channel UART Dual UARTDUART 2 Channel UART Quad UARTQUART 4 Channel UART Octal UART 8 Channel UART
SERIAL TO CPU INTERFACE
Parallel to Serial conversion Serial to Parallel conversion
BLOCK DIAGRAM
SERIAL PORT INTERFACE
IO PORTS
3 OUTPUTS 5 INPUTS
SERIAL INTERFACE
TXD amp RXD for data transfer RTS amp CTS for flow control or general purpose output and
input respectively DTR or general purpose output DSRDCD amp RI or general purpose input
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
TYPES OF U A R T
UART 1 Channel UART Dual UARTDUART 2 Channel UART Quad UARTQUART 4 Channel UART Octal UART 8 Channel UART
SERIAL TO CPU INTERFACE
Parallel to Serial conversion Serial to Parallel conversion
BLOCK DIAGRAM
SERIAL PORT INTERFACE
IO PORTS
3 OUTPUTS 5 INPUTS
SERIAL INTERFACE
TXD amp RXD for data transfer RTS amp CTS for flow control or general purpose output and
input respectively DTR or general purpose output DSRDCD amp RI or general purpose input
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
BLOCK DIAGRAM
SERIAL PORT INTERFACE
IO PORTS
3 OUTPUTS 5 INPUTS
SERIAL INTERFACE
TXD amp RXD for data transfer RTS amp CTS for flow control or general purpose output and
input respectively DTR or general purpose output DSRDCD amp RI or general purpose input
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
SERIAL PORT INTERFACE
IO PORTS
3 OUTPUTS 5 INPUTS
SERIAL INTERFACE
TXD amp RXD for data transfer RTS amp CTS for flow control or general purpose output and
input respectively DTR or general purpose output DSRDCD amp RI or general purpose input
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
8 BIT CPU INTERFACE
INTEL BUS MODE CS IR IOW Address Data INT
MOTOROLLA BUS MODE CS ReadWrite Address Data IRQ
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
TIMING amp BUAD RATE GENERATOR
Crystal or External Clock
Standard Clock Frequencies 18432 MHz 36864 MHz 73728 MHz 147456 MHz 18432 MHz 221114MHz
16 X Timing for internal operation
Standard Data Rates 110 to 9216 Kbps
Baud Rate Calculation Baud Rate = (Clock Frequency16)(Divisor)
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
RECEIVER
bull Serial to Parallel Conversionbull Receive (RX) FIFO amp Receive Shift
Register (RSR) with error tagsbull 16X timing clock for mid bit sampling
amp verificationbull Start bit detection amp verificationbull Data-Bit samplingbull Parity sampling amp verification (parity error)bull Stop-Bit sampling amp verificationbull Framing check amp error reportsbull FIFO status report (RXRDYINT)
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
TRANSMITTER
bull Parallel to Serial Conversion
bull Transmitter (TX) FIFO Transmitter
Shift Register (TSR)
bull 16X timing for bit shifting
bull Character Framing
bull Parity Insertion
bull FIFO empty report (TXRDYINT)
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
USING THE UART
Above is the UART data format which has a block of 11 bits
1 leading low start bit Indicating the start of data transmission 1 trailing high stop bit Indicating the end of data transmission 1 parity bit Checks for error if any by the receiver 8 data bits
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
REGISTER SET OVERVIEW
THR-Transmit Holding Register (write only) Loads data to be transmitted into TX FIFO RHR-Receive Holding Register (read only) Reads out received data from RX FIFO IER-Interrupt Enable Register (readwrite)
Enable or Disable Interrupt ISR- Interrupt Status Register (read only)
Highest priority pending interrupt FCR-FIFO Control Register (write only) FIFO enable FIFO reset FIFO trigger level selection LCR-Line Control Register (readwrite) word length stop bit length parity selection break divisor latch
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
Contrsquodhelliphelliphelliphellip
MSR-Modem Status Register (read only)
State of modem inputs and itrsquos changes since last read
SPR-Scratch Pad Register (readwrite)
General purpose ReadWrite Register
DLL amp DLM (readwrite)
DLL(LSB) DLM(MSB) is 16 bit divisor for internal baud rate generator
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
LOW POWER OPERATION
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
MARKET APPLICATION INDUSTRIAL APPLICATION THIN CLIENT TERMINAL SERVER
Cost effective Low maintenance More flexible amp Reliable
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
TELECOMUNICATION APPLICATIONRemote Access Server
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
Point Of Sale System
POS SYSTEM WITH8 TO 32 RS 232485 PORTS
VENDING
SYSTEMS
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME
THANK YOU VERY MUCH FOR YOUR PRECIOUS
TIME