Low Power Design Essentials

Series on Integrated Circuits and Systems

Series Editor: Anantha Chandrakasan

Massachusetts Institute of Technology

Cambridge, Massachusetts

Low Power Design Essentials

Jan Rabaey

ISBN 978-0-387-71712-8

Carbon Nanotube Electronics

Ali Javey and Jing Kong (Eds.)

ISBN 978-0-387-36833-7

Wafer Level 3-D ICs Process Technology

Chuan Seng Tan, Ronald J. Gutmann, and L. Rafael Reif (Eds.)

ISBN 978-0-387-76532-7

Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice

Alice Wang and Samuel Naffziger (Eds.)

ISBN 978-0-387-76471-9

mm-Wave Silicon Technology: 60 GHz and Beyond

Ali M. Niknejad and Hossein Hashemi (Eds.)

ISBN 978-0-387-76558-7

Ultra Wideband: Circuits, Transceivers, and Systems

Ranjit Gharpurey and Peter Kinget (Eds.)

ISBN 978-0-387-37238-9

Creating Assertion-Based IP

Harry D. Foster and Adam C. Krolnik

ISBN 978-0-387-36641-8

Design for Manufacturability and Statistical Design: A Constructive Approach

Michael Orshansky, Sani R. Nassif, and Duane Boning

ISBN 978-0-387-30928-6

Low Power Methodology Manual: For System-on-Chip Design

Michael Keating, David Flynn, Rob Aitken, Alan Gibbons, and Kaijian Shi

ISBN 978-0-387-71818-7

Modern Circuit Placement: Best Practices and Results

Gi-Joon Nam and Jason Cong

ISBN 978-0-387-36837-5

CMOS Biotechnology

Hakho Lee, Donhee Ham and Robert M. Westervelt

ISBN 978-0-387-36836-8

SAT-Based Scalable Formal Verification Solutions

Malay Ganai and Aarti Gupta

ISBN 978-0-387-69166-4, 2007

Ultra-Low Voltage Nano-Scale Memories

Kiyoo Itoh, Masashi Horiguchi and Hitoshi Tanaka

ISBN 978-0-387-33398-4, 2007

Continued after index

Jan Rabaey

Low Power Design Essentials

1 3

Jan RabaeyDepartment of Electrical Engineering &Computer Science (EECS)

University of CaliforniaBerkeley, CA 94720USAjan@eecs.berkeley.edu

ISSN 1558-9412ISBN 978-0-387-71712-8 e-ISBN 978-0-387-71713-5DOI 10.1007/978-0-387-71713-5

Library of Congress Control Number: 2008932280

# Springer ScienceþBusiness Media, LLC 2009All rights reserved. This work may not be translated or copied in whole or in part without the written permission of thepublisher (Springer ScienceþBusiness Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for briefexcerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage andretrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafterdeveloped is forbidden.The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified assuch, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.

Printed on acid-free paper

springer.com

To KathelijinFor so many years, my true source of support and motivation.

To My ParentsWhile I lost you both in the past two years, you still inspire me to reach ever further.

Preface

Slide 0.1

Welcome to this book titled‘‘Low Power Design Essen-tials’’. (A somewhat moreaccurate title for the bookwould be ‘‘Low PowerDigital Design Essentials’’,as virtually all of the mate-rial is focused on the digitalintegrated-circuit designdomain.)

In recent years, powerand energy have becomeone of the most compellingissues in the design of digi-tal circuits. On one end,power has put a severe lim-itation on how fast we can

run our circuits; at the other end, energy reduction techniques have enabled us to build ubiquitousmobile devices that can run on a single battery charge for an exceedingly long time.

Slide 0.2

Youmay wonder why there is a need for yet another book on low-power design, as there are quite anumber of those already on the market (some of them co-authored by myself). The answer is quitesimple: all these books are edited volumes, and target the professional who is already somewhatversed in themain topics of design for power or energy.With these topics becoming one of themostcompelling issues in design today, it is my opinion that it is time for a book with an educationalapproach. This means building up from the basics, and exposing the different subjects in a rigorousand methodological way with consistent use of notations and definitions. Concepts are illustratedwith examples using state-of-the-art technologies (90 nm and below). The book is primarilyintended for use in short-to-medium length courses on low-power design. However, the formatalso should work well for the working professional, whowants to update her/himself on low-powerdesign in a self-learning manner.

Preface

Jan M. Rabaey

vii

This preface also pre-

sents an opportunity for

me to address an issue that

has been daunting low-

power design for a while.

Many people in the field

seem to think that it is just

a ‘‘bag of tricks’’ applied in

a somewhat ad hoc fash-

ion, that it needs a guru to

get to the bottom, and that

the concept of a low-power

methodology is somewhat

an oxymoron. In fact, in

recent years researchers

and developers have demonstrated that this need not be the case at all. One of the most important

realizations over the past years is that minimum-energy design, though interesting, is not what we

truly are pursuing. In general, we design in an energy–delay trade-off space, where we try to find

design with the lowest energy for a given performance, or vice versa. A number of optimization and

design exploration tools can be constructed that help us to traverse this trade-off space in an

informed fashion, and this at all levels of the design hierarchy.In addition to adhering to such amethodology throughout the text, we are also investigating the

main roadblocks that we have to overcome in the coming decades if we want to keep reducing the

energy per operation. This naturally leads to the question of what the physical limits of energy

scaling might be. Wherever possible, we also venture some perspectives on the future.

Slide 0.3

Already in this preface,you observe the somewhat

unorthodox approach the

book is taking. Rather

than choosing the tradi-

tional approach of a

lengthy continuous text,

occasionally interspersed

with some figures, we use

the reverse approach: gra-

phics first, text as a side

note. In my experience, a

single figure does a lot

more to convey a message

than a page of text (‘‘A picture is worth a 1000 words’’). This approach was pioneered by Willy

Sansen in his book Analog Design Essentials (also published by Springer). The first time I saw the

book, I was immediately captivated by the idea. The more I looked at it, the more I liked it. Hence

this book . . . . When browsing through it, you will notice that the slides and the notes play entirely

Goals of This Book

Provide an educational perspective onlow-power desgn for digital integratedcircuitsPromote a structured design methodologyfor low power/energy designTraverse the levels of the design hierarchy Explore bounds and roadblocks Provide future perspectives

An Innovative Format

Pioneered in W. Sansen’s book Analog DesignEssentials (Springer) PowerPoint slides present a quick outlineof essential points and issues, and providea graphical perspective

Side notes provide depth, explainreasonings, link topics

Supplemented with web-site:http://bwrc.eecs.berkeley.edu/LowPowerEssentials

An ideal tool for focused-topic courses

viii Preface

different roles. Another advantage of the format is that the educator has basically all the lecturing

material in her/his hands rightaway. Besides distributing the slideware freely, we also offer addi-

tional material and tools on the web-site of the book.

Slide 0.4

The outline of the bookproceeds as follows: After

first establishing the basics,

we proceed to address

power optimization in

three different operational

modes: design time,

standby time, and run

time. The techniques used

in each of these modes dif-

fer considerably. Observe

that we treat dynamic and

static power simulta-

neously throughout the

text – in today’s semicon-

ductor technology, leakage

power is virtually on par-

with switching power.

Hence separating them does not make much sense. In fact, a better design is often obtained if

the two are carefully balanced. Finally, the text concludes with a number of general topics such as

design tools, limits on power, and some future projections.

Slide 0.5

Putting a book like thistogether without help is vir-

tually impossible, and a

couple of words of thanks

and appreciation are in

order. First and foremost,

I am deeply indebted to

Ben Calhoun, Jerry Fren-

kil, Dejan Markovic, and

Bora Nikolic for their help

and co-authorship of some

of the chapters. In addition,

a long list of people have

helped in providing the

basic slideware used in the

text, and in reviewing the

Outline

Background1. Introduction2. Advanced MOS Transistors and Their Models3. Power Basics

Optimizing Power @ Design Time4. Circuits

5. Architectures, Algorithms, and Systems6. Interconnect and Clocks7. Memories

Optimizing Power @ Standby8. Circuits and Systems9. Memory

Optimizing Power @ Runtime10. Circuits, Memory, and Systems

Perspectives11. Ultra Low Power/ VoltageDesign12. Low Power Design Methodologies and Flows13. Summary and Perspectives

Acknowledgements

The contributions of many of my colleagues to this book are greatlyappreciated. Without them, building this collection of slides would have beeni ibl E i ll I ld lik t i l t th i t f th f ll iimpossible. Especially, I would like to single out the inputs of the followingindividuals who have contributed in a major way to the book: Ben Calhoun,Jerry Frenkil, and Dejan Marković. As always, it has been an absolute pleasureworking with them.

In addition, a large number of people have helped to shape the book bycontrib ting material or b re ie ing as the emerged I amcontributing material, or by reviewing the chapters as they emerged. I amdeeply indebted to all of them: E. Alon, T. Austin, D. Blaauw, S. Borkar, R.Brodersen, T. Burd, K. Cao, A. Chandrakasan, H. De Man, K. Flautner, M.Horowitz K Itoh T Kuroda B Nikolić C Rowen T Sakurai A SangiovanniHorowitz, K. Itoh, T. Kuroda, B. Nikolić, C. Rowen, T. Sakurai, A. Sangiovanni-Vincentelli, N. Shanbhag, V. Stojanović, T. Sakurai, J. Tschanz, E. Vittoz, A.Wang, and D. Wingard, as well as all my graduate students at BWRC.

I also would like to express my appreciation for the funding agencies that haveprovided strong support to the development of low-power design technologiesand methodologies Especially the FCRP program (and its member companies)and methodologies. Especially the FCRP program (and its member companies)and DARPA deserve special credit.

Preface ix

earlier drafts of the book. Special gratitude goes to a number of folks who have shaped the low-

power design technology world in a tremendous way – and as a result have contributed enormously

to this book: Bob Brodersen, Anantha Chandrakasan, Tadahiro Kuroda, Takayasu Sakurai,

Shekhar Borkar, and Vivek De. Working with them over the past decade(s) has been a great

pleasure and a truly exciting experience!

Slide 0.6–0.7

Every chapter in the bookis concluded with a set of

references supporting the

material presented in the

chapter. For those of you

who are truly enamored

with the subject of low-

power design, these slides

enumerate a number of

general reference works,

overview papers, and

visionary presentations on

the topic.

I personally had a wonderful and truly enlightening time putting this material together whiletraversing Europe during my sabbatical in the spring of 2007. I hope you will enjoy it as well.

Jan M. Rabaey, Berkeley, CA

Low-Power Design – Special References

S. Borkar, “Design challenges of technology scaling,” IEEE Micro, 19 (4), p. 23–29, July–Aug. 1999.T.Kuroda, T. Sakurai, “Overview of low-power ULSI circuit techniques,” IEICE Trans. on Electronics, E78-C(4), pp. 334–344, Apr. 1995.

Journal-o fLow Power Electronics (JOLPE), http://www.aspbs.com/jolpe/

Proceedings of the IEEE, Special Issue on Low Power Design, Apr. 1995.Proceedings of the ISLPED Conference (starting 1994)Proceedings of ISSCC, VLSI Symposium, ESSCIRC, A-SSCC, DAC, ASPDAC, DATE, ICCAD conferences

Low Power Design – Reference Books

A. Chandrakasan and R. Brodersen, Low Power CMOS Design, Kluwer Academic Publishers, 1995.

A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, IEEE Press, 1998 (Reprint Volume)Volume).

A. Chandrakasan, Bowhill, and Fox, Design of High-Performance Microprocessors, IEEE Press, 2001.

• Chapter 4, “Low-Voltage Technologies,” by Kuroda and Sakuraipggy

• Chapter 3, “Techniques for Leakage Power Reduction,” by De, et al.

• M. Keating et al., Low Power Methodology Manual, Springer, 2007.

S. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Springer,2006.

M. Pedram and J. Rabaey, Ed., Power Aware Design Methodologies, Kluwer Academic Publishers, 2002.

CC. Piguet, Ed., Low-Power Circuit Design, CRC Press, 2005.

J. Rabaey and M. Pedram, Ed., Low Power Design Methodologies, Kluwer Academic Publishers, 1995.

JJ. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits - A Design Perspective,Prentice Hall, 2003.

S. Roundy, P. Wright and J.M. Rabaey, Energy Scavenging for Wireless Sensor Networks,Kluwer Academic Publishers, 2003.

A. Wang, Adaptive Techniques for Dynamic Power Optimization, Springer, 2008.

x Preface

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Nanometer Transistors and Their Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 Power and Energy Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4 Optimizing Power @ Design Time: Circuit-Level Techniques . . . . . . . . . . . . . . . . . . . . . 77

5 Optimizing Power @ Design Time – Architecture, Algorithms, and Systems. . . . . . . . . . 113

6 Optimizing Power @ Design Time – Interconnect and Clocks . . . . . . . . . . . . . . . . . . . . . 151

7 Optimizing Power @ Design Time – Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

8 Optimizing Power @ Standby – Circuits and Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

9 Optimizing Power @ Standby – Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

10 Optimizing Power @ Runtime: Circuits and Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

11 Ultra Low Power/Voltage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

12 Low Power Design Methodologies and Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

13 Summary and Perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

xi

Chapter 1

Introduction

Jan M. Rabaey

Introduction

Slide 1.1

In this chapter we discusswhy power and energy con-sumption has become oneof the main (if not themain) design concerns intoday’s complex digitalintegrated circuits. Wefirst aalyze the differentapplication domains andevaluate how each has itsown specific concerns andrequirements, from a

power perspective soon. Most projections into the future show that these concerns most likelywill not go away. In fact, everything seems to indicate that they will even aggravate. Next, weevaluate technology trends – in the idle hope that technology scaling may help to address some ofthese problems. Unfortunately, CMOS scaling only seems to make the problem worse. Hence,design solutions will be the primary mechanism in keeping energy/power consumption in controlor within bounds. Identifying the central design themes and technologies, and finding ways toapply them in a structured andmethodological fashion, is the main purpose of this book. For quitesome time, low-power design consisted of a collection of ad hoc techniques. Applying thosetechniques successfully on a broad range of applications and without too much ‘‘manual’’ inter-vention requires close integration in the traditional design flows. Over the past decade, muchprogress in this direction was made. Yet, the gap between low-power design technology andmethodology remains.

Slide 1.2

There are many reasons why designers and application developers worry about power dissipation.One concern that has come consistently to the foreground in recent years is the need for ‘‘green’’electronics. While the power dissipation of electronic components until recently was only a smallfraction of the overall electrical power budget, this picture has changed substantially in the last fewdecades. The pervasive use of desktops and laptops has made its mark in both the office and homeenvironments. Standby power of electronic consumer components and set-up boxes is risingrapidly such that at the time of writing this book their power drain is becoming equivalent to

J. Rabaey, Low Power Design Essentials, Series on Integrated Circuits and Systems,DOI 10.1007/978-0-387-71713-5_1, � Springer ScienceþBusiness Media, LLC 2009

1

that of a decent-size fridge.Electronics are becoming asizable fraction of thepower budget of a modernautomobile. These trendswill only becomemore pro-nounced in the comingdecade(s).

In this slide, the growingimportance of electronicsas part of the power budgetis brought home with a‘‘tongue-in-cheek’’ extra-polation. If Moore’s lawwould continue unabatedin the future and the com-putational needs wouldkeep on doubling every

year, the total energy of our galaxy would be exhausted in the relatively low time span of 180years (even if we assume that every digital operation is performed at its lowest possible level).However, as Gordon Moore himself stated in his keynote address at the 2001 ISSCC conference,‘‘No exponential is forever’’, adding quickly thereafter, ‘‘. . . but forever can be delayed’’.

Power: The Dominant Design Constraint (1)

Cost of large data centers solely determined by power bill …

Google Data Center, The Dalles, OregonGoogle Data Center, The Dalles, Oregon

Columbia River

8,000100,000

450,000

NY Times, June 06

400 Millions of Personal Computers worldwide (Year 2000)

-Assumed to consume 0.16 Tera (1012) kWh per year-Equivalent to 26 nuclear power plants

Over 1 Giga kWh per year just for cooling-Including manufacturing electricity

[Ref: Bar-Cohen et al., 2000]

Slide 1.3

The subsequent slide setsevaluate the power needand trends for a number ofdominant application areasof digital integrated cir-cuits. First, the domains ofcomputation and commu-nication infrastructure arediscussed. The advent ofthe Internet, combinedwith ubiquitous access tothe network using bothwired and wireless inter-faces, has dramaticallychanged the nature of com-puting. Todaymassive datastorage and computingcenters operated by large

companies at a number of centralized locations have absorbed a huge amount of the worldwidecomputational loads of both corporations and individuals. And this trend is not showing any signsof slowing down, as new server farms are being brought online at a staggering rate. Yet, thiscentralization comes at a price. The ‘‘computational density’’ of such a center, and hence the powerusage, is substantial. To quote Luis Barosso from Google (a company which is one of the mostprolific promoters of the remote-computation concept), the cost of a data center is determined

Why Worry About Power?

Total energy of Milky Way galaxy: 1059 J

Minimum switching energy for digital gate (1 electron@100mV): 1.6 × 10–20J (limited by thermal noise)

Upper bound on number of digital operations: 6 × 1078

Operations/year performed by 1 billion 100 MOPS computers: 3 × 1024

Entire energy might be consumed in 180 years, assuming a doublingof computational requirements every year (Moore’s Law).

The Tongue-in-Cheek Answer

2 Chapter #1

solely by the monthly power bill, not by the cost of hardware or maintenance. This bill results fromboth the power dissipation in the electronic systems and the cost of removing the dissipated heat –that is, air conditioning. This explains whymost data centers are now implanted at carefully chosenlocations where power is easily available and effective cooling techniques are present (such as in theproximity of major rivers – in an eerie similarity to nuclear plants).

While data centers represent a major fraction of the power consumed in the computation andcommunication infrastructure, other components should not be ignored. The fast routers that zipthe data around the world, as well as the wireless base stations (access points) which allow us toconnect wirelessly to the network, offer major power challenges as well. Owing to their location,the availability of power and the effectiveness of cooling techniques are often limited. Finally, thedistributed computing and communication infrastructure cannot be ignored either; the wired andwireless data routers in the office, plant, or home, the back-office computing servers and thedesktop computers add up to a sizable power budget as well. A large fraction of the air condition-ing bill in offices is due to the ever-growing computational infrastructure.

Power: The Dominant Design Constraint

[Ref: R. Schmidt, ACEED’03]

Slide 1.4

It is worth spending sometime on the cooling issue.A typical computing serverrack in a server farm canconsume up to 20 kW.With the racks in a farmeasily numbering over onehundred, power dissipationcan top the 2MW (all ofwhich is transformed intoheat). The design of the airconditioning system andthe flow of air through theroom and the racks is quitecomplicated and requiresextensive modeling andanalysis. The impact of an

ill-designed system can be major (i.e., dramatic failure), or more subtle. In one such data centerdesign, cool air is brought in from the floor and is gradually heated while it rises through the blades(boards) in the rack. This leads to a temperature gradient, which may mean that processors closerto the floor operate faster than the ones on the top! Even with the best air-cooling design practices,predicting the overall dynamics of the center can be hard and can lead to under-cooling. Sometimessome quick improvised fixes are the only rescue, as witnessed in these ironic pictures, provided byRoger Schmidt, a distinguished engineer at IBM and a leading expert in the engineering andengineering management of the thermal design of large-scale IBM computers.

Slide 1.5

While temperature gradients over racks can lead to performance variations, the same is true forthe advanced high-performance processors of today. In the past die sizes were small enough,and activity over the die was quite uniform. This translated into a flat temperature profile atthe surface of the die. With the advent of Systems-on-a-Chip (SoC), more and more diverse

Introduction 3

functionality is integratedin close proximity, veryoften with very differentworkloads and activityprofiles. For instance, mosthigh-performance micro-processors (or multi-coreprocessors) integrate mul-tiple levels of cache mem-ories on the die, just nextto the high-performancecomputing engine(s). Asthe data path of the proces-sor is clocked at the highestspeed and is kept busyalmost 100% of the time,its power dissipation issubstantially higher thanthat of the cache memories.

This results in the creation of hot spots and temperature gradients over the die. This may impactthe long-term reliability of the part and complicate the verification of the processor. Executionspeed and propagation delay are indeed strongly dependent on temperature. With temperaturegradients over the die (which may change dynamically depending upon the operation modes ofthe processors), simulation can now not be performed for a single temperature, as was the commonpractice.

Temperature Gradients (and Performance)

IBM PowerPC 4 temperature map

Hot spot:138 W/cm2

(3.6 x chip avg flux)

Glass ceramic substrate

SiC spreader (chip underneath spreader)

Copper hat (heat sink on top not shown)

[Ref: R. Schmidt, ACEED’03]

Slide 1.6

The existence of these ther-mal gradients is perfectlyillustrated in this slide,which plots the tempera-ture map of the IBMPowerPC 4 (a late 1990smicroprocessor). A tem-perature difference of over208C can be observedbetween the processor coreand the cache memory.Even more staggering, theheat generation at the hotspot (the data pipeline)equals almost 140W/cm2.This is 3.6 times the heatremoval capacity of thechip cooling system. To

correct for this imbalance, a complex package has to be constructed, which allows for the heatto spread over a wider area, thus improving the heat removal process. In high-performance

[Ref: R. Yung, ESSCIRC’02]

Chip Architecture and Power Density

Integration of diverse functionality on SoC causes major variations in activity(and hence power density)

The past: temperature uniformity

Today: steep gradients

Temperature variations cause performance degradation –higher temperature means slower clock speed

4 Chapter #1

components, packaging cost has become an important (if not dominating) fraction of the totalcost. Techniques that help to mitigate the packaging problems either by reducing the gradients orby reducing the power density of selected sub-systems are hence essential. Structured low-powerdesign methodologies, as advocated in this book, do just that.

Power consumption and battery capacity trends[Ref: Y. Nuevo, ISSCC’04]

Power : The Dominant Design Constraint (2)

© IEEE 2004

Slide 1.7

The second reason whydesign for low power/energy has become soimportant is the emergenceof mobile electronics.While mobile consumerelectronics has beenaround for a while (FMradios, portable CDplayers), it is the simulta-neous success of portablelaptops and digital cellularphones that has driven thequest for low-energy com-puting and communica-tion. In a battery-operated

device, the available energy is fixed, and the rate of power consumption determines the lifetime ofthe battery (for non-rechargeables) or the time between recharges. Size, aspect ratio, and weight aretypically set by the application or the intended device. The allowable battery size of a cellular phonetypically is set to at most 4–5 cm3, as dictated by user acceptance. Given a particular batterytechnology, the expected operational time of the device – cell phone users today expect multipledays of standby time and 4–5 h of talk time – in between recharges sets an upper bound on thepower dissipation for the different operational modes. This is turn determines what functionalitycan be supported by the device, unless breakthroughs in low-power design can be accomplished.For instance, the average power dissipation limit of a cell phone is approximately 3W, dictated bytoday’s battery technologies. This in turn dictates whether your phone will be able to supportdigital video broadcasting, MP3 functionality, and 3G cellular and WIFI interconnectivity.

Slide 1.8

From this perspective, it is worthwhile to classify consumer and computing devices into a numberof categories, based on their energy needs and hence functionality. In the ‘‘ambient intelligent’’home of the future (a term coined by Fred Boekhorst from Philips in his ISSCC keynote in 2002),we may identify three styles of components. First, we have the ‘‘Watt nodes’’ (P > 1W). These arenodes connected to the power grid, offering computational capacity of around 1GOPS andperforming functions such as computing and data serving, as well as routing and wireless access.The availability of energy, and hence computational prowess, makes them the ideal home foradvanced media processing, data manipulation, and user interfaces.

The second tier of devices is called the ‘‘Milliwatt nodes’’ (1 mW<P< 1 W). Operating at acouple of MOPS, these represent mobile, untethered devices such as PDAs, communicationdevices (connecting to WANs and LANs), and wireless displays. These components are battery-powered and fall into the scope of devices discussed in the previous slide.

Introduction 5

The ‘‘Microwatt nodes’’represent the final category(P< 1mW). Their functionis to add awareness to thenetwork, providing sensingfunctionality (temperature,presence, motion, etc.), andto transmit that data to themore capable nodes. The 1KOPS computational cap-ability severely limits theirfunctionality. Given that atypical homemay contain ahuge number of thesenodes, they have to beenergy self-contained orpowered using energyscavenging. Their very lowpower levels enable theatter. More information

about this class of nodes follows in later slides.

Battery Storage a Limiting Factor

Basic technology has evolved little– store energy using a chemical reaction

Battery capacity increases between 3% and 7% per year (doubled during the 1990s, relatively flat before that)

Energy density/size and safe handling are limiting factors

Energy density of material

kWh/kg

Gasoline 14

Lead-acid 0.04

Li polymer 0.15

For extensive information on energy density of various materials, check http://en.wikipedia.org/wiki/Energy_density

Slide 1.9

From the above discussion,obviously the questionarises: ‘‘Where is battery tech-nology heading?’’ As alreadyobserved in Slide 1.7,battery capacity (i.e., theamount of energy that canbe stored and deliveredfor a given battery volume)doubles approximatelyevery 10 years. This repre-sents an improvement of3–7% every year (the slopetends to vary based on theintroduction of new tech-nologies). This growthcurve lags substantially

behinds Moore’s law, which indicates a doubling in computational complexity every 18 months.The challenge with battery technology is that chemical processes are the underlying force, andimprovements in capacity are often related to new chemicals or electrode materials. These are hardto come by. Also, the manufacturing processes for every new material take a long time to develop.Yet, an analysis of the available chemicals seems to show some huge potential. The energy density

[Ref: F. Snijders, Ambient Intelligence’05]

6 Chapter #1

of alcohol or gasoline is approximately two orders of magnitude higher than that of lithium-polymer. Unfortunately, concerns about the effective and safe handling of these substances make ithard to exploit them in small form factors.

Battery Evolution

020406080

100120140160

1940 1950 1960 1970 1980 1990 2000 2010

First Commercial Use

Energy Density(Wh/kg)

Trend Line

Accelerated since the 1990s, but slower than IC power growth.

Li-ion

Slide 1.10

The historical trends in bat-tery capacity actually varyquite a bit. Up to the 1980s,very little or even no pro-gress was made – there wasactually little incentive todo so, as the scope of appli-cation was quite limited.Flash lights were probablythe driving application. Inthe 1990s, mobile applica-tions took off. Intensiveresearch combined withadvanced manufacturingstrategies changed the slopesubstantially, improving the

capacity by a factor of four in almost a decade. Unfortunately, the process has stalled somewhatsince the beginning of the 21st century. A major improvement in battery capacity can only be achievedby the introduction of new battery chemicals. It should also be observed that the capacity of a battery(that is the energy that can be extracted from it) also depends upon its discharge profile. Draining abattery slowly will deliver more energy than flash discharge. It is hence worthwhile to match the batterystructure to the application at hand.

Battery Technology Saturating

Battery capacity naturally plateaus as systems develop

[Courtesy: M. Doyle, Dupont]

Slide 1.11

The fact that the energydelivery capacity of a batteryis ultimately determinedby the basic chemical proper-ties of the materials involvedis clearly illustrated in thisslide. In the 1990s, the capa-city of Lithium-ion batteriesimproved substantially. Thiswas mostly due to betterengineering: improved elec-trode structures, bettercharging technology, andadvanced battery systemdesign. This ultimatelysaturated as the intrinsicmaximum potential of the

material is being approached. Today, progress in Lithium-ion battery technology has stalled,and little improvement is foreseen in the future.

Introduction 7

Need Higher Energy Density

Fuel cells may increase stored energy bymore than an order of magnitudeExample: Methanol = 5 kWh/kg

Ano

de

Ele

ctro

lyte

Cat

hode

+ ions

Load

e–

+–

Fue

l

2H2

4H+

+ 4

e–

Oxi

dant

O2

+ 4

H+

+ 4

e–2H

2O

H O

[Ref: R. Nowak, SECA’01]

Slide 1.12

The bottom line from thepresented trends is thatonly a dramatic change inchemicals will lead to sub-stantial increase in batterycapacity. The opportunityis clearly there. Forinstance, hydrogen has anenergy density 4–8 timesthat of Lithium-ion. It isno surprise that hydrogenfuel cells are currentlyunder serious considera-tion for the powering ofelectrical or hybrid cars.The oxidation of hydrogen

produces water and electrical current as output. Fuels such as alcohol, methanol, or gasoline areeven better. The challenge with these materials is to maintain the efficiency in small form factorswhile maintaining safety and reliability.

Fuel CellsMethanol fuel cellsfor portable PCs and MP3 players

Fuel cell for PC (12 W avg – 24% effiency)

Fuel cell for portable MP3 player(300 mW from 10 mlreservoir)

Dur

atio

n [h

]

[Ref: Toshiba, 2003-2004]

Slide 1.13

It should be of no surprisethat research in this area isintensive and that majorcompanies as well as start-ups are vying for a piece ofthe potentially huge cashpot. Success so far hasbeen few and far between.Toshiba, for instance, hasintroduced a number ofmethanol fuel cells, promis-ing to extend the opera-tional time of your cellphone to 1000 h (i.e., 40days!). Other companiesactively exploring the fuelcell option are NEC and

IBM. Yet, the technology still has to find its way into the markets. Long-term efficiency, safety,and usage models are questionable. Other candidates such as solid oxygen fuel cells (also calledceramic fuel cells) are waiting behind the curtain. If any one of these becomes successful, it couldchange the energy equation for mobiles substantially.

8 Chapter #1

Micro batteries: When Size Is an Issue

Battery printed on wireless sensor node

Using micro-electronics or thin-film manufacturing techniques to create integrated miniature (backup) batteries on chip or on board

Stencil press for printing patterns

[Courtesy: P. Wright, D. Steingart, UCB]

Slide 1.14

Another interesting newentry in the battery field isthe ‘‘micro battery’’. Usingtechnologies inherited fromthin-film and semiconduc-tor manufacturing, batteryanodes and cathodes areprinted on the substrate,and micromachined encap-sulations are used to con-tain the chemicals. In thisway, it is possible to printbatteries on printed circuitboards (PCBs), or evenembed them into integratedcircuits. While the capacityof these circuits will never

be large, micro batteries can serve perfectly well as backup batteries or as energy storage devices insensor nodes. The design of the battery involves trading off between current delivery capability(number of electrodes) and capacity (volume occupied by the chemicals). This technology is clearlystill in its infancy but could occupy some interesting niche in the years to come.

How Much Energy Storage in 1 cm3?

J/cm3 μW/cm3/year

Micro fuel cell 3500 110

Primary battery

2880 90

Secondary battery

1080 34

Ultracapacitor 100 3.2

Ultracapacitor

Micro fuel cell

Ultracapacitor

Slide 1.15

As a summary of the abovediscussions, it is worthwhileordering the various energystorage technologies formobile nodes based ontheir capacity (expressed inJ/cm3). Another usefulmetric is the average currentthat can be delivered overthe time span of a year bya 1 cm3 battery (mW/cm3/year), which provides ameasure of the longevity ofthe battery technology for aparticular application.

Miniature fuel cellsclearly provide the highestcapacity. In their currently

best incarnation, they are approximately three times more efficient than the best rechargeable(secondary) batteries. Yet, the advantage over non-rechargeables (such as alkaline) is at most 25%.

One alternative strategy for the temporary storage of energy was not discussed so far: thecapacitor. The ordinary capacitor constructed from high-quality dielectrics has the advantage ofsimplicity, reliability, and longevity. At the same time, its energy density is limited. One technology

Introduction 9

that attempts to bridge the gap between capacitor and battery is the so-called supercapacitor orultracapacitor, which is an electrochemical capacitor that has an unusually high energy densitywhen compared to common capacitors, yet substantially lower than that of rechargeable batteries.A major advantage of (ultra)capacitors is the instantaneous availability of a high dischargecurrent, which makes them very attractive for bursty applications. It is expected that newmaterialssuch as carbon nanotubes, carbon aerogels, and conductive polymers may substantially increasethe capacity of supercapacitors in the years to come.

Power: The Dominant Design Constraint (3)

Exciting emerging applications requiring “zero-power”

Example: Computation/communication nodes

[Ref: J. Rabaey, ISSCC’01]

for wireless sensor networks

Meso-scale low-cost wireless transceivers for ubiquitous wireless data acquisition that• are fully integrated

– size smaller than 1 cm3

• are dirt cheap–at or below 1$

• minimize power/energy dissipation– limiting power dissipation to 100 μW

enables energy scavenging, and

• form self-configuring, robust, ad hoc networks containing 100s to 1000s of nodes

Slide 1.16

The third and final motiva-tion behind ‘‘ultra lowpower’’ design is the emer-gence of a new class offrontier applications, called‘‘zero-power electronics’’ or‘‘disappearing electronics’’(microwatt nodes in theBoekhorst classification).The continuing miniaturi-zation of computing andcommunication compo-nents, enabled by semicon-ductor scaling, allows forthe development of tinywireless sensor nodes,often called motes. With

sizes in the range of cubic centimeters or less, these devices can be integrated into the daily-living environment, offering a wide range of sensing and monitoring capabilities. By providingspatial and temporal information about, for instance, the environmental conditions in a room,more efficient and more effective conditioning of the room is enabled. The integrated formatand the low cost make it possible to deploy large or even huge numbers of these motes. Theseemerging ‘‘wireless sensor networks (WSN)’’ have made some major inroads since theirinception in the late 1990s. Energy is one of the main hurdles to be overcome, if the WSNparadigm is to be successful. Given the large number of nodes in a network, regular batteryreplacement is economically and practically out of question. Hence, nodes should in principlebe energy self-contained for the lifetime of the application (which can be tens of years).Hence, a node should be able to operate continuously on a single battery charge, or shouldbe capable of replenishing its energy supply by energy-scavenging techniques. As both energystorage and scavenging capacities are proportional to volume and the node size is limited,ultra low-power design is absolutely essential. In the ‘‘PicoRadio’’ project, launched by theauthor in 1998, it was determined that the average power dissipation of the node could not belarger than 100 mW.

Slide 1.17

Since the inception of the WSN concept, much progress was made in reducing the size, cost, andpower dissipation of the mote. First-generation nodes were constructed from off-the-shelf compo-nents, combining generic microcontrollers, simple wireless transceivers with little power

10 Chapter #1

optimization, and standardsensors. The resulting moteswere at least one or twoorders off the stated goals inevery aspect (size, cost,power).

Since then, research inminiature low-power elec-tronics has blossomed, andhas produced spectacularresults. Advanced packagingtechnologies, introductionof novel devices (sensors,passives, and antennas),ultra low-voltage design,and intelligent power man-agement have producedmotes that are close to meet-

ing all the stated goals. The impact of these innovations goes beyond the world of wireless sensornetworks and can equally be felt in areas such as implantable devices for health monitoring orsmart cards.

Power: The Dominant Design Constraint

Exciting emerging applications requiring “zero-power”

Real-time Health Monitoring

Smart Surfaces

Artificial Skin

Philips Sand module

UCB mm3 radio

UCB PicoCube

Still at least one order of magnitude away

Slide 1.18

Even more, progress inultra low-power design andextreme miniaturization mayenable the emergence of anumber of applications thatotherwise would be comple-tely impossible. A couple ofexamples may help to illus-trate this. Dense networksof sensor nodes deployed ona broad surface may leadto ‘‘artificial skin’’, sensitiveto touch, stress, pressure, orfatigue. Obvious applicationsof such networks would beintelligent plane wings, noveluser interfaces, and improvedrobots. Embedding multiple

sensors into objects may lead to smart objects such as intelligent tires that sense the condition ofthe road and adjust the driving behavior accordingly. The concept of ‘‘inject-able’’ health diagnostic,monitoring, and, eventually, surgery devices was suggested in the science fiction world in the 1960s(for instance, in the notorious ‘‘Fantastic Voyage’’ by Isaac Asimov), but it may not be fiction afterall. Yet, bringing each of these applications into reality will require power and size reduction by anotherorder ofmagnitude (if not two). The cubic-centimeter nodes of today should be reduced to true ‘‘dust’’ size

How to Make Electronics Truly Disappear?

From 10s of cm3 and 10s to 100s of mW

To 10s of mm3 and 10s of μW

Introduction 11

(i.e., cubic millimeter). This provides a true motivation for further exploration of the absolute boundariesof ultra low-power design, which is the topic of Chapter 11 in this book.

How Much Energy Can One Scavenge in 1 cm3?

Thermal

Air Flow

Solar

Vibrations

Slide 1.19

Energy scavenging is anessential component forthe success of microwattnodes. The idea is to trans-form the physical energypresent in various sourcesin the environment intoelectrical power. Examplesof the former are tempera-ture or pressure gradients,light, acceleration, andkinetic and electromagneticenergy. In recent years,researchers both in aca-demics and in industryhave spent substantialefforts in cataloguing andmetricizing the effective-ness of the various scaven-

ging technologies [Roundy03, Paradiso05]. The efficiency of an energy harvester is best expressedby the average power provided by a scavenger of 1 cm3, operating under various conditions. Justlike with batteries, scavenging efficiency is linearly proportional to volume (or, as in the case forsolar cells, to surface area).

From the table presented in the slide, it is clear that light (captured by photovoltaic cells) is by farthe most efficient source of energy, especially in outdoors conditions. A power output of up to15mW/cm2 can be obtained. Unfortunately, this drops by two or three orders of magnitudes whenoperated in ambient indoor conditions. Other promising sources of energy that are ubiquitouslyavailable are vibration, wind, and temperature and pressure gradients. The interested reader canrefer to the above-mentioned reference works for more information. The main takeaway is thataverage power levels of around 100W/cm3 are attainable in many practical situations.

The discussion so far has not included some other sources of energy, magnetic and electro-magnetic, that are prime targets for scavenging. Putting moving coils in a magnetic field (or havinga variable magnetic field) induces current in a coil. Similarly, an antenna can capture the energybeamed at it in the form of an electromagnetic wave. This concept is used effectively for thepowering of passive RF-IDs. None of these energy sources occurs naturally though, and an‘‘energy transmitter’’ has to be provided. Issues such as the impact on health should be considered,if large power levels are required. Also, the overall efficiency of these approaches is quite limited.

12 Chapter #1

A Side Note: What Can One Do with 1 cm3?

Reference case: the human brain

Pavg(brain): 20 W (20% of the total dissipation, 2% of the weight)

Power density: ~15 mW/cm3

Nerve cells only 4% of brain volume Nerve cells only 4% of brain volume Average neuron density: 70 million/cmAverage neuron density: 70 million/cm33

Slide 1.20

This introduction has so farfocused on the variousapplication domains ofmicroelectronics and theirpower needs and con-straints. In the subsequentslides, we will discuss theenergy and power trendsfrom a technology perspec-tive, looking back at pastevolutions and projectingfuture developments.Before doing so, one moreside note is probably use-ful. To put the energy effi-ciency of microelectronicsystems into perspective, it

is worth comparing them with other ‘‘computational engines’’, in this case biological machinery(i.e., the brain).

The average power consumption of an average human brain approximately equals 20W, whichis approximately 20% of the total power dissipation of the body. This fraction is quite high,especially when considering that the brain represents only 2% of the total body mass� in fact, theratio of power to the brain versus the total body power is a telling indicator of where the beingstands on the evolutionary ladder. Again considering the average brain size (1.33 dm3), this leads toa power consumption of 15mW/cm3 – similar to what could be provided by 1 cm2 of solar cells.Active neurons only represent a small fraction of this volume (4%) –most of the rest is occupied byblood vessels, which transport energy in and heat out of the brain, and the dense interconnectingnetwork.

Judging the energy efficiency of the brain is a totally different matter, though. Comparing the‘‘computational complexity’’ of a neuron with that of a digital gate or a processor is extremely hard,if not irrelevant. The brain contains on the average 70million neurons per cubic centimeter, each ofwhich performs complex non-linear processing. For the interested readers, a great analysis of andcomparison between electronic and neurological computing is offered in the best-selling book byRay Kurzweil, ‘‘The Singularity Is Near.’’

Introduction 13

Power Versus Energy

� Power in high-performance systems– Heat removal– Peak power and its impact on power delivery networks

� Energy in portable systems– Battery life

� Energy/power in “zero-power systems”– Energy-scavenging and storage capabilites

� Dynamic (energy) vs. static (power) consumption– Determined by operation modes

Slide 1.21

Before discussing trends,some words about usefulmetrics are necessary(more details to follow inChapter 3). So far, wehave used the terms powerand energy quite inter-changeably. Yet, each hasits specific role dependingupon the phenomena thatare being addressed or theconstraints of the applica-tion at hand. Averagepower dissipation is theprominent parameter when

studying heat-removal and packaging concerns of high-performance processors. Peak powerdissipation, on the other hand, is the parameter to watch when designing the complex power supplydelivery networks for integrated circuits and systems.

When designing mobile devices or sensor network nodes, the type of energy source determineswhich property is the most essential. In a battery-powered system, the energy supply is finite, andhence energy minimization is crucial. On the other hand, the designer of an energy-scavengingsystem has to ensure that the average power consumed is smaller than the average power providedby the scavenger.

Finally, dividing power dissipation into dynamic (proportional to activity) and static (indepen-dent of activity) is crucial in the design of power management systems exploiting the operationalmodes of the system. We will see later that the reality here is quite complex and that a carefulbalancing between the two is one of the subtleties of advanced low-power design.

Slide 1.22

While concerns about power density may seem quite recent to most designers, the issue hassurfaced a number of times in the design of (electrical) engineering systems before. Obviouslyheat removal was and is a prime concern inmany thermodynamic systems. In the electronics world,power dissipation, and consequent high temperatures, was amain cause of unreliability in vacuum-tube computers. While bipolar computer design offered prime performance, exceeding what couldbe delivered by MOS implementations at that time, power density and the ensuing reliabilityconcerns limited the amount of integration that could be obtained. The same happened with pureNMOS logic – the static current inherent in non-complimentary logic families ultimately causedsemiconductor manufacturers to switch to CMOS, even though this meant an increased processcomplexity and a loss in performance. When CMOS was adopted as the technology-of-choice inthe mid 1980s, many felt that the power problem had been dealt with effectively, and that CMOSdesign would enjoy a relatively trouble-free run to ever higher performance. Unfortunately, it wasnot to be. Already in the early 1990s, the ever-increasing clock frequencies and the emergence ofnew application domains brought power back to the foreground.

The charts in this slide document how the increases in heat flux in bipolar and CMOS systemsmirror each other, only offset by about a decade. Theymake the interesting point that exponentialsare hard to get around. New technologies create a fixed offset, but the exponential increases in

14 Chapter #1

complexity – so essential tothe success of the semicon-ductor industry – conspireto eliminate that in theshortest possible time.

Power Trends for Processors

Pow

er p

er c

hip

[W]

1980 1985 1990 1995 20000.01

0.1

1

10

100

1000

Year[Ref: T. Sakurai, ISSCC’03]

MPU

x4 / 3

year

s

DSP

x1.4 / 3 years© IEEE 2003

Slide 1.23

The power trends of thepast are best observed byempirically sampling theleading processor designsover the years (as embodiedby publications in ISSCC,the leading conference inthe field) [Courtesy ofT. Kuroda and T. Sakurai].Plotting the power dissipa-tions of microprocessorsand DSPs as a function oftime reveals some interest-ing trends. Up to the mid1990s, the average powerdissipation of a processorrose by a factor of fourevery three years. At that

time, a discontinuity occurred. A major slowdown in the rise of power dissipation of leading-edge processors is apparent (to approximately a factor of 1.4 every three years). Simultaneously,another downward vector emerged: owing to the introduction of mobile devices, a market forlower-power lower-performance processors was materializing. One obviously wonders about the

Power Evolution over Technology Generations

Introduction of CMOS over bipolar bought the industry 10 years(example: IBM mainframe processors)

[Ref: R. Chu, JEP’04]

Year of Announcement1950 1960 1970 1980 1990 2000 2010

Mod

ule

Hea

t Flu

x(w

/cm

2 )

0

2

4

6

8

10

12

14

Bipolar

CMOS

VacuumIBM 360

IBM 370IBM 3033

IBM ES9000

Fujitsu VP2000

IBM 3090S

NTT

Fujitsu M-780

IBM 3090

CDC Cyber 205IBM 4381

IBM 3081Fujitsu M380

IBM RY5

IBM GP

IBM RY6

Apache

Pulsar

Merced

IBM RY7

IBM RY4

Pentium II(DSIP)

T-Rex

Squadrons

Pentium 4

Mckinley

Start ofWater Cooling

Prescott

Jayhawk(dual)

©ASME 2004

Introduction 15

discontinuity around 1995, the answer for which is quite simple: Owing to both power andreliability concerns, the semiconductor industry finally abandoned the idea of a supply voltagefixed at 5V (the ‘‘fixed-voltage scaling model’’), and started scaling supply voltages in correspon-dence with successive process nodes. Fixed-voltage scaling was an attractive proposition, as itsimplified the interfacing between different components and parts, yet the power cost becameunattainable. Reasoning about the precise value of the slope factors is somewhat simplified whenstudying power density rather than total power, as the former is independent of the actual die size.

PDYNAMIC k0.7

Proportional V scaling and short-channel devices

PDYNAMIC k0kk .7

Proportional V scaling andshort-channel devices

Power Density Trend for Processors

P = PDYNAMIC (+ PLEAK)

Scaling the Prime Reason!

Pow

er d

ensi

ty :

p [W

/cm

2 ]

0.1

1

10

100

1000

1 10

Design rule [µm]0.11

Scaling variable: k

k3

10000

k0.7

MPU DSP

Constant-voltage scalingand long-channel devices

PDYNAMIC k 3

Proportional-voltage scalingand short-channel devicest

P

© IEEE 2003

∝

∝

∝

DYNAMIC k 0.7∝

→→

[Ref: T. Sakurai, ISSCC’03]

Slide 1.24

Under the assumptionsof fixed-voltage scaling[see Rabaey03] and long-channel devices (moreabout this in Chapter 2 ondevices), it is assumed thatthe supply voltage remainsconstant and the dischargecurrent scales. Under theseconditions, the clock fre-quency f scales betweentechnology generations ask2, where k is the technol-ogy scaling factor (whichtypically equals 1.41). Thepower density

p ¼ CVDD2f

then evolves as

kp ¼ k� 1� k2 ¼ k3:

Consider now the situation after 1995. Under the full-scaling mode, supply voltages were scaledin proportion to the minimum feature size of the technology. Also at that time, short-channeldevice effects such as velocity saturation (again see Chapter 2) were becoming important, causingthe saturation current (i.e., the maximum discharge current) to scale approximately as k�0.3,leading to a slowdown in the clock frequency increase to k1.7. For the power density, this meansthat

p ¼ CVDD2f

now scales as

kp ¼ k� ð1=kÞ2 � k1:7 ¼ k0:7;

16 Chapter #1

which corresponds with the empirical data. Even though this means that power density is stillincreasing, a major slowdown is observed. This definitely is welcome news.

Evolution of Supply Voltages in the Past

Minimum Feature Size (μm)10–11

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Sup

ply

Vol

tage

(V

)

Supply voltage scaling only from the 1990s

Slide 1.25

To illustrate the fact that thefull scaling model was trulyadopted starting around the0.65 mm CMOS technologynode, this slide plots therange of supply voltagesthat were (are) typicallyused for every generation.Up to the early 1990s,supply voltages were prettymuch fixed at 5V, droppingfor the first time to 3.3V forthe 0.35mm generation.Since then, supply voltageshave by and large followedthe minimum feature size.

For instance, the nominal supply voltage for the 180nm processor equals 1.8V; for 130nm it is1.3V; and so on. Unfortunately, this trend is gradually changing for the worse again, upsetting thesubtle balance between performance and power density, as will become clear in the following slides.

Sub-threshold Leakage as an Extra Complication

[Ref: T. Sakurai, ISSCC’03]

2002 ’04 ’06 ’08 ’10 ’12 ’14 ’160

1

2

Year

PDYNAMIC

P LEAK

Po

wer

[µ

W /

gat

e]

Subthreshold leak(Active leakage)

Year2002’04 ’06 ’08 ’10 ’12 ’14 ’160

0.2

0.4

0.6

0.8

1

1.2

0

20

40

60

80

100

120

Tec

hn

olo

gy

no

de[

nm

]

Vo

ltag

e [V

]

VTH

VDD

Technologynode

©IEEE 2003

Slide 1.26

By the end of the 20th cen-tury, new storm clouds weregathering on the horizon.The then prevalent scalingmodelmade the assumptionthat a certain ratio betweensupply voltage and thresh-old voltage is maintained.If not, a substantial degra-dation in maximum clockspeed (which was generallyequated to system perfor-mance) results, a penaltythat the designers of thattime were not willing toaccept. The only plausible

solution to address this challenge was to maintain a constant ratio by scaling the threshold voltagesas well. This, however, posed a whole new problem. As we will discuss in detail in later chapters, theoff-current of aMOS transistor (i.e., the current when the gate–source voltage is set to zero) increasesexponentially with a reduction in the threshold voltage. Suddenly, static power dissipation � aproblem that had gone away with the introduction of CMOS � became a forefront issue again.Projections indicated that, if left unattended, static power dissipationwould overtake dynamic powersometime in the mid to late 2000s.

Introduction 17

Static Power (Leakage) May Ruin Moore’s Law

Pow

er p

er c

hip

[W

]

1980 1985 1990 1995 20000.01

0.1

1

10

100

1000

Year

MPU

x4 / 3

year

s

DSP

x1.4 / 3 years

Processors published in ISSCC

2005 2010 2015

x1.1 / 3 years

ITRS requirement

10000

Dynamic

[Ref: T. Sakurai, ISSCC’03]

Leakage

1/100© IEEE 2003

Slide 1.27

The problem was such thatone was afraid that leakagemight become the undoingof Moore’s law. While theInternational TechnologyRoadmap for Semiconduc-tors (ITRS) was prescrib-ing a further slowdown inthe average power dissipa-tion (by a factor ofapproximately 1.1 everythree years), static powerdissipation potentially wasregistering a very rapidincrease instead.

Fortunately, designershave risen to the challengeand have developed a range

of techniques to keep leakage power within bounds. These will be described in detail in later chapters.Yet, static power has become a sizable fraction of the overall power budget of today’s integratedcircuits, and most indicators suggest that this problem will only get more severe with time.

Power Density Increases

4004

20102000199019801970

8008

80808085

8086

286386

486Pentium® proc

P6

1

10

100

1000

10000

Year

Po

wer

Den

sity

(W

/cm

2 )

Hot Plate

Nuclear Reactor

Rocket Nozzle

Sun’s Surface

UpperBound?

Unsustainable in the long term

[Courtesy: S. Borkar, Intel]

Slide 1.28

There exist very compellingreasons why a furtherincrease in power densityshould be avoided at allcosts. As shown in an ear-lier slide for the PowerPC 4,power densities on chipscan become excessive andlead to degradation orfailure, unless extremelyexpensive packaging techni-ques are used. To drive thepoint home, power densitylevels of some well-knownprocessors are comparedto general-world examples,such as hot plates, nuclearreactors, rocket nozzles, or

even the sun’s surface. Surprisingly, high-performance ICs are not that far off from some of theseextreme heat sources! Classic wisdom dictates that power densities above 150W/cm2 should beavoided for themajority of designs, unless the highest performance is an absolutemust and cost is notan issue.

18 Chapter #1

Projecting into the Future

1

10

100

1000

2006 20082004 20162014 20202018 202220122010

Active power density: k

1.9

Leakage power density: k

2.7

Computing density: k

3

FD-SOI Dual Gate

Power density (active and static) accelerating anewTechnology innovations help, but impact limited

Slide 1.29

At this point, it is worthgazing into the future a bitand injecting some projec-tions on how voltages,power, and computing den-sities may evolve over thecoming decades. Theplotted curves are basedon the 2005 version of theITRS. Obviously, unfore-seen innovations in manu-facturing, devices, anddesign technology maydrastically alter the slopeof some of these curves.Hence, they should betaken with a grain of salt.

Yet, they help to present the dire consequences of what would happen if we do not act and identifyareas where intensive research is necessary.

The first observation is that computing density (defined as the number of computations per unitarea and time) continues to increase at a rate of k3. This assumes that clock frequencies continue torise linearly, which is probably doubtful considering the other trends. The dynamic power density isprojected to accelerate anew (from k0.7 to k1.9). This is particularly bad news, and is mainly due to acontinuing increase in clock speed combined with a slowdown in supply voltage scaling (as is plottedin the next slide). The latter is a necessity if static power dissipation is to be kept somewhat withinbounds. Yet, even when accounting for a slowdown in supply- and threshold-voltage scaling, andassuming some technology and device breakthroughs such as full-depleted SOI (FD-SOI) and dual-gate transistors, static power density still grows at a rate of k2.7. This means that leakage power if leftunattended will come to dominate the power budget of most integrated circuits.

Most probably, the above scenario will not play out. Already clock frequencies of leadingprocessors have saturated, and architectural innovations such as multi-core processing are usedto maintain the expected increase in overall performance. The obtained slack can be used to reduceeither dynamic or static power, or both. In addition, the heterogeneous composition of most SoCsmeans that different scenarios apply to various parts of the chip.

Introduction 19

Complicating the Issue: The Diversity of SoCs

Power budgets of leading general purpose (MPU) and specialpurpose (ASSP) processors

[Ref: many combined sources]

Slide 1.30

To emphasize the last argu-ment, this slide plots thepower budget of a numberof microprocessors andDSPs from different com-panies. The distribution ofpower over differentresources, such as compu-tation, memory, clock, andinterconnect, varies wildly.Looking forward, thistrend will only accelerate.Complex SoCs for commu-nication, media processing,and computing contain awide variety of componentswith vastly different perfor-mance and activity profiles(including mixed signal,

RF, and passive components). Managing the different scaling trajectories of each of these is thetask of the ‘‘power management’’, which is the topic of Chapter 10.

Supply and Threshold Voltage Trends

VDD

VT

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

VDD /

VTH = 2

Voltage reduction projected to saturateOptimistic scenario – some claims exist that VDD may get stuck around 1 V

[Ref: ITRS 05, Low power scenario]

2006 20082004 20162014 20202018 202220122010

Slide 1.31

Leakage concerns put alower bound on the thresh-old voltages. Barring the(improbable) event that aleakage-resistant logic familysuddenly emerges, thresholdvoltages are unlikely to dropbelow 0.25V. This severelyimpedes further scaling ofthe supply voltages. TheITRS (low-power scenario)optimistically projects thatsupply voltages will bereduced to 0.5V. Gettingthere presents a severechallenge though. It is evendoubtful whether reliablememories are feasible at all

at these low voltage levels.Innovations at the device and circuit level may come somewhat to the rescue. Transistors with

higher mobility are currently researched at a number of institutions. Higher current drive means

20 Chapter #1