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Jan M. Rabaey
Low Power Design Essentials ©2008 Chapter 11
Ultra-Low Power/Voltage Design
Low Power Design Essentials ©2008 11.2
Chapter Outline
Rationale Lower Bounds on Computational Energy Subthreshold Logic Moderate Inversion as a Trade-off Revisiting Logic Gate Topologies Summary
Low Power Design Essentials ©2008 11.3
Rationale
Continued increase of computational density must be combined with decrease in energy/operation (EOP).
Further scaling of supply voltage essential to accomplish that– The only other option is to keep on reducing activity
Some key questions:– How far can the supply voltage be scaled?– What is the minimum energy per operation that can
be obtained theoretically and practically?– What to do about the threshold voltage and leakage?– How to practically design circuits that approach the
minimum energy bounds?
Low Power Design Essentials ©2008 11.4
Opportunities for Ultra-Low Voltage
Number of applications emerging that do not need high performance, only extremely low power dissipation
Examples:– Standby operation for mobile components– Implanted electronics and artificial senses– Smart objects, fabrics and e-textiles
Need power levels below 1 mW (even mW in certain cases)
Low Power Design Essentials ©2008 11.5
Minimum Operational Voltage of Inverter
Swanson, Meindl (April 1972) Further extended in Meindl
(Oct 2000)Limitation: gain at midpoint > -1
Cox: gate capacitanceCd: diffusion capacitancen: slope factor
For ideal MOSFET (60 mV/decade slope):
)1ln()(2(min)
)2ln()(2(min)
nq
kTV
C
C
q
kTV
DD
ox
dDD
Vq
kT
q
kTVDD 036.038.1)2ln(2(min)
at 300° K
or
[Ref: R. Swanson, JSSC’72; J. Meindl, JSSC’00]
© IEEE 1972
Low Power Design Essentials ©2008 11.6
Subthreshold Modeling of CMOS Inverter
From Chapter 2:
qkT
V
qkTn
V
qkT
V
qkTn
VV
SDS
DSGSDSTHGS
eeIeeII 11 0
(DIBL can be ignored at low voltages)
with
qkTn
V
S
TH
eII
0
Low Power Design Essentials ©2008 11.7
Subthreshold DC model of CMOS Inverter
Assume NMOS and PMOS are fully symmetrical and all voltages normalized to the thermal voltage FT = kT/q(xi = Vi/FT; xo = Vo/FT; xD = VDD/FT)
The VTC of the inverter for NMOS and PMOS in subthreshold can be derived:
[Ref: E. Vittoz, CRC’05]
)2
4)1(1ln(
2 Dx
Do
GeGGxx
with nxx DieG /)2(
so that
)2(
)1(2oDoD
DoDo
xxxx
xxxx
V eeen
eeeA
neA DxV /)1( 2/
max and
For |AVmax| = 1: xD = 2ln(n+1)
Low Power Design Essentials ©2008 11.8
Results from Analytical Model
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 21
2
3
4
5
6
7
n
x dAmax=1
Amax=2
Amax=4
Amax=10
Normalized VTC for n=1.5 as a function of VDD (xd)
Subthreshold InverterMinimum supply voltage for a given maximum gain as a function of the slope factor n
[Ref: E. Vittoz, CRC’05]
xdmin = 2ln(2.5) = 1.83 for n=1.5xd =4 sufficient for reliable operation
xD=8
xD=6
xD=4
xD=1
xD=2 n=1.5
0 1 2 3 4 5 6 7 80
1
2
3
4
5
6
7
8
xi
x o
Low Power Design Essentials ©2008 11.9
Confirmed by simulation (at 90 nm)
0.5 1 1.5 2 2.5 340
45
50
55
60
65
70
75
80
85
90
Observe: non-symmetry of VTC increases VDDmin
For n =1.5,VDDmin = 1.83 FT
= 48 mV
Minimum operational supply voltage
pn-ratio
VD
Dm
in (
mV
)
Low Power Design Essentials ©2008 11.10
Also Holds for More Complex Gates
Degradation due toasymmetryMinimum operational supply voltage
(2-input NOR)
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3
mV
pn ratio
both inputs one input
pn-ratio
Low Power Design Essentials ©2008 11.11
Minimum Energy per Operation
Moving one electron over VDDmin:– Emin = QVDD/2 = q 2(ln2)kT/2q = kTln(2)
– Also called the Von Neumann-Landauer-Shannon bound– At room temperature (300K): Emin = 0.29 10-20 J
Minimum sized CMOS inverter at 90 nm operating at 1V– E = CVDD
2 = 0.8 10-15 J, or 5 orders of magnitude larger!
J. von Neumann,[Theory of Self-Reproducing Automata, 1966].
Predicted by von Neumann: kTln(2)
How close can one get?
[Ref: J. Von Neumann, Ill’66]
Low Power Design Essentials ©2008 11.12
Propagation Delay of Subthreshold Inverter
T
DD
n
VDD
on
DDp
eI
CV
I
CVt
0
Normalizing tp to t0 = CFT/I0:
nxD
pp
Dext /
0
(for VDD >> FT)
Comparison betweencurve-fitted model and simulations (FO4, 90 nm)
3 4 5 6 7 8 9 100
20
40
60
80
100
120
xd
t p
0 = 338
n = 1.36
(nse
c)
Low Power Design Essentials ©2008 11.13
Dynamic Behavior
Also: Short circuit current ignorable if input rise time smaller than t0, or balanced slopes at in- and outputs
0 0.5 1 1.5 2 2.50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (normalized to t0)
Vol
tage
(n
orm
. to
4F T
)
Transient response
tr = 2t0t00.5t0
0
tp
tp as a function of trise
0 0.5 1 1.5 2 2.5 30.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
triset p
(normalized to 0)
xD = 4
Low Power Design Essentials ©2008 11.14
Power Dissipation of Subthreshold Inverter
Pdyn = CVDD2f (nothing new)
Short-circuit power can be ignored (< 1%) for well-proportioned circuits and xD >= 4
1 2 3 4 5 6 7 8 9 100.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
xD
I Sta
tI 0
n=1.5
circuit fails
logic levels degenerate
Leakage current equal to I0 for xD >= 4 (ignores DIBL)
Increases for smaller values of xD due to degeneration of logic levels
)12
()2
(/
0
2
02
nxD
TDD
pDDstatdyn De
xC
VIt
CVPPP
Low Power Design Essentials ©2008 11.15
Power-Delay Product and Energy-Delay
)2
()( /2
2nx
D
T
p DexC
Ptpdp
)
2()
/( //3
02
2
nxnxD
T
p DD eexC
Pted
3 4 5 6 7 8 9 100
1
2
3
4
5
6
7
8
9
10
xd
pdp
For low activity (a << 1), large xD advantageous!
3 4 5 6 7 8 9 100
0.5
1
1.5
ed
xd
=1 =.5=.25
=.1
=.01
=.05
=1=.5
=.25
=.1
=.01
Low Power Design Essentials ©2008 11.16
Energy for a Given Throughput
Most important question – assuming 1/T = a/2tp what minimizes the energy for a given task?
)2
1()( /2
2nx
D
T
DexC
PTe
3 4 5 6 7 8 9 10 11 12101
102
103
104
xd
ener
gy
Energy minimized by keeping a as high as possible and have computation occupy most of the time – use minimum voltage that meets T
If a must be low because of topology (< 0.05), there exists an optimum voltage that minimizes the energy
a=1
a=.1
a=.05
a=.01
a=.005
a=0.001
dynamic power dominates
Low Power Design Essentials ©2008 11.17
Example: Energy-Aware FFT
[Ref: A. Wang, ISSCC’04]
Architecture scales gracefully from 128 to 1024 point lengths, and supports 8b and 16b precision.
© IEEE 2004
Low Power Design Essentials ©2008 11.18
FFT Energy-Performance Curves
The optimal VDD for the 1024-point, 16b FFT is estimated from switching and leakage models for a 0.18mm process.
Op
timal (V
DD , V
TH )
Threshold Voltage (VTH)
Su
pp
ly V
olt
age
(VDD)
[Ref: A. Wang, ISSCC’04]
© IEEE 2004
Low Power Design Essentials ©2008 11.19
SubThreshold FFT
0.18mm CMOS process VDD=180mV-900mV fclock = 164Hz-6MHz. At 0.35V, Energy = 155nJ/FFT;
fclock = 10kHz; W = 0.6mW
Data Memory
TwiddleROMs
ButterflyDatapath
Control logic
2.1
mm
2.6 mm
VDD(mV)
Clo
ck fr
eque
ncy
VDD(mV)
1024-point, 16 bit
measured
estimatedEne
rgy
(nJ)
[Ref: A. Wang, ISSCC’04]
© IEEE 2004
Low Power Design Essentials ©2008 11.20
Challenges in Sub-Threshold Design
Obviously only for very low speed design Analysis so far only for symmetrical gates
– minimum operation voltage increases for non-symmetrical structures
Careful selection of and sizing logic structures is necessary – Data dependencies may cause gates to fail
Process variations further confound the problem
Registers and memory a major concern
Low Power Design Essentials ©2008 11.21
Logic Sizing Considerations
Wp (max)
Inverter with a minimum sized Wn
0 1Wp (min)
drive currentleakage current CMOS in subthreshold is
“ratioed logic” Careful sizing of transistors
necessary to ensure adequate logic levels
Max Size
Min Size
OperationalRegion
[Ref: A. Wang, ISSCC’04]
180 nm CMOS
© IEEE 2004
Low Power Design Essentials ©2008 11.22
Logic Sizing Considerations
Wp(max)SF corner
Wp(min)FS corner
Wp(m
ax)
Inverter sizing analysis and minimum supply voltage analysis must be performed at the process corners.
Variations raise the minimum voltage the circuit can be run at.
Impact of Process Variations
OperationalRegion
[Ref: A. Wang, ISSCC’04]
© IEEE 2004
Low Power Design Essentials ©2008 11.23
The Impact of Data Dependencies
B
Z
B
AA
XOR1
Z
B
B
A
B
A
XOR2
100
50
01m 2m 3m 4m0
A=1 B=0
A=0 B=1
A=0 B=0
A=1 B=1
Voltage level at Z (mV)
50
0
Voltage level at Z (mV)
100
1m 2m 3m 4m0
A=1 B=0
A=0 B=1
A=0 B=0
A=1 B=1
[Ref: A. Wang, ISSCC’04]
© IEEE 2004
Low Power Design Essentials ©2008 11.24
The Impact of Data Dependencies
idle current
drive current
A=1, B=0, Z=1Z
Leakage through the parallel devices causes XOR1 to fail at 100mV.
XOR1
idle current
drive current
A=1, B=0, Z=1
weak drive current
Z
Balanced number of devices reduces the effects of leakage and process variations.
XOR2
Solid sub-threshold design requires symmetry for all input vectors
[Ref: A. Wang, ISSCC’04]
© IEEE 2004
Low Power Design Essentials ©2008 11.25
The Sub-Threshold (Low Voltage) Memory Challenge
Obstacles that limit functionality at low voltage– SNM– Write margin– Read current / bit-line leakage – Soft errors– Erratic behavior
Read SNM worst challengeSNM read
SNM hold
SNM for sub-VT, 6T cell at 300mV
Variation aggravates situation
Low Power Design Essentials ©2008 11.26
Solutions to Enable Sub-VTH Memory
Standard 6T way of doing business won’t work Voltage scaling versus transistor sizing
– Current depends exponentially on voltages in sub-threshold
– Use voltages (not sizing) to combat problems
New bitcells– Buffer output to remove Read SNM– Lower BL leakage
Complemented with architectural strategies– ECC, interleaving, SRAM refresh, redundancy
Low Power Design Essentials ©2008 11.27
Sub-threshold SRAM Cell
[Ref: B. Calhoun, ISSCC’06]
Buffered read allows separate Read, Write ports
Removing Read SNM allows operation at lower VDD with same stability at corners;
WL_WR BLBBL
QQB
VVDD
RBLRWL
floating
VVDD floats during write access, but feedback restores ‘1’ to VDD
QB=1
RBL=10
QBB heldnear 1 byleakage
QB=0
RBL=10QBB =1
leakagereducedby stack
Buffer reduces BL leakage: Allows 256 cells/BL instead of 16 cells/BLHigher integration reduces area of peripheral circuits
© IEEE 2006
Low Power Design Essentials ©2008 11.28
Sub-threshold SRAM
Chip functions without error to below 400mV, holds without error to <250mV: At 400mV, 3.28mW and 475kHz at
27oC Reads to 320mV (27oC) and
360mV (85oC) Write to 380mV (27oC) and 350mV
(85oC)
256kb SRAM Array
32k
b B
lock
[Ref: B. Calhoun, ISSCC’06]
Sub-VTH operation demonstrated in 65nm memory chip
Low Power Design Essentials ©2008 11.29
Example: Sub-Threshold Microprocessor
Processor for sensor network applications
I-Mem8-bit words
ROM8-bit words
Pre
fetch
Bu
ffer
32
bits
Reg File
Acc
32
bits
Shifterx1
D-Mem
ALU
IF-STAGE
CONTROL LOGIC
ID-STAGE EX/MEM-STAGE
8 x 16 bits16 x 8 bits32 x 4 bits
81632
8-bit16-bit32-bit
8-bit words16-bit words32-bit words
81632
EventScheduler
ExternalInterrupts
I-Mem8-bit words
ROM8-bit words
Pre
fetch
Bu
ffer
32
bits
Reg File
Acc
32
bits
Shifterx1
D-Mem
ALU
IF-STAGE
CONTROL LOGIC
ID-STAGE EX/MEM-STAGE
8 x 16 bits16 x 8 bits32 x 4 bits
8 x 16 bits16 x 8 bits32 x 4 bits
81632
81632
8-bit16-bit32-bit
8-bit16-bit32-bit
8-bit words16-bit words32-bit words
8-bit words16-bit words32-bit words
81632
81632
EventScheduler
ExternalInterrupts
– Simple 8-bit architecture to optimize energy efficiency
– 3.5 pJ per instruction at 350mV and 354 kHz operation
– 10X less energy than previously reported
– 11 nW at 160 mV (300 mV RBB)– 41 year operation on 1g Li-ion
battery
[Ref: S. Hanson, JSSC’07]
© IEEE 2007
Low Power Design Essentials ©2008 11.30
Prototype Implementation
6 subliminal processors
large solar cell
solar cell for adders
level converter array
discrete adders
processor memories
test memories
solar cell for processor
discrete cells / xtors
solar cell for discretes
test module
Level converter array
Chip Layout with 7 processors
[Courtesy: D. Blaauw, Univ. Michigan]
Low Power Design Essentials ©2008 11.31
Is Sub-threshold the Way to Go?
Achieves lowest possible energy dissipation But … at a dramatic cost in performance
0.00.5
1.0
1.52.02.5
3.03.5
0 0.2 0.4 0.6 0.8 1
VDD (V)
t p
(ms)
130 nm CMOS
Low Power Design Essentials ©2008 11.32
In Addition: Huge Timing Variance
0
10
20
30
40
50
60
70
80
0 0.2 0.4 0.6 0.8 1
VDD (V)
/
(%)
Normalized timing variance increases dramatically with VDD reduction
Design for yield means huge overhead at low voltages:– Worst-case design at 300mV: > 200% overkill
Low Power Design Essentials ©2008 11.33
Increased Sensitivity to Variations
Subthreshold circuits operate at low Ion/Ioff ratios, from about a 1000 to less than 10 (at xD = 4)
Small variations in device parameters can have a large impact, and threaten the circuit operation
1 2 3 4 5 6 7 8 9 10100
101
102
103
I on
over
Iof
f
xDD
Low Power Design Essentials ©2008 11.34
ONE SOLUTION: Back Off A Bit …
The performance cost of minimum energy is exponentially high.
Operating slightly above the threshold voltage improves performance dramatically while having small impact on energy
The Challenge: Modeling in the Moderate Inversion region
Delay
Ene
rgy
Optimal E-D Trade-off Curve
Low Power Design Essentials ©2008 11.35
The EKV Model covers strong, moderate and weak inversion regions
Modeling Over All Regions of Interest
2)(2 Tox
DS
S
DS
LW
Cn
I
I
IIC
Inversion Coefficient IC measures the degree of saturation
S
DDp IIC
CVkt
with k a fit factor and
IS the specific current
and is related directly to VDD
d
ICTTH
DD
enVV
1
1ln2
[Ref: C. Enz, Analog’95]
Low Power Design Essentials ©2008 11.36
Relationship between VDD and IC
10-3
10-2
10-1
100
101
102
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
IC
V DD
Threshold changesmove curves up or downIC = 1 equals
VDD ~ VTH
90 nm CMOS
weak moderate strong
Low Power Design Essentials ©2008 11.37
10-2
100
102
10-2
10-1
100
101
102
103
IC
Nor
mal
ized
t p
Model
Simulation
Provides Good Match over Most of the Range
Largest deviations in strong inversion –Velocity saturation not well handled by simple model
stronginversion
weakinversion
Low Power Design Essentials ©2008 11.38
Modeling Energy
CVt
IVEOP DDP
leakDD 2)2
(
T
DDd
T
THDDd
n
V
n
VV
Sleak eIeII
0
10-3
10-2
10-1
100
101
102
10-16
10-15
IC
EO
P [
J]
a=1
a=0.2
a=0.02
a=0.002
Low Power Design Essentials ©2008 11.39
High Activity Scenario
0.1 1
1
1
1
2
2
2
2
4
4
4
4
6
6
6
8
8
10
10
1214
VTH
VD
D
0.010.01
0.10.1
0.1 0.1
1
1 1 1
2
2 2 2
3
3 3 3
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Equal energy
Equal performance
IC = 1
Minimum energy
(90 nm, a = 0.02)
Low Power Design Essentials ©2008 11.40
Low Activity Scenario
0.1 1
1
1
1
2
2
2
2
4
4
4
4
6
6
6
8
8
10
10
12
14
VTH
VD
D
0.010.1
0.1
0.1
111
1
1 1
2
2
2
2 2
3
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Equal energy
Equal performance
IC = 1
Minimum energy
(90 nm, a = 0.002)
Low Power Design Essentials ©2008 11.41
Example: Adder
Simple full-adder using NAND & INV only
Low Power Design Essentials ©2008 11.42
100
101
102
103
10-3
10-2
10-1
100
Optimizing over size, VDD, VTH (full range)
delay
(min delay, max energy)
ene
rgy
10-1
100
101
102
IC
Delay and energy normalized to minimum delay and corresponding maximum energy
Significant energy savings within strong inversion
Relatively little energy savings going from moderate to weak
Higher potential for energy savings when activity is lower
=0.1
=0.01
=0.001
VTH ↑
VDD ↓
[Ref: C. Marcu, UCB’06]
Low Power Design Essentials ©2008 11.43
Sensitivity to Parameter Variations
[Ref: C. Marcu, UCB’06]
Low Power Design Essentials ©2008 11.44
Moving the Minimum Energy Point
Having the minimum energy point in the sub-threshold region is unfortunate– Sub-threshold energy savings are small and expensive– Further technology scaling not offering much relief
Remember the stack effect …
Can it be moved upwards?
Or equivalently… Can we lower the threshold?
100 101 102 103 10410-3
10-2
10-1
100
101
Delay [ps]
Ene
rgy
[fJ]
90nm
65nm
45nm
32nm
22nm
Energy Limit
Low Power Design Essentials ©2008 11.45
Complex versus Simple Gates
Example (from Chapter 4)
Fan-in(2)Fan-in(4)
versus
Complex gates improve the Ion/Ioff ratio!
Low Power Design Essentials ©2008 11.46
Moving the Minimum Energy Point
stack2 stack4 stack6
VTH
VDD
Low Power Design Essentials ©2008 11.47
Complex versus Simple Gates
10-10
10-9
10-8
10-18
10-17
10-16
10-15
10-14
Delay
Ene
rgy
Nand4
NaNo2
VDD = 1VVTH = 0.1V
VDD = 0.14VVTH = 0.25V
VDD = 0.1VVTH = 0.22V
VDD = 0.34VVTH = 0.43V
VDD = 0.29VVTH = 0.38V
= 0.1
= 0.001
Low Power Design Essentials ©2008 11.48
Controlling Leakage in PTL
Pass Transistor Network
drivers receivers
• No leakage through the logic path• No VDD and GND connections in the logic path• Leverage complexity
• Confine leakage to well-defined and controllable paths
[Ref: L. Alarcon, Jolpe’07]
Low Power Design Essentials ©2008 11.49
Sense-Amplifier Based Pass-Transistor Logic (SAPTL)
Pass Transistor network
Leakage path confined toroot node driver and sense amplifier
Sense amplifier to recover delay andvoltage swing
[Ref: L. Alarcon, Jolpe’07]
S
S
senseamplifierstack
root node driver
data inputs
timing control
outputs
Low Power Design Essentials ©2008 11.50
Sense-Amplifier Based Pass-Transistor Logic (SAPTL)
RootInput
A
B S
S
P0
to senseampA
B
B
B
S S
OutOut
CK
CK CK
CK
CK
• Outputs pre-charged to VDD during low CK cycle (pre-conditioning subsequent logic module)
• Latch retains value even after inputs are pulled low
• Low voltage operation (300 mV)
• Current steering• Works with very low Ion /Ioff
• Regular and balanced• (Programmable)
[Ref: L. Alarcon, Jolpe’07]
Low Power Design Essentials ©2008 11.51
Static CMOS
SAPTL
TG-CMOS
90nm CMOSVDD : 300mV – 1VVTH 300mV
Energy-Delay Trade-off
Energy (fJ)
De
lay
(FO
4 @
1V
)
1 10 100 1K1
10
100
1K
10K
100K
VDD = 450mV SAPTLVDD = 300mV TG-CMOS
VDD = 900mV SAPTLVDD = 400mV Static CMOS
VDD =1V TG-CMOSVDD = 550mV Static CMOS
VDD scalingstill works!
20
2.5K
Sweet-spot:< 10 fJ> 2.5k FO4
10
[Ref: L. Alarcon, Jolpe07]
Low Power Design Essentials ©2008 11.52
Summary
To continue scaling, a reduction in energy per operation is necessary
This is complicated by the perceived lower limit on the supply voltage
Design techniques such as circuits operating in weak or moderate inversion, combined with innovative logic styles are essential if voltage scaling is to continue
Ultimately the deterministic Boolean model of computation
may have to be abandoned.
Low Power Design Essentials ©2008 11.53
ReferencesBooks and Book Chapters E. Vittoz, “Weak Inversion for Ultimate Low-Power Logic,” in C. Piguet, Ed., Low-Power Electronics Design, Ch. 16,
CRC Press, 2005. A. Wang, A. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems, Springer, 2006.
Articles L. Alarcon, T.T. Liu, M. Pierson, J. Rabaey, “Exploring Very Low-Energy Logic: A Case Study,” Journal of Low Power
Electronics, Vol. 3, No. 3. , December 2007. B. Calhoun and A. Chandrakasan, “A 256kb Sub-threshold SRAM in 65nm CMOS,”, Digest of Technical Papers,
ISSCC 2006, pp. 2592-2601, San Francisco, Febr. 2006. J. Chen et al, “An Ultra-Low_Power Memory with a Subthreshold Power Supply Voltage,” IEEE Journal of Solid State
Circuits, Vol. 41 No 10, pp. 2344-2353, Oct 2006. C. Enz, F. Krummenacher, and E. Vittoz, “An Analytical MOS Transistor Model Valid in All Regions of Operation and
Dedicated to Low Voltage and Low-Current Applications,” Analog Integrated Circuits and Signal Proc., vol. 8, pp. 83-114, July 1995.
S. Hanson et al., “Exploring Variability and Performance in a Sub-200-mV Processor,” in Journal of Solid State Circuits, Vol. 43, No. 4, pp. 881-891, April 2008.
R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal Res. Develop, 5:183-191, 1961.
C. Marcu, M. Mark, and J. Richmond, “Energy-Performance Optimization Considerations in All Regions of MOSFET Operation with Emphasis on IC=1”, Project Report EE241, UC Berkeley, Spring 2006.
J.D. Meindl, J. Davis,“The fundamental limit on binary switching energy for tera scale integration (TSI)”, IEEE Journal of Solid-State Circuits, Volume 35, Issue 10, pp. 1515 – 1516, Oct 2000.
M. Seok et al, “The Phoenix Processor: A 30 pW Platform for Sensor Applications,” Proceedings VLSI Symposium, Honolulu, June 2008.
Low Power Design Essentials ©2008 11.54
References (cntd)
R. Swanson and J. Meindl, “Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits,” IEEE J. Solid State Circuits, vol. SC-7, pp. 146-153, April 1972.
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