Logical Effort of Higher Valency Adders David Harris Harvey Mudd College November 2004

Logical Effort ofHigher Valency Adders

David Harris

Harvey Mudd CollegeNovember 2004

Logical Effort of Higher Valency Adders Slide 2

Outline Are higher valency adders worth the hassle? Prefix networks Building blocks Critical paths Results Conclusions


Prefix Networks

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

Precomputation

Prefix Network

PostcomputationC0C1C2C3

Cout

C4

G0:0G1:1G2:2G3:3 P0:0P1:1P2:2P3:3P4:4


Pre/post computation

Cell Term Noninverting CMOS Inverting CMOS Footed Domino Footless Domino

Bitwise LEbit9/3 9/3 6/3 * 5/6 4/3 * 5/6

PDbit6/3 + 1 6/3 7/3 + 5/6 5/3 + 5/6

Sum XOR LExor9/3 9/3 3/3 * 5/6 2/3 * 5/6

PDxor9/3 + 12/3 9/3 + 12/3 7/3 + 5/6 5/3 + 5/6

Buffer LEbuf1 * 1/2 1 * 1/2 2/3 * 5/6 * 1/2 1/3 * 5/6 * 1/2

Bitwise

PiPi'

Gi-1:0

Si_h

Pi

Ki-1:0

Pi'Si_l

Pi'Ai_h Ai_l

Bi_h

Gi

Ai_h

Bi_l

Ai_l

Pi

Ki

Sum XO

R

2 2

2

2

2

2

111

2 2

2

2

2

2

11

2

2

22 4

4

11

Gi

PiAi

Bi

BiAi

Bi

Bi

Ai

Ai

Gi-1:0

Gi-1:0 Gi-1:0Gi-1:0

Gi-1:0 Gi-1:0

Pi Pi

Pi Pi

Si

4

4

4

4

2

2

2

2

2

1

Inverting Static CMOS Footless Domino

H

H

H

H

H

tiny


Valency 2 Networks

f ( F a n o u t)

t ( W i r e T r a c k s )

l ( L o g i c L e v e l s )

0 ( 2 )

1 ( 3 )

2 ( 5 )

3 ( 9 )

0 ( 4 )

1 ( 5 )

2 ( 6 )

3 ( 8 )

2 ( 4 )

1 ( 2 )

0 ( 1 )

3 ( 7 )

K o g g e -

S to n e

S k l a n s k y

B r e n t -

K u n g

H a n -

C a r l s o nK n o w l e s

[2 , 1 ,1 ,1 ]

K n o w l e s

[4 , 2 , 1 ,1 ]

L a d n e r -

F i s c h e r

H a n -

C a r l s o n

L a d n e r -

F i s c h e r

N e w

( 1 ,1 , 1 )

( e ) K n o w le s [ 2 , 1 , 1 , 1 ]

1 : 02 : 13 : 24 : 35 : 46 : 57 : 68 : 79 : 81 0 : 91 1 : 1 01 2 : 1 11 3 : 1 21 4 : 1 31 5 : 1 4

3 : 04 : 15 : 26 : 37 : 48 : 59 : 61 0 : 71 1 : 81 2 : 91 3 : 1 01 4 : 1 11 5 : 1 2

4 : 05 : 06 : 07 : 08 : 19 : 21 0 : 31 1 : 41 2 : 51 3 : 61 4 : 71 5 : 8

2 : 0

01234567891 01 11 21 31 41 5

1 5 : 0 1 4 :0 1 3 : 0 1 2 : 0 1 1 : 0 1 0 : 0 9 : 0 8 :0 7 : 0 6 : 0 5 :0 4 : 0 3 : 0 2 : 0 1 : 0 0 : 0

1 :03 :25 :47 :69 :81 1 :1 01 3 :1 2

3 :07 :41 1 :81 5 :1 2

5 :07 :01 3 :81 5 :8

1 5 :1 4

1 5 :8 1 3 :0 1 1 :0 9 :0

0123456789101112131415

1 5 :0 1 4 :0 1 3 :0 1 2 :0 1 1 :0 1 0 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0

( f ) L a d n e r - F is c h e r

( a ) B r e n t - K u n g

1 :03 : 25 : 47 : 69 :81 1 :1 01 3 : 1 21 5 : 1 4

3 : 07 : 41 1 : 81 5 : 1 2

7 : 01 5 :8

1 1 :0

5 : 09 :01 3 :0

01234567891 01 11 21 31 41 5

1 5 : 0 1 4 : 0 1 3 : 0 1 2 : 0 1 1 : 0 1 0 :0 9 : 0 8 : 0 7 : 0 6 : 0 5 : 0 4 :0 3 : 0 2 : 0 1 : 0 0 : 0

( b ) S k la n s k y

1 :0

2 : 03 : 0

3 : 25 : 47 :69 :81 1 : 1 01 3 :1 21 5 :1 4

6 : 47 :41 0 : 81 1 : 81 4 : 1 21 5 :1 2

1 2 : 81 3 :81 4 : 81 5 :8

01234567891 01 11 21 31 41 5

1 5 : 0 1 4 : 0 1 3 : 0 1 2 : 0 1 1 : 0 1 0 : 0 9 : 0 8 : 0 7 : 0 6 : 0 5 : 0 4 : 0 3 : 0 2 :0 1 : 0 0 : 0

( c ) K o g g e - S t o n e

1 : 02 : 13 : 24 : 35 : 46 : 57 : 68 : 79 : 81 0 : 91 1 : 1 01 2 : 1 11 3 : 1 21 4 : 1 31 5 : 1 4

3 : 04 : 15 : 26 : 37 : 48 : 59 : 61 0 : 71 1 : 81 2 : 91 3 : 1 01 4 : 1 11 5 : 1 2

4 : 05 : 06 : 07 : 08 : 19 : 21 0 : 31 1 : 41 2 : 51 3 : 61 4 : 71 5 : 8

2 : 0

01234567891 01 11 21 31 41 5

1 5 : 0 1 4 : 0 1 3 : 0 1 2 : 0 1 1 :0 1 0 : 0 9 : 0 8 : 0 7 : 0 6 : 0 5 :0 4 : 0 3 : 0 2 : 0 1 : 0 0 : 0

1 : 03 : 25 : 47 : 69 : 81 1 : 1 01 3 : 1 21 5 : 1 4

3 : 05 : 27 : 49 : 61 1 : 81 3 : 1 01 5 : 1 2

5 : 07 : 09 : 21 1 : 41 3 : 61 5 : 8

01234567891 01 11 21 31 41 5

1 5 : 0 1 4 : 0 1 3 :0 1 2 : 0 1 1 : 0 1 0 : 0 9 : 0 8 : 0 7 : 0 6 : 0 5 : 0 4 : 0 3 : 0 2 : 0 1 : 0 0 : 0

( d ) H a n - C a r ls o n

( 1 , 2 , 0 )

( 0 , 3 , 0 )

( 0 , 1 , 2 )

( 3 , 0 , 0 )

( 1 , 0 , 2 )

( 0 , 0 , 3 )


Valency 3: BK

01234567891011121314151617181920212223242526

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:026:0 25:0 24:0 23:0 22:0 21:0 20:0 19:0 18:0 17:0 16:0


Valency 3: LF

0

0:026:0

26


Valency 3: Sklansky

01234567891011121314151617181920212223242526

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:026:0 25:0 24:0 23:0 22:0 21:0 20:0 19:0 18:0 17:0 16:0


Valency 3: KS

01234567891011121314151617181920212223242526

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:026:0 25:0 24:0 23:0 22:0 21:0 20:0 19:0 18:0 17:0 16:0


Valency 3: HC

01234567891011121314151617181920212223242526

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:026:0 25:0 24:0 23:0 22:0 21:0 20:0 19:0 18:0 17:0 16:0


Building Blocks Black Cells, Gray Cells, Buffers

– Black cells compute G and P– Gray cells compute G

Circuit families– Inverting Static CMOS– Noninverting Static CMOS– Footed Domino– Footless Domino


Valency 2

P1

G1:0

P1:0

K1:0P0G0

G1

K0

K1

2

1

2 2

1

111

2

G1 G01 2

2

44

4

P1

G1

G0 P1

P1

P0

2

2

22Gi:j

P0P1P1:0

H

H

H


Valency 4

G3 P3

G2P2

G1P1

G0

1

4

4

4

4

2

2

G3

P3 G2

P2 G1

P1G0

8

8

8

8 8

4

4

G3:0 G0

G1

G2

P3

P2

P1

P0

1 1 1

4

4

4

44

2

4/3

1G3

K0

K1

K2K3

P3:0

K3:0

G3:0

P3:0

P3

P0P1

P2

14/3

2

4


Delay Parameters (v=2)Term Cell Inverting

CMOSNoninverting CMOS

Footed Domino

Footless Domino

PDg 7/3 7/3 + 1 6/3 + 5/6 4/3 + 5/6

PDp 2 2 + 1 3/3 + 5/6 2/3 + 5/6

LEg1 5/3 1/2 * 5/6 1/3 * 5/6

LEg0 6/3 3/3 * 5/6 2/3 * 5/6

LEp1 Gray 6/3 3/3 * 5/6 2/3 * 5/6

LEp1 Black 10/3 6/3 * 5/6 4/3 * 5/6

LEp0 Black 4/3 3/3 * 5/6 2/3 * 5/6s




Footed Domino

Footless Domino

PDg 13/3 13/3 + 1 10/3 + 5/6 7/3 + 5/6

PDp 3 3 + 1 4/3 + 5/6 3/3 + 5/6

LEg2 7/3 4/9 * 5/6 1/3 * 5/6

LEg1 8/3 2/3 * 5/6 1/2 * 5/6

LEg0 9/3 4/3 * 5/6 3/3 * 5/6

LEp2 Gray 5/3 4/3 * 5/6 3/3 * 5/6

LEp1 Gray 9/3 4/3 * 5/6 3/3 * 5/6

LEp2 Black 10/3 8/3 * 5/6 6/3 * 5/6

LEp1 Black 14/3 8/3 * 5/6 6/3 * 5/6

LEp0 Black 5/3 4/3 * 5/6 3/3 * 5/6




Footed Domino

Footless Domino

PDg 17/3 17/3 + 1 13/3 + 5/6 10/3 + 5/6

PDp 4 4 + 1 5/3 + 5/6 4/3 + 5/6

LEg3 9/3 5/12 * 5/6 1/3 * 5/6

LEg2 10/3 5/9 * 5/6 4/9 * 5/6

LEg1 10/3 5/6 * 5/6 2/3 * 5/6

LEg0 12/3 5/3 * 5/6 4/3 * 5/6

LEp3 Gray 8/3 5/3 * 5/6 4/3 * 5/6

LEp2 Gray 6/3 5/3 * 5/6 4/3 * 5/6

LEp1 Gray 12/3 5/3 * 5/6 4/3 * 5/6

LEp3 Black 14/3 10/3 * 5/6 8/3 * 5/6

LEp2 Black 12/3 10/3 * 5/6 8/3 * 5/6

LEp1 Black 18/3 10/3 * 5/6 8/3 * 5/6

LEp0 Black 6/3 5/3 * 5/6 4/3 * 5/6


Wire Capacitance Wires contribute capacitance per length

– Count tracks t spanned by each wire = (wire cap / track) / unit inverter capacitance w = t W = sum(wi)


Delay Estimation Ideally choose best size for each gate

– Only valid if wire parasitics are negligible Alternatively, make each stage have unit drive

How much performance does this cost?– Very little unless stage efforts are nonuniform– Overestimates delay of Sklansky / LF networks

1/NFD D P NF P

1

/ 2

2 2 11

inverting static CMOS

2 others (2 gates/stage)

N

F ii

N

F i ii

D D P W f P W

D D P W f f P W


Method Create MATLAB models of adders

– For each stage, list f, p, t• Depends on architecture, valency, circuit family

– Use MATLAB to calculate total delays Compare ideal and unit drive delays for = 0

– Verifies unit drive simplification Plot D vs. # of bits


Results

# of bits

Del

ay (F

O4)

Valency 2Valency 3

Valency 4

0 500

10

20

30

Bren

t-Kun

g0 50

0

10

20

30

0 500

10

20

30

0 500

10

20

30

0 500

10

20

30La

dner

-Fisc

her

0 500

10

20

30

0 500

10

20

30

0 500

10

20

30

0 500

10

20

30

Skla

nsky

0 500

10

20

30

0 500

10

20

30

0 500

10

20

30

0 500

10

20

30

Kogg

e-St

one

0 500

10

20

30

0 500

10

20

30

0 500

10

20

30

0 500

10

20

30

Han-

Carls

on

Inverting CMOS0 50

0

10

20

30

Noninverting CMOS0 50

0

10

20

30

Footed Domino0 50

0

10

20

30

Footless Domino


Conclusions For fast prefix networks, the logical effort model

predicts that valency barely affects delay– Valency 2 designs are simpler– But most commercial designs use valency 4

Weaknesses of logical effort model– Overpredicts g for higher valency– Underpredicts p for higher valeny– Calibrate model through simulation– Or simulate entire designs

Documents

Logical Effort of Higher Valency Adders David Harris Harvey Mudd College November 2004