Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004

CMOS VLSI Design11: AddersSlide 2 Outline Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Lookahead Adder Carry-Select Adder Carry-Increment Adder Tree Adder

CMOS VLSI Design11: AddersSlide 3 Single-Bit Addition Half Adder Full Adder ABC out S 00 01 10 11 ABC S 000 001 010 011 100 101 110 111

CMOS VLSI Design11: AddersSlide 4 Single-Bit Addition Half Adder Full Adder ABC out S 0000 0101 1001 1110 ABC S 00000 00101 01001 01110 10001 10110 11010 11111

CMOS VLSI Design11: AddersSlide 5 PGK For a full adder, define what happens to carries Generate: C out = 1 independent of C G = Propagate: C out = C P = Kill: C out = 0 independent of C K =

CMOS VLSI Design11: AddersSlide 6 PGK For a full adder, define what happens to carries Generate: C out = 1 independent of C G = A B Propagate: C out = C P = A B Kill: C out = 0 independent of C K = ~A ~B

CMOS VLSI Design11: AddersSlide 7 Full Adder Design I Brute force implementation from eqns

CMOS VLSI Design11: AddersSlide 8 Full Adder Design II Factor S in terms of C out S = ABC + (A + B + C)(~C out ) Critical path is usually C to C out in ripple adder

CMOS VLSI Design11: AddersSlide 9 Layout Clever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters

CMOS VLSI Design11: AddersSlide 10 Full Adder Design III Complementary Pass Transistor Logic (CPL) Slightly faster, but more area

CMOS VLSI Design11: AddersSlide 11 Full Adder Design IV Dual-rail domino Very fast, but large and power hungry Used in very fast multipliers

CMOS VLSI Design11: AddersSlide 12 Carry Propagate Adders N-bit adder called CPA Each sum bit depends on all previous carries How do we compute all these carries quickly?

CMOS VLSI Design11: AddersSlide 13 Carry-Ripple Adder Simplest design: cascade full adders Critical path goes from Cin to Cout Design full adder to have fast carry delay

CMOS VLSI Design11: AddersSlide 14 Inversions Critical path passes through majority gate Built from minority + inverter Eliminate inverter and use inverting full adder

CMOS VLSI Design11: AddersSlide 15 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j Base case Sum:

CMOS VLSI Design11: AddersSlide 16 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j Base case Sum:

CMOS VLSI Design11: AddersSlide 17 PG Logic

CMOS VLSI Design11: AddersSlide 18 Carry-Ripple Revisited

CMOS VLSI Design11: AddersSlide 19 Carry-Ripple PG Diagram

CMOS VLSI Design11: AddersSlide 20 Carry-Ripple PG Diagram

CMOS VLSI Design11: AddersSlide 21 PG Diagram Notation

CMOS VLSI Design11: AddersSlide 22 Carry-Skip Adder Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal

CMOS VLSI Design11: AddersSlide 23 Carry-Skip PG Diagram For k n-bit groups (N = nk)

CMOS VLSI Design11: AddersSlide 24 Carry-Skip PG Diagram For k n-bit groups (N = nk)

CMOS VLSI Design11: AddersSlide 25 Variable Group Size Delay grows as O(sqrt(N))

CMOS VLSI Design11: AddersSlide 26 Carry-Lookahead Adder Carry-lookahead adder computes G i:0 for many bits in parallel. Uses higher-valency cells with more than two inputs.

CMOS VLSI Design11: AddersSlide 27 CLA PG Diagram

CMOS VLSI Design11: AddersSlide 28 Higher-Valency Cells

CMOS VLSI Design11: AddersSlide 29 Carry-Select Adder Trick for critical paths dependent on late input X Precompute two possible outputs for X = 0, 1 Select proper output when X arrives Carry-select adder precomputes n-bit sums For both possible carries into n-bit group

CMOS VLSI Design11: AddersSlide 30 Carry-Increment Adder Factor initial PG and final XOR out of carry-select

CMOS VLSI Design11: AddersSlide 31 Carry-Increment Adder Factor initial PG and final XOR out of carry-select

CMOS VLSI Design11: AddersSlide 32 Variable Group Size Also buffer noncritical signals

CMOS VLSI Design11: AddersSlide 33 Tree Adder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders

CMOS VLSI Design11: AddersSlide 34 Brent-Kung

CMOS VLSI Design11: AddersSlide 35 Sklansky

CMOS VLSI Design11: AddersSlide 36 Kogge-Stone

CMOS VLSI Design11: AddersSlide 37 Tree Adder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding 2 No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels:L + l Fanout:2 f + 1 Wiring tracks:2 t Known tree adders sit on plane defined by l + f + t = L-1

CMOS VLSI Design11: AddersSlide 38 Tree Adder Taxonomy

CMOS VLSI Design11: AddersSlide 39 Tree Adder Taxonomy

CMOS VLSI Design11: AddersSlide 40 Han-Carlson

CMOS VLSI Design11: AddersSlide 41 Knowles [2, 1, 1, 1]

CMOS VLSI Design11: AddersSlide 42 Ladner-Fischer

CMOS VLSI Design11: AddersSlide 43 Taxonomy Revisited

CMOS VLSI Design11: AddersSlide 44 Summary ArchitectureClassificationLogic Levels Max Fanout TracksCells Carry-RippleN-111N Carry-Skip n=4N/4 + 5211.25N Carry-Inc. n=4N/4 + 2412N Brent-Kung(L-1, 0, 0)2log 2 N 1212N Sklansky(0, L-1, 0)log 2 NN/2 + 110.5 Nlog 2 N Kogge-Stone(0, 0, L-1)log 2 N2N/2Nlog 2 N Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application.

Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004

cmos vlsi design11

ripple adder slide

cmos vlsi design lecture

adder abc

b slide

carryskip adder carryripple

eqns slide

area slide

Text of Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004

Logical Effort of Higher Valency Adders David Harris Harvey Mudd College November 2004

VLSI Digital System Design 1.Carry-Save, 2.Pass-Gate, 3.Carry-Lookahead, and 4.Manchester Adders

Vlsi Adders

Introduction to CMOS VLSI Design Lecture 17: Design for Testability David Harris Harvey Mudd College Spring 2004

Lecture 17: Adders - Harvey Mudd · PDF file17: Adders CMOS VLSI DesignCMOS VLSI Design 4th Ed. 24 Carry-Select Adder Trick for critical paths dependent on late input X

1 The Mudd ][: A 6502 Microprocessor Implementation E158 Introduction to CMOS VLSI Design May 7, 2008

Introduction to CMOS VLSI Design Lecture 5: Logical Effort GRECO-CIn-UFPE Harvey Mudd College Spring 2004

Lecture 12b: Adders. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 2 Generate / Propagate  Equations often factored into G and P  Generate and

Introduction to CMOS VLSI Design – Lecture 9: Circuit · PDF fileIntroduction to CMOS VLSI Design Lecture 9: Circuit Families David Harris Harvey Mudd College Spring 2004

Introduction to CMOS VLSI Design Lecture 6: Logical Effort David Harris Harvey Mudd College Spring 2007

Introduction to CMOS VLSI Design Introduction Manoel E. de Lima David Harris - Harvey Mudd College

Lecture 11: Sequential Circuit Design - Harvey Mudd · PDF fileLecture 11: Sequential Circuit Design. 11: Sequential Circuits 2CMOS VLSI DesignCMOS VLSI Design 4th Ed. ... lect11-seq.ppt

EE466: VLSI Design Lecture 13: Adders. CMOS VLSI Design11: AddersSlide 2 Outline  Single-bit Addition  Carry-Ripple Adder  Carry-Skip Adder  Carry-Lookahead

Introduction to CMOS VLSI Design Lecture 13: SRAM David Harris Harvey Mudd College Spring 2004

VLSI Arithmetic Adders & Multipliers

Lecture 17: Adders - Bangladesh University of Engineering ... · PDF file17: Adders CMOS VLSI DesignCMOS VLSI Design 4th Ed. 2 Outline Single-bit Addition ... Carry-Select Adder Trick

PowerPoint · PPT file · Web view2010-07-22 · Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004 11: Adders Slide * Brent-Kung 11:

8. Design of Adders - University of Texas at Austin jaa/vlsi/lectures/8-2.pdf · PDF file VLSI Design, Fall 2019 8. Design of Adders 13 Kogge-Stone Adder ECE Department, University

Introduction to CMOS VLSI Design Lecture 11: Adders

Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harvey Mudd College Spring 2004

Introduction to CMOS VLSI Design Lecture 15: Nonideal Transistors David Harris Harvey Mudd College Spring 2004

VLSI Design with Electric - Harvey Mudd · PDF file VLSI Design with Electric A Tutorial By David Harris Harvey Mudd College July 19, 2001 1. Introduction The Information Age is made

Introduction to CMOS VLSI Design Lecture 10: Combinational Circuits David Harris Harvey Mudd College Spring 2005

Lecture 11: CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004 2 11: Adders CMOS VLSI Design Slide 2 Outline Single-bit Addition Carry-Ripple Adder Carry-Skip

CMOS VLSI Design Introduction to CMOS VLSI Design Lecture 3: Adder Salman Zaffar Iqra Universitys Spring 2012 Slides from D. Harris, Harvey Mudd College

Introduction to CMOS VLSI Design Lecture 19: Nonideal Transistors David Harris Harvey Mudd College Spring 2007

Lecture 11: Adders - CMOS VLSI Design

Fall 2008EE 5323 - VLSI Design I - © Kia Bazargan 1 EE 5323 – VLSI Design I Kia Bazargan University of Minnesota Adders

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2007

Introduction to� CMOS VLSI� Design ��Adders