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Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004

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Text of Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004

  • Slide 1
  • Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004
  • Slide 2
  • CMOS VLSI Design11: AddersSlide 2 Outline Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Lookahead Adder Carry-Select Adder Carry-Increment Adder Tree Adder
  • Slide 3
  • CMOS VLSI Design11: AddersSlide 3 Single-Bit Addition Half Adder Full Adder ABC out S 00 01 10 11 ABC S 000 001 010 011 100 101 110 111
  • Slide 4
  • CMOS VLSI Design11: AddersSlide 4 Single-Bit Addition Half Adder Full Adder ABC out S 0000 0101 1001 1110 ABC S 00000 00101 01001 01110 10001 10110 11010 11111
  • Slide 5
  • CMOS VLSI Design11: AddersSlide 5 PGK For a full adder, define what happens to carries Generate: C out = 1 independent of C G = Propagate: C out = C P = Kill: C out = 0 independent of C K =
  • Slide 6
  • CMOS VLSI Design11: AddersSlide 6 PGK For a full adder, define what happens to carries Generate: C out = 1 independent of C G = A B Propagate: C out = C P = A B Kill: C out = 0 independent of C K = ~A ~B
  • Slide 7
  • CMOS VLSI Design11: AddersSlide 7 Full Adder Design I Brute force implementation from eqns
  • Slide 8
  • CMOS VLSI Design11: AddersSlide 8 Full Adder Design II Factor S in terms of C out S = ABC + (A + B + C)(~C out ) Critical path is usually C to C out in ripple adder
  • Slide 9
  • CMOS VLSI Design11: AddersSlide 9 Layout Clever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters
  • Slide 10
  • CMOS VLSI Design11: AddersSlide 10 Full Adder Design III Complementary Pass Transistor Logic (CPL) Slightly faster, but more area
  • Slide 11
  • CMOS VLSI Design11: AddersSlide 11 Full Adder Design IV Dual-rail domino Very fast, but large and power hungry Used in very fast multipliers
  • Slide 12
  • CMOS VLSI Design11: AddersSlide 12 Carry Propagate Adders N-bit adder called CPA Each sum bit depends on all previous carries How do we compute all these carries quickly?
  • Slide 13
  • CMOS VLSI Design11: AddersSlide 13 Carry-Ripple Adder Simplest design: cascade full adders Critical path goes from Cin to Cout Design full adder to have fast carry delay
  • Slide 14
  • CMOS VLSI Design11: AddersSlide 14 Inversions Critical path passes through majority gate Built from minority + inverter Eliminate inverter and use inverting full adder
  • Slide 15
  • CMOS VLSI Design11: AddersSlide 15 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j Base case Sum:
  • Slide 16
  • CMOS VLSI Design11: AddersSlide 16 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j Base case Sum:
  • Slide 17
  • CMOS VLSI Design11: AddersSlide 17 PG Logic
  • Slide 18
  • CMOS VLSI Design11: AddersSlide 18 Carry-Ripple Revisited
  • Slide 19
  • CMOS VLSI Design11: AddersSlide 19 Carry-Ripple PG Diagram
  • Slide 20
  • CMOS VLSI Design11: AddersSlide 20 Carry-Ripple PG Diagram
  • Slide 21
  • CMOS VLSI Design11: AddersSlide 21 PG Diagram Notation
  • Slide 22
  • CMOS VLSI Design11: AddersSlide 22 Carry-Skip Adder Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal
  • Slide 23
  • CMOS VLSI Design11: AddersSlide 23 Carry-Skip PG Diagram For k n-bit groups (N = nk)
  • Slide 24
  • CMOS VLSI Design11: AddersSlide 24 Carry-Skip PG Diagram For k n-bit groups (N = nk)
  • Slide 25
  • CMOS VLSI Design11: AddersSlide 25 Variable Group Size Delay grows as O(sqrt(N))
  • Slide 26
  • CMOS VLSI Design11: AddersSlide 26 Carry-Lookahead Adder Carry-lookahead adder computes G i:0 for many bits in parallel. Uses higher-valency cells with more than two inputs.
  • Slide 27
  • CMOS VLSI Design11: AddersSlide 27 CLA PG Diagram
  • Slide 28
  • CMOS VLSI Design11: AddersSlide 28 Higher-Valency Cells
  • Slide 29
  • CMOS VLSI Design11: AddersSlide 29 Carry-Select Adder Trick for critical paths dependent on late input X Precompute two possible outputs for X = 0, 1 Select proper output when X arrives Carry-select adder precomputes n-bit sums For both possible carries into n-bit group
  • Slide 30
  • CMOS VLSI Design11: AddersSlide 30 Carry-Increment Adder Factor initial PG and final XOR out of carry-select
  • Slide 31
  • CMOS VLSI Design11: AddersSlide 31 Carry-Increment Adder Factor initial PG and final XOR out of carry-select
  • Slide 32
  • CMOS VLSI Design11: AddersSlide 32 Variable Group Size Also buffer noncritical signals
  • Slide 33
  • CMOS VLSI Design11: AddersSlide 33 Tree Adder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders
  • Slide 34
  • CMOS VLSI Design11: AddersSlide 34 Brent-Kung
  • Slide 35
  • CMOS VLSI Design11: AddersSlide 35 Sklansky
  • Slide 36
  • CMOS VLSI Design11: AddersSlide 36 Kogge-Stone
  • Slide 37
  • CMOS VLSI Design11: AddersSlide 37 Tree Adder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding 2 No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels:L + l Fanout:2 f + 1 Wiring tracks:2 t Known tree adders sit on plane defined by l + f + t = L-1
  • Slide 38
  • CMOS VLSI Design11: AddersSlide 38 Tree Adder Taxonomy
  • Slide 39
  • CMOS VLSI Design11: AddersSlide 39 Tree Adder Taxonomy
  • Slide 40
  • CMOS VLSI Design11: AddersSlide 40 Han-Carlson
  • Slide 41
  • CMOS VLSI Design11: AddersSlide 41 Knowles [2, 1, 1, 1]
  • Slide 42
  • CMOS VLSI Design11: AddersSlide 42 Ladner-Fischer
  • Slide 43
  • CMOS VLSI Design11: AddersSlide 43 Taxonomy Revisited
  • Slide 44
  • CMOS VLSI Design11: AddersSlide 44 Summary ArchitectureClassificationLogic Levels Max Fanout TracksCells Carry-RippleN-111N Carry-Skip n=4N/4 + 5211.25N Carry-Inc. n=4N/4 + 2412N Brent-Kung(L-1, 0, 0)2log 2 N 1212N Sklansky(0, L-1, 0)log 2 NN/2 + 110.5 Nlog 2 N Kogge-Stone(0, 0, L-1)log 2 N2N/2Nlog 2 N Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application.