Introduction toCMOS VLSI

Design

Lecture 11: AddersDavid Harris

Harvey Mudd College

Spring 2004

CMOS VLSI Design11: Adders Slide 2

Outline Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Lookahead Adder Carry-Select Adder Carry-Increment Adder Tree Adder

CMOS VLSI Design11: Adders Slide 3

Single-Bit AdditionHalf Adder Full Adder

A B Cout S

0 0

0 1

1 0

1 1

A B C Cout S

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

A B

S

Cout

A B

C

S

Cout

out

S

C

out

S

C

CMOS VLSI Design11: Adders Slide 4

Single-Bit AdditionHalf Adder Full Adder

A B Cout S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A B C Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

A B

S

Cout

A B

C

S

Cout

out

S A B

C A B

out ( , , )

S A B C

C MAJ A B C

CMOS VLSI Design11: Adders Slide 5

PGK For a full adder, define what happens to carries

– Generate: Cout = 1 independent of C

• G =

– Propagate: Cout = C

• P =

– Kill: Cout = 0 independent of C

• K =

CMOS VLSI Design11: Adders Slide 6

PGK For a full adder, define what happens to carries

– Generate: Cout = 1 independent of C

• G = A • B

– Propagate: Cout = C

• P = A B

– Kill: Cout = 0 independent of C

• K = ~A • ~B

CMOS VLSI Design11: Adders Slide 7

Full Adder Design I Brute force implementation from eqns

out ( , , )

S A B C

C MAJ A B C

ABC

S

Cout

MA

J

ABC

A

B BB

A

CS

C

CC

B BB

A A

A B

C

B

A

CBA A B C

Cout

C

A

A

BB

CMOS VLSI Design11: Adders Slide 8

Full Adder Design II Factor S in terms of Cout

S = ABC + (A + B + C)(~Cout)

Critical path is usually C to Cout in ripple adder

SS

Cout

A

B

C

Cout

MINORITY

CMOS VLSI Design11: Adders Slide 9

Layout Clever layout circumvents usual line of diffusion

– Use wide transistors on critical path– Eliminate output inverters

CMOS VLSI Design11: Adders Slide 10

Full Adder Design III Complementary Pass Transistor Logic (CPL)

– Slightly faster, but more area

A

C

S

S

B

B

C

C

C

B

BCout

Cout

C

C

C

C

B

B

B

B

B

B

B

B

A

A

A

CMOS VLSI Design11: Adders Slide 11

Full Adder Design IV Dual-rail domino

– Very fast, but large and power hungry– Used in very fast multipliers

Cout _h

A_h B_h

C_h

B_h

A_h

Cout _l

A_l B_l

C_l

B_l

A_l

S_hS_l

A_h

B_h B_hB_l

A_l

C_lC_h C_h

CMOS VLSI Design11: Adders Slide 12

Carry Propagate Adders N-bit adder called CPA

– Each sum bit depends on all previous carries– How do we compute all these carries quickly?

+

BN...1AN...1

SN...1

CinCout

11111 1111 +0000 0000

A4...1

carries

B4...1

S4...1

CinCout

00000 1111 +0000 1111

CinCout

CMOS VLSI Design11: Adders Slide 13

Carry-Ripple Adder Simplest design: cascade full adders

– Critical path goes from Cin to Cout– Design full adder to have fast carry delay

CinCout

B1A1B2A2B3A3B4A4

S1S2S3S4

C1C2C3

CMOS VLSI Design11: Adders Slide 14

Inversions Critical path passes through majority gate

– Built from minority + inverter– Eliminate inverter and use inverting full adder

Cout Cin

B1A1B2A2B3A3B4A4

S1S2S3S4

C1C2C3

CMOS VLSI Design11: Adders Slide 15

Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j

Base case

Sum:

:

:

i j

i j

G

P

:

:

i i i

i i i

G G

P P

0:00:00inGCP0:00:00inGCP

0:0 0

0:0 0

G G

P P

iS

CMOS VLSI Design11: Adders Slide 16

Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j

Base case

Sum:

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P G

P P P

:

:

i i i i i

i i i i i

G G A B

P P A B

0:00:00inGCP0:00:00inGCP

0:0 0

0:0 0 0inG G C

P P

1:0i i iS P G

CMOS VLSI Design11: Adders Slide 17

PG Logic

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC0C1C2C3

Cout

C4

CMOS VLSI Design11: Adders Slide 18

Carry-Ripple Revisited

:0 1:0 i i i iG G P G

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

C0C1C2C3

Cout

C4

CMOS VLSI Design11: Adders Slide 19

Carry-Ripple PG DiagramD

elay

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Bit Position

ripplet

CMOS VLSI Design11: Adders Slide 20

Carry-Ripple PG DiagramD

elay

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Bit Position

ripple xor( 1)pg AOt t N t t

CMOS VLSI Design11: Adders Slide 21

PG Diagram Notation

i:j

i:j

i:k k-1:j

i:j

i:k k-1:j

i:j

Gi:k

Pk-1:j

Gk-1:j

Gi:j

Pi:j

Pi:k

Gi:k

Gk-1:j

Gi:j Gi:j

Pi:j

Gi:j

Pi:j

Pi:k

Black cell Gray cell Buffer

AOP tt AOP tt

CMOS VLSI Design11: Adders Slide 22

Carry-Skip Adder Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits

– Decision based on n-bit propagate signal

Cin+

S4:1

P4:1

A4:1 B4:1

+

S8:5

P8:5

A8:5 B8:5

+

S12:9

P12:9

A12:9 B12:9

+

S16:13

P16:13

A16:13 B16:13

CoutC4

1

0

C81

0

C121

0

1

0

CMOS VLSI Design11: Adders Slide 23

Carry-Skip PG Diagram

For k n-bit groups (N = nk)

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

4n4n4n4n

skipt

CMOS VLSI Design11: Adders Slide 24

Carry-Skip PG Diagram

For k n-bit groups (N = nk)

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

4n4n4n4n 4k

skip xor2 1 ( 1)pg AOt t n k t t

AOP tnt )1(2

CMOS VLSI Design11: Adders Slide 25

Variable Group Size

Delay grows as O(sqrt(N))

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

CMOS VLSI Design11: Adders Slide 26

Carry-Lookahead Adder Carry-lookahead adder computes Gi:0 for many bits

in parallel. Uses higher-valency cells with more than two inputs.

Cin+

S4:1

G4:1P4:1

A4:1 B4:1

+

S8:5

G8:5P8:5

A8:5 B8:5

+

S12:9

G12:9P12:9

A12:9 B12:9

+

S16:13

G16:13P16:13

A16:13 B16:13

C4C8C12Cout

CMOS VLSI Design11: Adders Slide 27

CLA PG Diagram

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

CMOS VLSI Design11: Adders Slide 28

Higher-Valency Cells

i:j

i:k k-1:l l-1:m m-1:j

Gi:k

Gk-1:l

Gl-1:m

Gm-1:j

Gi:j

Pi:j

Pi:k

Pk-1:l

Pl-1:m

Pm-1:j

CMOS VLSI Design11: Adders Slide 29

Carry-Select Adder Trick for critical paths dependent on late input X

– Precompute two possible outputs for X = 0, 1– Select proper output when X arrives

Carry-select adder precomputes n-bit sums– For both possible carries into n-bit group

Cin+

A4:1 B4:1

S4:1

C4

+

+

01

A8:5 B8:5

S8:5

C8

+

+

01

A12:9 B12:9

S12:9

C12

+

+

01

A16:13 B16:13

S16:13

Cout

0

1

0

1

0

1

CMOS VLSI Design11: Adders Slide 30

Carry-Increment Adder Factor initial PG and final XOR out of carry-select

5:4

6:4

7:4

9:8

10:8

11:8

13:12

14:12

15:12

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

incrementt

CMOS VLSI Design11: Adders Slide 31

Carry-Increment Adder Factor initial PG and final XOR out of carry-select

5:4

6:4

7:4

9:8

10:8

11:8

13:12

14:12

15:12

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

increment xor1 ( 1)pg AOt t n k t t

CMOS VLSI Design11: Adders Slide 32

Variable Group Size Also buffer

noncritical

signals

3:25:4

6:4

8:7

9:7

12:11

13:11

14:11

15:11

10:7

3:25:4

6:4

8:7

9:7

12:11

13:11

14:11

15:11

10:7 6:0

3:0

1:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design11: Adders Slide 33

Tree Adder If lookahead is good, lookahead across lookahead!

– Recursive lookahead gives O(log N) delay Many variations on tree adders

CMOS VLSI Design11: Adders Slide 34

Brent-Kung

1:03:25:47:69:811:1013:1215:14

3:07:411:815:12

7:015:8

11:0

5:09:013:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design11: Adders Slide 35

Sklansky

1:0

2:03:0

3:25:47:69:811:1013:1215:14

6:47:410:811:814:1215:12

12:813:814:815:8

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design11: Adders Slide 36

Kogge-Stone

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design11: Adders Slide 37

Tree Adder Taxonomy Ideal N-bit tree adder would have

– L = log N logic levels– Fanout never exceeding 2– No more than one wiring track between levels

Describe adder with 3-D taxonomy (l, f, t)– Logic levels: L + l– Fanout: 2f + 1– Wiring tracks: 2t

Known tree adders sit on plane defined by

l + f + t = L-1

CMOS VLSI Design11: Adders Slide 38

Tree Adder Taxonomy

f (Fanout)

t (Wire Tracks)

l (Logic Levels)

0 (2)1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

CMOS VLSI Design11: Adders Slide 39

Tree Adder Taxonomy

f (Fanout)

t (Wire Tracks)

l (Logic Levels)

0 (2)1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

Kogge-Stone

Brent-Kung

Sklansky

CMOS VLSI Design11: Adders Slide 40

Han-Carlson

1:03:25:47:69:811:1013:1215:14

3:05:27:49:611:813:1015:12

5:07:09:211:413:615:8

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design11: Adders Slide 41

Knowles [2, 1, 1, 1]

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design11: Adders Slide 42

Ladner-Fischer

1:03:25:47:69:811:1013:12

3:07:411:815:12

5:07:013:815:8

15:14

15:8 13:0 11:0 9:0

0123456789101112131415

15:0 14:013:012:0 11:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

CMOS VLSI Design11: Adders Slide 43

Taxonomy Revisited

f (Fanout)

t (Wire Tracks)

l (Logic Levels)

0 (2)1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

Kogge-Stone

Sklansky

Brent-Kung

Han-Carlson

Knowles[2,1,1,1]

Knowles[4,2,1,1]

Ladner-Fischer

Han-Carlson

Ladner-Fischer

New(1,1,1)

(c) Kogge-Stone

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(e) Knowles [2,1,1,1]

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(b) Sklansky

1:0

2:03:0

3:25:47:69:811:1013:1215:14

6:47:410:811:814:1215:12

12:813:814:815:8

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

1:03:25:47:69:811:1013:12

3:07:411:815:12

5:07:013:815:8

15:14

15:8 13:0 11:0 9:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(f) Ladner-Fischer

(a) Brent-Kung

1:03:25:47:69:811:1013:1215:14

3:07:411:815:12

7:015:8

11:0

5:09:013:0

0123456789101112131415

15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

1:03:25:47:69:811:1013:1215:14

3:05:27:49:611:813:1015:12

5:07:09:211:413:615:8

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(d) Han-Carlson

CMOS VLSI Design11: Adders Slide 44

Summary

Architecture Classification Logic Levels

Max Fanout

Tracks Cells

Carry-Ripple N-1 1 1 N

Carry-Skip n=4 N/4 + 5 2 1 1.25N

Carry-Inc. n=4 N/4 + 2 4 1 2N

Brent-Kung (L-1, 0, 0) 2log2N – 1 2 1 2N

Sklansky (0, L-1, 0) log2N N/2 + 1 1 0.5 Nlog2N

Kogge-Stone (0, 0, L-1) log2N 2 N/2 Nlog2N

Adder architectures offer area / power / delay tradeoffs.

Choose the best one for your application.