Logic Synthesis For Low Power CMOS Digital Design

Outlines

• Power consumption model

• Dynamic power minimization

– Reduction of output gate transitions

i. Logic synthesis for low power

ii. State assignment for low power

– Turning-off portions of a circuit

• Leakage power minimization

Power Dissipation

• Static dissipation due to leakage circuit

• Short-circuit dissipation

• Charge and discharge of a load capacitor

Vin Vout

VDD

GND

o

Power Dissipation Model

P: the power dissipation for a gate,

C: the load capacitance,

Vdd: the supply voltage,

Tcyc: the clock period,

E: the transition count of the gate per clock cycle.

P C V T Edd cyc 1

22( )

How to Compute Transition Density?

signal probability P1(g):

the probability of a logic 1 at the output of gate g

signal probability P0(g):

the probability of a logic 0 at the output of gate g, 1-P1(g)

signal transition probability(density) Pt

0 1 or 1 0

1

2

3

45

i1i2

i3i4

Simulation-based Computation

LogicSimulator

Logic waveformof each node

• Input-pattern dependent

• Two many input patterns

Probability-based Computation

A simple method :

gi1P0(g) =P1(g) =

P1(i1)P0(i1)

P1(g) = P1(i1) *P1(i2)

P0(g) = 1-P1(g)

P0(g) = P0(i1) *P0(i2)

P1(g) = 1-P0(g)

g

gi1i2

i1i2

Probability-based Computation

A simple method :

1

2

3

45

i1i2

i3i4

Timeti ti+1

P0(e)P1(e)

P1(e)P0(e)

..........

• (1-P1(g))*P1(g) P1(g)*(1-P1(g))

=> 2*P1(g)*(1-P1(g))

• Inaccuracy of the simple model

– Temporal relations

– Spatial relations

Technology Mapping For Low Power

(a) Circuit to be mapped

Gate Type Area Intrinsic Input Load Cap. Cap. INV 928 0.1029 0.0514 NAND2 1392 0.1421 0.0747 NAND3 1856 0.1768 0.0868 AOI33 3248 0.3526 0.1063

(b) Characteristics of the Library

Pt=

0.179

Pt=

0.179

Pt=

0.179

G1

G2G3

abcdef

Pt=0.109

Pt=0.109

out

Technology Mapping For Low Power

G1

G2G3

abcdef

out

AOI33

INV

Area Cost: 4176Power Cost: 0.0907

(c) Minimum-Area Mapping

out

G1

G2G3

abcdef

NAND3NAND2 WIRE

NAND3Area Cost: 5104Power Cost: 0.0803

(d) Minimum-Power Mapping

State Assignment

S2

S1

S3

01-0

00

10-1

0-1-01

-011

11

Combinational Logic

PI PO

PS NS

u1

u2

v1

v2

S4

State Assignment for Low Power Design

• Uneven distribution of state transitions in Finite State Machine

• State assignment such that states with high transitions are given state codes of short distance

• Minimize

– w(s,t): transition between s and t (power cost)

w s t dist enc s enc tall pairs

( , ) ( ( ), ( )) s,t

area cost + (1- ) power cost

State Probability Model

Sk Si

Ik,i

Prob(Si) = Pr ( ) Pr ( ),,( )

ob S ob Ik k iSk PS Si

where PS(Si) : the set of immediately previous

states of Si,

Prob(Ik,i): the probability of input pattern

Ik,i

State Probability Model (cont.)

• The summation of all states probability is equal to 1, therefore

• The state probabilities of Si’s can be

obtained by solving the linear system using the Cholesky Decomposition method.

Pr ( ) Pr ( ) .... Pr ( ) ,

Pr ( ) Pr ( ) Pr ( ),,( )

ob S ob S ob S

ob S ob S ob Im

i k k iPS Si

1 2 1

i = 1 to m.

Sk

Partitioning of a Controller

START s4

s6

s5

s2 s7

s3

M1

M2

4

21

2

21

4

21

1

21

2

21

9

42

7

42

1/00

0/00

0/01

0/00

1/10

0/10

1/101/01

0/00

1/10

0/00

00/0

1/00

1/00

• Turning Off Portions of a Circuit

Four Questions:

1. How do we determine the submachine to be turned on in each clock cycle?

2. When an inactive submachine becomes active, how do we set it to the correct state for the next clock cycle?

3. How does an active submachine relinquish control and pass it to the submachine

which will become active in the next clock cycle?

4. Physically, how do we turn off a piece of combinational logic?

Question 1

How do we determine which submachine to be turned on?

current state + input next state

the submachine to be turned on

To simplify the control logic:

state code:

– States in the same submachine will have the same control bits.

– The remaining bits will be used to distinguish among states in the same submachine.

need control logic tomake this decision

control bits

State Code of the Sub-machines

START S4

s6

s5

s2 s7

s3

M1

M2

4

21

2

21

4

21

1

21

2

21

9

42

7

42

1/00

0/00

0/01

0/00

1/10

0/10

1/101/01

0/00

1/10

0/00

00/0

1/00

1/00

Question 2

When an inactive submachine becomes active, how do we set it to the correct state?

Include the crossing transition in the state transition table of the submachine

An Example

s0

s1

s2

s3

s4

s5

1

1

0

110

M1 M2

input present state next state output

M1

0 1 0 1 0 1

s0s0s1s1s2s2

s1s3s2s3s1s5

101011

input present state next state output

M2

0 1 0 1 0 1

s3s3s4s4s5s5

s0s1s1s5s4s3

101000

Question 3

How does an active submachine relinquish control to allow another submachine to become active? The above state assignment will allow

control to be transferred from one machine to another with no additional circuitry

Question 4

How we actually turn on and off a piece of combinational logic?

mux_12 1mux

mux_22 1mux

mux_32 1mux

mux_42 1mux

mux_52 1mux

O1 O2

Com_1(M 1) Com_2(M 2)

1 2decoder

e1

e2

A B C D E F G H

X1 X1

control_1

FF1 FF2 FF3

Two Subproblems to Solve

1. Partitioning a Finite State Machine into submachines

2. State assignment for submachines

Leakage Power Optimization

– Gate threshold voltage assignment

• high threshold voltage:

– leakage power↓

– delay↑

• low threshold voltage:

– leakage power ↑

– delay↓

How to Reduce Leakage Power Without Performance Loss

1. use low threshold voltage gates for timing optimization

2. compute the slack time of each node

3. find all non-critical nodes and compute cost for each non-critical node

4 find candidate nodes for replacement

5 replace candidate nodes by high threshold voltage gates to save leakage power

6 re-compute the slack time of each node

7 if timing requirement is not violated, go to step 3.

An Example to Reduce Leakage Power Without Performance Loss

• Initial solution are all low threshold voltage gates for timing optimization • Critical path = wuzx

(x,y, z) means (slack, timing cost, power reduction)

x

y z

u

wv

a

b c d e

f

y

(0, 0.5, 1)

(0, 0.2, 0.5)(0.5, 0.25, 0.5)

(0, 0.5, 0.25)(0.5, 0.25, 1)

(0, 0.5, 0.5)

x Low threshold voltage gate

x High threshold voltage gate

An Example to Reduce Leakage Power Without Performance Loss

• High threshold gate = {v, y}• Low threshold gate = {w, u, z, x}• Power reduction = 1.5• No performance degradation

x

y z

u

wv

a

b c d e

f

y

(0, 0.5, 1)

(0, 0.2, 0.5)(0.25, 0, 0)

(0, 0.5, 0.25)(0.25, 0, 0)

(0, 0.5, 0.5)

(x,y, z) means (slack, timing cost, power reduction)

x Low threshold voltage gate

x High threshold voltage gate