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Combinational Logic Gates in CMOS References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall © UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian, Addison Wesley Adapted from: EE216A Lecture Notes by Prof. K. Bult © UCLA

Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

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Page 1: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Combinational Logic Gates in CMOS

References:

Adapted from: Digital Integrated Circuits: A Design

Perspective, J. Rabaey, Prentice Hall © UCB

Principles of CMOS VLSI Design: A Systems Perspective,

N. H. E. Weste, K. Eshraghian, Addison Wesley

Adapted from: EE216A Lecture Notes by Prof. K. Bult ©

UCLA

Page 2: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Design Techniques for Large Fan-In

• Transistor Sizing

• Progressive Transistor Sizing

• Transistor Ordering

• Logic Design to reduce the gate fan-in

Page 3: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Progressive Sizing

• When parasitic capacitance

is significant (e.g., when fan-

in is large), needs to

consider distributed RC

effect

• Increasing the size of M1 has

the largest impact in terms of

delay reduction

• M1 > M2 > M3 > … > MN

ln3

lnN

Out

ln1

ln2

M1

M2

M3

MN

Page 4: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Delay Optimization by Transistor Ordering

ln3

lnN

Out

ln1

ln2

M1

M2

M3

MN

Critical signal next to supply

Critical path

ln3

ln1

Out

lnN

ln2

MN

M2

M3

M1

Critical signal next to output

Critical path

Page 5: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Improved Logic Design

Reduce the fan-in to each gate

Page 6: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Example: F = ((A + B + C).D)

A

B

C

D

A B C

D

output

which path is the slowest ?

Page 7: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Example: F = ((A+B +C).D )

A

B

C

D

A B C

D

Slowest path

Alternatives ?

If minimum-size: tdr 6 tdf,inv

tdf,inv = delay of a minimum inverter

Page 8: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Example: F = ((A+B+C).D)

A

B

C

D

If minimum-size: tdr 7 tdf.inv

this approach is advantageous if driving larger load

Page 9: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Design of an 8-Input AND

Approach 1

Approach 2

Approach 3

Page 10: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

3-input NAND Gate with Parasitic Capacitors

inc

out

inb

ina

Cp+load

Ca

Cb

Cc

P1 P2 P3

N3

N2

N1

Page 11: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Macro Modeling for Worst Case Analysis

tdf = [RN1Ca] + [(RN1+RN2)Cb] + [(RN1 + RN2 + RN3)Cc] +

[(RN1 + RN2 + RN3)Cp + [(RN1 + RN2 + RN3)Cload]

Internal delay External load

td = Td, internal + x Cload

Page 12: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Macro Modeling

)(2

2

Lj

N

jNdfCmpC

n

mRCR

mmt

m: fan-in

n: sizing factor of NMOS transistors

p: sizing factor of PMOS transistors

Cinv,min = total gate capacitance of minimum size inverter

k = “fan-out” corresponding to CL

Cj = r Cinv,min

n

mkC

n

pCmCmmRt

invjj

Ndf

min,

22

2

)(

Keep m2 and m2p/n and mk/n reasonable

Page 13: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Macro Modeling for NOR Gate

p

mkC

p

nCmCmmRt

invjj

PNORdr

min,

22

,2

)(

Keep m2 and m2n/p and mk/p reasonable

n

kC

n

mpCmCRt

invj

jNNORdf

min,

,

Keep n as small as possible to minimize the impact on rise-delay

Page 14: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Design Strategy

• Use minimum sized transistors

• Analyze critical path (slowest, maybe more than 1)

• Look at alternative implementations (substitute

NOR’s ?)

• Compare and choose best

• Analyze critical path(s) and optimize transistor

sizing

Page 15: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Complementary Logic

• 2n transistors

• Complicated wiring

• No functional sizing required

Page 16: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Ratioed Logic

Page 17: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Ratioed Logic

Reduce the number of devices over complementary logic

Page 18: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Ratioed Logic

• Use PDN to implement the function (which is the

negation of the network)

• Total number of devices: n for the input, 1 for the

static load

• Minimum load is 1 unit-gate load

• Functional sizing is required to optimize noise margin

Page 19: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Functional Sizing in Ratioed Logic

• N transistors

• VOH = VDD

• Asymmetrical response

• Static power consumption

• tpLH = 0.69 RLCL

• tpHL = 0.69 (RL || RPDN) CL

DD

LPDN

PDN

OLV

RR

RV

Page 20: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Current Source as the Static Load

• If current source equals VDD/RL

= initial charging current from

the resistive load

• More than 25% reduction

compared to resistive load

ave

swingL

pLHI

VCt

2/

PDN

F

In1

In2

In3 2

LL

pLH

RCt

Page 21: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Load Lines of Ratioed Gates

0.0 1.0 2.0 3.0 4.0 5.0

V ou t (V )

0

0.25

0.5

0.75

1

I L(N

orm

aliz

ed

)

R esistive load

Pseudo-N M O S

D epletion load

C urrent source

Page 22: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

NMOS Depletion Load

Use depletion mode NMOS transistor as pull-up

Vtdep of depletion transistor is < 0 V

The depletion mode transistor is always ON:

gate and source connected Vgs = 0

Vin = 0 transistor pull down is off Vout is high

Page 23: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Voltage Output Low

Driver is in linear region with input high

Load is in saturation region

2

2

)(22

)(tdep

loadOL

OLtnDDdriverV

VVVV

Assume: VDD = 5.0V

Vtn = 1.0V = - Vtdep

Proper design: Vol < Vtn

Let: Vol = 0.5V

267.0

load

driver

Page 24: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Gate Threshold Voltage

Assume that both driver and load are in saturation with input Vinv

22

2

)(

)(2

)(2

)(2

dep

load

tinv

driver

tgs

driver

satDS

VVV

VVI

Hence,

driver

load

deptinvVVV

Gate threshold voltage = Vinv

= Input voltage at which Vin = Vout

If driver is increased relative to load then, Vinv decreases

Page 25: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

PMOST Load with Constant VGS

Voh = 5.0V

Vol = ???

I = 0.5 p.(Vdd-Vtp)2

I = n Vdd-Vtn)Vol-0.5Vol2

)5.0)((

)(5.0

2

2

ololtndd

tpdd

p

n

VVVV

VV

Page 26: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Sizing for VOL

)5.0)((

)(5.0

2

2

ololtndd

tpdd

p

n

VVVV

VV

Assume: Vdd = 5.0V

Vtn = Vtp = 1.0V

Proper design: Vol < Vth

Let: Vol = 0.5V

26.4

p

n

Page 27: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Sizing for Gate Threshold Voltage

N-device: saturated

2)(

2tnin

n

dsnVVI

)(tninout

VVV

P-device: non-saturated

]2

)())([(

2

DDout

DDouttpDDpdsp

DDgsp

VVVVVVI

VV

Equating the two currents we obtain,

]2

)())([()(

2

2

2 DDout

DDouttpDDptnin

nVV

VVVVVV

Page 28: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Sizing for Gate Threshold Voltage

Solving for Vout

CVVVVtpDDtpout

2)(

Where C = k (Vin - Vtn)2

p

nk

Also,2

22

)(

)()(

tnin

tpouttpDD

p

n

VV

VVVV

To make gate threshold voltage = 0.5VDD

11.6

p

n

Page 29: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Forcing the Voltage Output Low

Page 30: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Propagation Delay of Pseudo-NMOS Inverter

• Use average current

)8

()2

)(()(22

1)(

2

2 DDDD

tpDDPtpDD

P

av

VVVVVVHLI

8)(

2)()()(

22

1)(

2

2 DD

PN

DD

tnDDPtnDDNtnDD

N

av

VVVVVVVVLHI

• Propagation delay

av

DDL

pI

VCt

)2/(

Page 31: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Power Consumption

• Consume power when the output is low

2

,)(

2tpDD

P

lowavVVI

2

,,)(

2tpDDDD

P

lowavDDlowavVVVIVP

Page 32: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Trade-offs to be Considered

• To reduce static power, ILoad should be low

• To obtain a reasonable NML, VOL = ILoadRPDN should

be low

• To reduce tpLH CLVDD/(2ILoad), ILoad should be high

• To reduce tpHL 0.69 RPDNCL, RPDN should be kept

small

Page 33: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Pseudo-NMOS NOR Gate

• Fan-in of N inputs requires only N+1 transistors,

smaller parasitic capacitance and area

• Smaller load to preceding gate

• Static power consumption at output low

• Pseudo-NMOS gates can be used effectively when

speed is importance and majority of the output is high

A B C D

Page 34: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Pseudo-NMOS NAND Gate

VDD

GND

Page 35: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Improved Loads (2)

V DD

V SS

PD N 1

O ut

VDD

V SS

PD N 2

O ut

A

A

B

B

M1 M 2

D ual C ascod e V oltage Sw itch L ogic (D C V S L )

Page 36: Combinational Logic Gates in CMOS - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Logic... · Combinational Logic Gates in CMOS References: ... • Transistor Sizing ... • Minimum

Example

B

A A

B B B

O ut

O ut

X O R -N X O R gate