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Logic Gate Delay Modeling -1
Bishnu Prasad Das
Research Scholar
CEDT, IISc, Bangalore
OUTLINE
• Motivation
• Delay Model History
• Delay Definition
• Types of Models
-RC delay Models
-Logical Effort
• Limitation of Logical Effort
• Summary
Motivation
• Why Model is required?– For fast simulation– Solving differential equation is difficult– For creating optimal design– Real design will be always more costly and
time consuming.So model is used to simulate the system before actual implementation.
Types of Models
• Physical Models– Based on Physical phenomena of device
• Empirical Models– Based on curve fitting ( i.e. Quadratic,Cubic etc.)– No physical significance.
• Table Models– Storing the data in a Lookup Table– Do interpolation between stored data
Delay Model History
Courtesy : Synopsys
Delay Definitions
• tpdr: rising propagation delay– From input to rising output crossing VDD/2
• tpdf: falling propagation delay– From input to falling output crossing VDD/2
• tpd: average propagation delay– tpd = (tpdr + tpdf)/2
• tr: rise slew– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall slew– From output crossing 0.8 VDD to 0.2 VDD
• tcdr: rising contamination delay
– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
Delay Definitions
• tpdr: rising propagation delay– From input to rising output crossing VDD/2
• tpdf: falling propagation delay– From input to falling output crossing VDD/2
• tpd: average propagation delay– tpd = (tpdr + tpdf)/2
• tr: rise time– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall time– From output crossing 0.8 VDD to 0.2 VDD
Delay Definitions
• tcdr: rising contamination delay
– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
Delay Definitions
RC Delay Models
• Use equivalent circuits for MOS transistors– Ideal switch + capacitance and ON resistance– Unit nMOS has resistance R, capacitance C– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width• Resistance inversely proportional to width
kg
s
d
g
s
d
kCkC
kCR/k
kg
s
d
g
s
d
kC
kC
kC
2R/k
Example: 3-input NAND
• Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
• Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
Example: 3-input NAND
3
3
222
3
Example: 3-input NAND
• Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
3-input NAND Caps
• Annotate the 3-input NAND gate with gate and diffusion capacitance.
2 2 2
3
3
3
3-input NAND Caps
2 2 2
3
3
33C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
• Annotate the 3-input NAND gate with gate and diffusion capacitance.
9C
3C
3C3
3
3
222
5C
5C
5C
3-input NAND Caps
• Annotate the 3-input NAND gate with gate and diffusion capacitance.
Elmore Delay
• ON transistors look like resistors• Pullup or pulldown network modeled as RC ladder• Elmore delay of RC ladder
R1 R2 R3 RN
C1 C2 C3 CN
nodes
1 1 1 2 2 1 2... ...
pd i to source ii
N N
t R C
R C R R C R R R C
Example: 2-input NAND
• Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.
h copies
6C
2C2
2
22
4hC
B
Ax
Y
h copies
6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CY
pdrt
Example: 2-input NAND
• Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.
Example: 2-input NAND
• Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
6 4pdrt h RC
6C
2C2
2
22
4hC
B
Ax
Y
h copies
R
(6+4h)CY
Example: 2-input NAND
• Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies
6C
2C2
2
22
4hC
B
Ax
Y
Example: 2-input NAND
• Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
pdft (6+4h)C2CR/2
R/2x Y
h copies
6C
2C2
2
22
4hC
B
Ax
Y
Example: 2-input NAND
• Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
2 2 22 6 4
7 4
R R Rpdft C h C
h RC
(6+4h)C2CR/2
R/2x Y
Delay Components
• Delay has two parts– Parasitic delay
• 6 or 7 RC
• Independent of load
– Effort delay• 4h RC
• Proportional to load capacitance
Contamination Delay• Best-case (contamination) delay can be substantially
less than propagation delay.• Ex: If both inputs fall simultaneously
6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CYR 3 2cdrt h RC
Layout Comparison
• Which layout is better?
AVDD
GND
B
Y
AVDD
GND
B
Y
Delay in a Logic Gate
• Express delays in process-independent unit
• Delay has two components
• f is due to external loading
• p is due to self loading
absdd
d f p
τ = 3RC = FO1 delay without parasitic delay
Delay in a Logic Gate
• Express delays in process-independent unit
• Delay has two components
• Effort delay f = gh (a.k.a. stage effort)– Again has two components
absdd
d f p
τ = 3RC = FO1 delay without parasitic delay
Delay in a Logic Gate
• Express delays in process-independent unit
• Delay has two components
• Effort delay f = gh (a.k.a. stage effort)– Again has two components
• g: logical effort– Measures relative ability of gate to deliver current– g 1 for inverter
absdd
d f p
τ = 3RC = FO1 delay without parasitic delay
Delay in a Logic Gate
• Express delays in process-independent unit
• Delay has two components
• Effort delay f = gh (a.k.a. stage effort)– Again has two components
• h: electrical effort = Cout / Cin
– Ratio of output to input capacitance– Sometimes called fanout
absdd
d f p
τ = 3RC = FO1 delay without parasitic delay
Delay in a Logic Gate
• Express delays in process-independent unit
• Delay has two components
• Parasitic delay p– Represents delay of gate driving no load– Set by internal parasitic capacitance
absdd
d f p
τ = 3RC = FO1 delay without parasitic delay
Effort Delay • Logical Effort g = Cingate/Cin_unit_inv
• Electrical Effort h = Cout / Cingate
• f = g*h = (Cingate/Cin_unit_inv)*(Cout / Cingate)
= (Cout / Cin_unit_inv)
• (Dactual)ext = g*h * τ = (Cout / Cin_unit_inv)*3*R*C
= (Cout / Cin_unit_inv)*R*Cin_unit_inv
= Cout*R
Computing Logical Effort
• DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.
• Measure from delay vs. fanout plots• Or estimate by counting transistor widths
A YA
B
YA
BY
1
2
1 1
2 2
2
2
4
4
Cin = 3g = 3/3
Cin = 4g = 4/3
Cin = 5g = 5/3
Catalog of Gates
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
• Logical effort of common gates
Catalog of Gates
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
• Parasitic delay of common gates– In multiples of pinv (1)
Delay Plots
d = f + p = gh + p
Electrical Effort:h = C
out / C
in
Nor
mal
ized
Del
ay: d
Inverter2-inputNAND
g =p =d =
g =p =d =
0 1 2 3 4 5
0
1
2
3
4
5
6
Delay Plots
d = f + p = gh + p
• What about
NOR2?
Electrical Effort:h = C
out / C
in
Nor
mal
ized
Del
ay: d
Inverter2-inputNAND
g = 1p = 1d = h + 1
g = 4/3p = 2d = (4/3)h + 2
Effort Delay: f
Parasitic Delay: p
0 1 2 3 4 5
0
1
2
3
4
5
6
Example: Ring Oscillator• Estimate the frequency of an N-stage ring oscillator
Logical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay:d =
Frequency: fosc =
Example: Ring Oscillator
• Estimate the frequency of an N-stage ring oscillator
Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay:d = 2
Frequency: fosc = 1/(2*N*d) = 1/4N
Example: FO4 Inverter• Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay:d =
d
Example: FO4 Inverter• Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g = 1
Electrical Effort: h = 4
Parasitic Delay: p = 1
Stage Delay:d = 5
d
The FO4 delay is about
200 ps in 0.6 m process
60 ps in a 180 nm process
f/3 ns in an f m process
Multistage Logic Networks
10x y z
20g1 = 1h
1 = x/10
g2 = 5/3h
2 = y/x
g3 = 4/3h
3 = z/y
g4 = 1h
4 = 20/z
Limits of Logical Effort
• Chicken and egg problem– Need path to compute G– But don’t know number of stages without G
• Simplistic delay model– Neglects input rise time effects
• Interconnect– Iteration required in designs with wire
• Maximum speed only– Not minimum area/power for constrained delay
Summary
RC Delay Model
Delay measurement using Logical Effort Method
Gate sizing using Logical Effort for minimum delay
Limitations of Logical Effort
Reference
• N. H. E. Weste and D. Harris, “CMOS VLSI Design, A circuits and Systems Perspective” 3rd edition Pearson Addison Wesley
• Rabaey, Chandrakasan and Nikolic, “Digital Integrated Circuits, a Design Perspective”, Pearson Education
