Logic design of asynchronous circuits

1

Logic design ofasynchronous circuits

Part III:

Advanced topics on synthesis

ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits 2

Outline

• Logic decomposition– Hazard-free decomposition

– Signal insertion

– Technology mapping

• Optimization based on timing information– Relative timing

– Timing assumptions and constraints

• Other synthesis paradigms– HDLs, CSP, burst-mode, ...


Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flow


No Hazards

abc

x 0

abcx1000

1100

b+

0100

a-

0110

c+

1

1

0

0

1

1

0

1

0

1

0

0


Decomposition May Lead to Hazards

abcx1000

1100

b+

0100

a-

0110

c+

a

bz

cx

1

0

0

0

0

1000

11001100

0100

0110

1

1

0

0

0

1

1

1

0

0

0

1

1

0

0

0

1

1

1

1

0

1

0

1

0


Decomposition

• Acknowledgement

• Global acknowledgement

• Generating candidates

• Hazard-free signal insertion

– Event insertion

– Signal insertion


Global acknowledgement

abc

z

abd

y

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-


abc

z

abd

y

How about 2-input gates ?

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-


a

bc

z

abd

y

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-



a

bc

z

abd

y

00

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-



abc

z

a

bd

y

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-



cz

dy

a

b

d- b+ d+ y+ a- y- c+ d-

c- d+ z- b- z+ c+ a+ c-



Strategy for logic decomposition

• Each decomposition defines a new internal signal

• Method: Insert new internal signals such that– After resynthesis, some large gates are decomposed– The new specification is hazard-free

• Generate candidates for decomposition using standard logic factorization techniques:

– Algebraic factorization– Boolean factorization (boolean relations)


y-

z- w-

y+ x+

z+

x-

w+

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

Decomposition example


yz=1yz=0

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

C

C

x

y

x

y

w

z

xyz

y

zw

z

w

z

y



s-

s+

s-

s-

s=1

s=0

1001 1011

1000

1010

0111

0011y+

x-

w+

z+

z-

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

C

C

x

y

x

y

w

z

x

y

z

w

z

w

z

y

sy-



y-

z- w-

y+ x+

z+

x-

w+

s-

s+

s-

s+

s-

s-

s=1

s=0

1001 1011

1000

1010

0111

0011y+

x-

w+

z+

z-

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

y-



C

C

x

y

x

y

w

z

xyz

y

zw

z

w

z

y

yz=1yz=0

1001 1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

1011

1000

1010

0001

0000 0101

0010 0100

0110 0111

0011

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

1001



s-

s+

s=1

s=0

1001 1011

0111

0011

x-

w+

z+

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

y-y-

z- w-

y+ x+

z+

x-

w+

s-

s+

z- is delayed by the new transition s- !



C

C

x

y

x

y

w

z

x

y

z

w

z

w

z

yyyyyyy

s-

s+

s=1

s=0

1001 1011

0111

0011

x-

w+

z+

0001

0000 0101

0010 0100

0110

x+

w-

w-

w-

z-

z-y+

y+

x+

x+

1001

1000

1010

y+

z-

0111

y-


FC

Sr

D

Decomposition(Algebraic, Boolean relations)

Hazard-free ?(Event insertion)

NO YES

C

C

C

C

SrSr

D

D

FC

Sr

D

Hazard-free ?(Event insertion)

NO YES

CC

Sr

D

until no more progress

Decomposition(Algebraic, Boolean relations)


Signal insertion for function F

State Graph

F=0 F=1

Insertion by input borders

F-

F+


Event insertion

a b

ER(x)

c


Event insertion

a b

ER(x)

cx x x x

b

SR(x)

a


Properties to preserve

a

a

b

b

a

a

b

b

a

a

b

b

xx

a

a

b

b

a

a

b

b

ba

a

b

b

xx

xx

a ispersistent

a is disabled by b

= hazards


Boolean decomposition

Fx1

xn

f H Gx1

xn

h1

hm

f

f = F (x1,…,xn) f = G(H(x1,…,xn))

Our problem: Given F and G, find H

Ch1

h2

f

state f next(f) (h1,h2)

s1 0 0 (0,-) (-,0) s2 0 1 (1,1) s3 1 0 (0,0) s4 1 1 (-,1) (1,-) dc - - (-,-)This is a Boolean Relation

y-

a+ c-

d-

a-

c+

a+

y+

a-c-

d+

c+

y

acd Facd y c d ( )

Rsy

R

S

y-

a+ c-

d-

a-

c+

a+

y+

a-c-

d+

c+

y

acd acd y c d ( )

Rsy

acdc

d

y-

a+ c-

d-

a-

c+

a+

y+

a-c-

d+

c+

y

acd acd y c d ( )

Rsy

cd yc

a

y-

a+ c-

d-

a-

c+

a+

y+

a-c-

d+

c+

y

acd acd y c d ( )

Rsya

Ddc


Technology mapping

• Merging small gates into larger gates introduces no new hazards

• Standard synchronous technique can be applied, e.g. BDD-based boolean matching

• Handles sequential gates and combinational feedbacks

• Due to hazards there is no guarantee to find correct mapping (some gates cannot be decomposed)

• Timing-aware decomposition can be applied in these rare cases


Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


Timing assumptions in design flow

• Speed-independent: wire delays after a forksmaller than fan-out gate delays

• Burst-mode: circuit stabilizes betweentwo changes at the inputs

• Timed circuits: Absolute bounds on gate / environment delays are known a priori (before physical design)


Relative Timing Circuits

• Assumptions: “a before b” – for concurrent events: reduces reachable state space

– for ordered events: permits early enabling

– both increase don’t care space for logic synthesis => simplify logic (better area and timing)

• “Assume - if useful - guarantee” approach: assumptions are used by the tool to derive a circuit and required timing constraints that must be met in physical design flow

• Applied to design of the Rotating Asynchronous Pentium Processor(TM) Instruction Decoder (K.Stevens, S.Rotem et al. Intel Corporation)


Speed-independent C-element

Relative Timing Asynchronous Circuits

a- before b-Timing assumption (on environment):

ab c

RT C-element: faster,smaller; correct only under timing constraint: a- before b-

ab c


State Graph (Read cycle)

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+


Lazy Transition Systems

ER (LDS+)ER (LDS+)

ER (LDS-)ER (LDS-)

LDS-LDS-

LDS+

LDS-DTACK- FR (LDS-)FR (LDS-)

Event LDS- is lazy: firing = subset of enabling


Timing assumptions

• (a before b) for concurrent events: concurrency reduction for firing and enabling

• (a before b) for ordered events: early enabling

• (a simultaneous to b wrt c) for triples of events: combination of the above


Speed-independent Netlist

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr

LDS

LDTACK

csc

map


Adding timing assumptions (I)


DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr

LDS

LDTACK

csc

map

LDTACK- before DSr+

FAST

SLOW


Adding timing assumptions (I)

DTACKD

DSr

LDS

LDTACK

csc

map


DTACK-

LDS-LDTACK-

DSr+

LDTACK- before DSr+


State space domain

LDTACK- before DSr+

LDTACK-

DSr+


State space domain

LDTACK- before DSr+

LDTACK-

DSr+


State space domain

LDTACK- before DSr+

LDTACK-

DSr+

Two more unreachable states


Boolean domain

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 0 0 0 0/1?

1

111

-

-

-

---

- - - -

-

- ---

- - -


Boolean domain

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 - 0 0 1

1

111

-

-

-

---

- - - -

-

- ---

- - -

One more DC vector for all signals One state conflict is removed


Netlist with one constraint


DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr

LDS

LDTACK

csc

map


Netlist with one constraint


DTACK-

LDS-LDTACK-

DSr+

DTACK D

DSr LDS

LDTACK

LDTACK- before DSr+

TIMING CONSTRAINT


Timing assumptions

• (a before b) for concurrent events: concurrency reduction for firing and enabling

• (a before b) for ordered events: early enabling

• (a simultaneous to b wrt c) for triples of events: combination of the above


Ordered events: early enabling

a

c

b

a

a

c

b

a

bb

c cF G

Logic for gate c may change


Adding timing assumptions (II)


DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr LDS

LDTACK

D- before LDS-


State space domain

LDS-

D-

Reachable space is unchanged

For LDS- enabling can be changed in one state

D- before LDS-

Potential enabling for LDS-

DSr-


Boolean domain

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 - 0 0 1

1

111

-

-

-

---

- - - -

-

- ---

- - -


Boolean domain

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 - 0 0 1

1

11-

-

-

-

---

- - - -

-

- ---

- - -

One more DC vector for one signal: LDSIf used: LDS = DSr, otherwise: LDS = DSr + D


Before early enabling


DTACK-

LDS-LDTACK-

DSr+

DTACKD

DSr LDS

LDTACK


Netlist with two constraints


DTACK-

LDS-LDTACK-

DSr+

LDTACK- before DSr+and D- before LDS-

TIMING CONSTRAINTSDTACKD

DSr LDS

LDTACK

Both timing assumptions are used for optimization and become constraints


Value of Relative Timing

• RT circuits provides up to 2-3x (1.3-2x) delay&area reduction with respect to SI circuits synthesized without (with) concurrency reduction

• Automatic generation of timing assumptions => foundation for automatic synthesis of RT circuits with area/performance comparable/better than manual

• Back-annotation of timing constraints => minimal required timing information for the back-end tools

• Timing-aware state encoding allows significant area/performance optimization

Specification(STG + user assumptions)

Lazy State Graph

Lazy SG withCSC



Gate netlist


Timing-aware state encoding


Logic decomposition

Technology mapping

Design Flow with TimingDesign Flow with Timing

Required Timing Constraints

Automatic Timing Assumptions


FIFO example

FIFOli

lo

ro

ri

li-

li+

lo+

lo-

ro+

ro-

ri+

ri-


Speed-Independent Implementation

without concurrency reduction 3 state signals are required


SI implementation with concurrency reduction

li

lo ro

ri

xli-

li+

lo+

lo-

ro+

ro-

ri+

ri-

x+

x-

+gCgC +-


RT implementation

li

lo ro

ri

xli-

li+

lo+

lo-

ro+

ro-

ri+

ri-

x+

x-

OR

li-

li+

lo+

lo-

ro+

ro-

ri+

ri-

x+

x-


RT implementation

li

lo ro

ri

xli-

li+

lo+

lo-

ro+

ro-

ri+

ri-

x+

x-

OR

li-

li+

lo+

lo-

ro+

ro-

ri+

ri-

x+

x-

To satisfy the constraint: Delay(x- ) < Delay (ri+ ) andDelay(lo+) + Delay(x- ) < Delay(ro+ ) + Delay (ri+ ) All constraints are either satisfied by default oreasy to satisfy by sizing


Other synthesis paradigms: outline

• Synthesis from HDL (Verilog) [Lavagno et al, Async00]

– Subset for asynchronous specification

– Data-path/control partitioning

– Circuit architecture. Control generation

• Synthesis from asynchronous HDL (CSP, Tangram)

– CSP for control generation [A. Martin et al, Caltech]

– Tangram for silicon compilation [K. van Berkel et al, Philips]

• Control synthesis using FSMs [K. Yun, S. Nowick]

– Burst-mode machines

– Comparison with STGs


Motivation

• Language-based design key enabler to synchronous logic success

• Use HDL as single language for• specification• logic simulation and debugging• synthesis• post-layout simulation

• HDL must support multiple levels of abstraction


• Splitting of asynchronous control and synchronous data path

• Automated insertion of bundling delays

CONTROLUNIT

DATAPATH

delay

request

acknowledge

Control-data partitioning

Design flow

Control/datasplitting

STG(control)

HDLspecification

SynthesizableHDL (data)

Synthesis(petrify)

Timing analysis(Synopsys)

HDLimplementation

Synthesis(Synopsys)

Logicimplementation

Delayinsertion

Logic delays


Asynchronous Verilog subset by example

always begin

wait(start);R = SMP * 3;RES = SMP * 4 + R;if(RES[7] == 1) RES = 0;else begin if(RES[6] == 1) RES = 1;end;done = 1;wait(!start);done = 0;

end

RRES

SMP

donestart

RES

C.U.

• begin-end for sequencing, fork-join for concurrency, if-else for input choice• Only structured mix of sequencing, concurrency and choice can be specified


Synthesis from asynchronous HDL

• CSP based languages• CSP = communicating sequential processes

[Hoare]• Two synthesis techniques

– based on program transformations [Caltech]

– based on direct compilation [Philips]

• Tools are more mature than for asynchronous synthesis from standard HDL

• Complete shift in design methodology is required


Using CSP for control generation

• After li goes high do full handshake at the right, then complete handshake at the left and iterate.

li+ ro+ ri+ ro- ri- lo+ li- lo-

ro

ri

li

lo

Q element

*[[li];ro+;[ri];ro-;[not ri];lo+;[not li];lo-]

• “;” = sequencing operator• ro+ = ro goes high; ro- = ro goes low• [li] = wait until li is high; [not li] = wait until li is low

CSP:

STG:


Using CSP for control generation

*[[li];ro+;[ri];ro-;[not ri];lo+;[not li];lo-]

• Conflict: ro+ and ro- are not mutually exclusive (since ri+ and li+ are not)

• Eliminate conflict by state signal insertion (= CSC)

CSP:

Production rules:li -> ro+; ri -> ro-not ri -> lo+; not li -> lo-

ri

li

ro

weak


Conflict elimination

*[[li];ro+;[ri];x+;[x];ro-;[not ri];lo+;[not li];x-;[not x];lo-]CSP:

Production rules:not x and li -> ro+; x or not li -> ro-x and not ri -> lo+; not x or ri -> lo-ri -> x+; not li -> x-

FFx not x

li

lo ri

ro


Buffer example in Tangram(a?byte & b!byte)begin

x0: var byte | forever do

a?x0 ; b!x0od

end

Buffer

*

xa bT

;

T

a b

passive port

active port Each circle mapped to a netlist

Data path

Q element


Summary

• Tangram program is partitioned into data path and control

• Data path is implemented as dual or single rail

• Control is mapped to composition of standard elements (“;” “||” etc)

• Each standard element is mapped to a circuit

• Post-optimization is done

• Composing islands of control elements and re-synthesis with STG can give more aggressive optimization

• Philips made a few chips using Tangram, including a product: 8051 micro-controller in low-power pager Muna (25 wks battery life from one AAA battery)

• Similar approach used in Balsa (Manchester Univ.)


Burst mode FSM

s1

s2

s3

s4

b-/x-a+b+/y+

a-/x+y-

c+/y-c-/y+

• Close to synchronous FSMs with binary encoded I/O

• Work in bursts:– Input transitions fire

– Output transitions fire

– State signals change

• Mostly limited to fundamental mode: next input burst cannot arrive before stabilization at the outputs


Extended Burst mode

s1

s2

s3

s4

b-/x-

a+b*/y+<b+>a-/x+y-

<b+>c+/y-c-/y+

• Directed don’t cares (b*): some concurrency is allowed for input transitions that do not influence an output burst

• Conditional guards <b+> = “if b=1 then …”


Synthesis of XBM

• Next state and output functions free of functional and logic hazards

• Sequential feedbacks should not introduce new hazards• State assignment

– one state of the BM spec to one layer of Karnaugh map

– compatible layers are merged

– layers are compatible if merging does not introduce CSC violations or hazards

– Layers are encoded using race free encoding


XBM and STG

s1

s2

s3

s4

b-/x-

a+b*/y+<b+>a-/x+y-

<b+>c+/y-c-/y+

x-

a+

y+

b+

eps

c-

a- c+

y-

y+

x+ y-

b-

Documents

Logic design of asynchronous circuits