LNA Design Using UMS Foundry Desig Kit

LNA DesignUsing UMS Foundry Design Kit

Alain Michel, Ansoft FranceTony Donisi, Ansoft USA

Presentaton #10

Agendaw LNA Design

w Introductionw FET Characteristicsw Input Matchw Output Matchw Layout Considerationsw Final Results

w Design kit Descriptionw Building Design Kit in Ansoft Designer

w Layout stationary file (Layers definition)w Component creation

w Symbols, Layout, Electrical and Components creationw Conclusion

LNA Design

Using UMS PH25 Design KitThis circuit was designed by CNES

Using UMS PH25 Design KitThis circuit was designed by CNES

Introductionw It is difficult to obtain a good noise match

with a good input matchw Broad frequency rangew “optimal” noise match typically mismatches the

inputw Balancing the amplifier degrades noise figure

w Γopt is the “optimum noise matching point of an LNAw This match gives optimal noise figure, or nopt

w Design approach w Choose FET topology/Process Such that Γopt is

close to 50Ω

LNA DesignLNA Design

FET Characteristics

Process PH25 Low Noise PH15 Low Noise HP07 Power PPH25 Power PPH15 Power HB20P Power HB20L L-Band BES

Noise / Gain 0.6dB/13dB @10GHz 2dB/8dB @40GHz

0.5dB/14dB@10GHz 1.9dB/6dB@60GHz

Power 250mW/mm 300mW/mm 500mW/mm 700mW/mm 600mW/mm 3500mW/mm 2000mW/mm@3V

Gate length 0.25µm 0.15µm 0.7µm 0.25µm 0.15µm 2µm 3µm 1µm

Active layer MBE MBE Implanted MBE MBE Epitaxy Epitaxy MBE

IDS (gm max) IDS SAT/IC HBT 200mA/mm 500mA/mm 220mA/mm 550mA/mm 450mA/mm 200mA/mm

450mA/mm300mA/mm 600mA/mm 0.3mA/µm² 0.3mA/µm²

VBDS / VBCE >5V >4V >14V >12V >8V >16V >15V >-5V (Anode/Cathode)

Cut off freq. 90GHz 110GHz 15GHz 50GHz 75GHz 25GHz 25GHz 3THz

Data source UMS

w Two process dedicated to Low Noise applicationw The bias conditions are chosen following the

foundry recommendation: IDSS/xw The topology of the FET is chosen for Γopt close to

50Ohm


Input Match: FET Topology

w Start with linear S and noise parametersw Choose foundry’s recommended Low-Noise

topology

w Plot Γopt

w Add series feedbackw Slightly degrades noisew Allows “tuning” of Γopt


Γopt Versus FET Topology: Simulation


Γopt versus FET Topology: Results

Γopt at 40Ghz for 4x30um FETΓopt at 40Ghz for 4x30um FET


Noise Match:Adding Series Feedback


Gopt & Stabilization:Tuning Source Inductance


Noise Figure VariationWith Series Inductance

This 3D plot has a “minimum” along the inductance axis with respect to frequency. This indicates that there is an inductance that will minimize the 50Ω noise figure.

This 3D plot has a “minimum” along the inductance axis with respect to frequency. This indicates that there is an inductance that will minimize the 50Ω noise figure.


Input Match: Smith Tool


Input Match: Smith Tool


Output Match: Smith Tool


Input and output Matched


Insertion of CapacitanceTo Attenuate Low Frequency Gain


From Ideal to Real

w Step by step replacement of ideal elementsw Tuningw Optimizationw TRL

w Replace ideal capacitors, Inductors and viasw Use elements from design kit

w Optimize layoutw Absorb parasiticsw Build parameterized field solver sub-circuit

w Planar EM Co-simulation


Final Schematic


Electromagnetic Elements: Solver On Demand


Electromagnetic Elements: Solver On Demand


Final Layout


Final Results S21, NF & FMIN


Final Results S11 & S22


Final Results: K


Tolerance Analysis


Tolerance Analysis ResultsGain & Noise Figure


Tolerance Analysis ResultsReturn Loss & Stability


Design kit Description

Mandatory Foundry Data For Design Kit Creation:

w Electrical model documentationw Model topologiesw Equationsw Relationship with layout

w Layout design rulesw Layer definitionsw Layout cell geometriesw Design rules

Design Kit DescriptionDesign Kit Description

Model Topology (MIM Capacitor)Model Topology (MIM Capacitor)

2) main capacitance

The main capacitance is described by capacitance C in series with a resistance Rs:

SEL = L * WEL (surface of the top electrode)C(pF) = coef1 * SEL (mm2)Rs(W)= (coef2 + coef3 * Lai(mm)) / WN1(mm)

3/ air-bridge output

The output circuit is the equivalent circuit of air-bridge

- Lo (pH) = coef4 - coef5 * ln(WB(mm))- Ro (W) = coef6 * 1/WB(mm)- Co (fF) = coef7 + coef8 * WB(mm)

Equations

Electrical model

Relation with layout


Layout Cell GeometriesLayout Cell Geometries

Design RulesDesign Rules

Layer Definitions

Layer Definitions

Layout Design Rules


Building Design Kit in Ansoft Designer

Design Kit ImplementationDesign Kit Implementation

Technology File:Layer Definitions


Ansoft Designer provides an Editor that will help to create each part and link them together.

Ansoft Designer provides an Editor that will help to create each part and link them together.

Component Creation

w A component consists of :w Symbolw Layout cellw Electrical model


Symbol Creation


Layout Cell Creation


Layout Cell Creation: Drawing

Boolean Functions Add, Subtract, Union, etc.

Boolean Functions Add, Subtract, Union, etc.


Layout Cell Creation: Fixed or Scripted


Electrical Model Creation

Netlist FragmentsNetlist Fragments “C” Coded UDM’s“C” Coded UDM’s

Parameterized SubcircuitsParameterized Subcircuits

InterpretiveUDM’sInterpretiveUDM’s


Conclusion

w Ansoft Designer offers powerful facilities to build component and libraries

w Building Design Kit is fast and easyw LNA design using Designer features:

w Tuningw Parametric Analysisw Optimizationw Smith toolw Parameterized field solver sub-circuit

Documents

LNA Design Using UMS Foundry Desig Kit