Differntial LNA Design

7/23/2019 Differntial LNA Design

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Low Noise Amplifier (LNA) Design

Low Noise Amplifier (LNA) is the first block after the receiving antenna. The gain of the LNA

should be high not only to amplify the received signal by the antenna but also to decrease the

effect of noise in the subsequent stages of the receiver. On the other hand, the noise of the LNA

itself must be minimized as it directly adds to the overall Noise Figure (NF) of the receiver. A

differential LNA has two unique stages. It is advantageous over single stage LNA. Firstly, the

virtual ground formed at the ‘tail’ removes the sensitivity to parasitic ground inductances, which

makes the real part of the input impedance purely controlled by the source degeneration

inductance (Ls). Secondly the differential amplification of the signal ensures attenuation of the

common mode signal, in most systems this common mode signal will be noise. Thirdly, the use

of Gilbert mixers and image rejection schemes require to be fed from a differential source.

Architecture of the designed LNA circuit

Designed LNA is shunt degenerated. It is a wide band LNA. Due to this matching circuit output

gain is increased. Input matching is optimized by sweeping Lg. Output matching is optimized by

sweeping Cout. R d determines quality factor. So increasing the value of R d subsequently increases

the bandwidth and decreased gain. Ld can be tuned to optimize the gain. It is not possible to

simulate 4 ports network on Hspice. That’s why we have used a balun circuit at input to make

single ended input to differential input. Also a balun circuit at output is used to make differential

output to single ended.

Again for matching input impedance of 50 ohm the input impedance of LNA must be near 50

ohm. It can be measured from s11 and s22 parameter.

So sweeping Lg is more suitable than sweeping Ls as it determines the center frequency of

operation. The circuit diagram and BalUn circuit is given below:

gs

sm

gs

s g inC

L g

sC L L s Z

1)(



Figure 1: Circuit Diagram of differe=ntial LNA

Balun circuit is used at input and also at output to get differential from single ended and single

ended from differential.

Performance of the LNA

This section exhibit the simulated response of the LNA. Fig. 2 shows the gain of the differential

LNA. Center frequency of the design is at 4.5GHz. LNA is -12.7 dB. Bandwidth of the

differential LNA is 1.41GHz.



S11 and S22

Figure 2: S11 (dB) and s22 (dB) of the differential LNA. Peak is less than -10dB at 4.5GHz.

S12:

This have to beless than -20dB for bettr performance. My design met the specification.

Figure 3: S12 (dB) of the differential LNA.



S21

Center frequency of the design is at 4.5GHz. Peak gain of the differential LNA is 12.7 dB.

Bandwidth of the differential LNA is about 1.41GHz

Figure 4: S21 (dB) of the differential LNA. Peak is 12.7dB at 4.5GHz

Noise Factor & Noise min

Most important parameters of a LNA are the NF and NFmin. These should be as low as possible

is needed. At center frequency, NF is about 1.65 dB and NFmin is about 1.4dB.

Figure 6: Noise Factor of the differential LNA



Figure 7 : Noise min of the differential LNA

Required parameters of the LNA is shown on table

Parameters Value

Gain 12.7 dB

Center frequency 4.5GHz

Bandwidth 1.41 GHz

Power Consumption 10.4 mW

IIP3 -35

1 dB compression point -25 dBm

Noise Figure 1.65 dB



Differential LNA parameter(S11, S12, S21, S22, Noise Factor, Noise min) by using HSPICE

Code

*Design of Differential LNA #0413062226

.options post=2

.options tnom=25

.lib 'rf018.l' TT_RFMOS

* subckt for generating single ended input to differential & differential output to single ended output

.subckt balun 1 2 3 4

E1 5 2 1 0 0.5

V1 3 5

F1 1 0 V1 -0.5

R1 1 0 1T

E2 6 4 1 0 0.5

V2 2 7

F2 1 0 V2 -0.5

R2 7 6 1u

.ends balun

.param r1=50 lg=2.857n

*first end

cc1 nvin n1 1.4153p

rrin nvbias n1 1k

llg n1 n3 3.2n *2.857n

cc3 n3 ns1 0.15p

xmna nd1 n3 ns1 ns1 nmos_rf lr=.18u wr=4u

lls ns1 0 1n

lld nd2 nvdd1 5n

rrd nvdd1 nvdd 30

xmnd nd2 nvdd nd1 nd1 nmos_rf lr=.18u wr=1.8u

ccout nd2 nvout 150f



*second end

cc1s nvins n1s 1.4153p

rrins nvbiass n1s 1k

llgs n1s n3s 3.2n *2.857n

cc3s n3s ns1s 0.15p

xmnas nd1s n3s ns1s ns1s nmos_rf lr=.18u wr=4u

llss ns1s 0 1n

llds nd2s nvdd1s 5n

rrds nvdd1s nvdd 30

xmnds nd2s nvdd nd1s nd1s nmos_rf lr=.18u wr=1.8u

ccouts nd2s nvouts 150f

vdd nvdd 0 1.8

vbias nvbias 0 .55

vbiass nvbiass 0 .55

*vin nvin 0 dc 0 ac 1m

*rrc c 0 1000

rrcd cs 0 200

xdi d c nvin nvins balun

xdo ds cs nvout nvouts balun

.ac lin 1000 2.3g 6.7g *sweep r1 10 100 10

P1 nvin 0 port=1 z0=50 DC=0

P2 nvout 0 port=2 z0=75

.lin noisecalc=1 sparcalc=1

.print ac s11(db) s12(db) s21(db) s22(db)

.print ac nf(db) nfmin(db)

.end



IIP3 is measured by Hspice code.


.options post=2

.options tnom=25


* subckt for generating single ended input to differential & differential output to single ended

output


E1 5 2 1 0 0.5

V1 3 5

F1 1 0 V1 -0.5

R1 1 0 1T

E2 6 4 1 0 0.5

V2 2 7

F2 1 0 V2 -0.5

R2 7 6 1u

.ends balun

*.param r1=50 lg=2.857n

.param inputP=1u

*first end

cc1 nvin n1 1.4153p

rrin nvbias n1 1k

llg n1 n3 3.2n *2.857n

cc3 n3 ns1 0.15p


lls ns1 0 1n



lld nd2 nvdd1 5n

rrd nvdd1 nvdd 30



*second end




cc3s n3s ns1s 0.15p


llss ns1s 0 1n

llds nd2s nvdd1s 5n

rrds nvdd1s nvdd 30



vdd nvdd 0 1.8

vbias nvbias 0 .55



*rrc c 0 1000

rrcd cs 0 200



.ac lin 1000 2.3g 6.7g *sweep r1 10 100 10

P1 nvin 0 port=1 z0=50 DC=0 hb 'inputP' 0 1 1 hb 'inputP' 0 1 2

P2 nvout 0 port=2 z0=75

.lin noisecalc=1 sparcalc=1

*Measung IIP3

.hb tones=4.5G 4.51G nharms=6 6 sweep inputP 1u 10u 1u

.measure hb pin find pdbm(p1)[1,0] at=1u



.measure hb pout find pdbm(p2)[1,0] at=1u

.measure hb p3rd find pdbm(p2)[2,-1] at=1u

.measure hb IIP3=param('pin+(pout-p3rd)/2')

.measure hb OIP3=param('pout+(pout-p3rd)/2')

.print hb p(p1) pdbm(p1)

.print hb p(p2) pdbm(p2)

.end





Power Measurement by Hspice code.


.options post=2

.options tnom=25


.tran 0.0001n 10n

* subckt for generating single ended input to differential & differential output to single ended output


E1 5 2 1 0 0.5

V1 3 5

F1 1 0 V1 -0.5

R1 1 0 1T

E2 6 4 1 0 0.5

V2 2 7

F2 1 0 V2 -0.5

R2 7 6 1u

.ends balun

*.param r1=50 lg=2.857n

.param inputP=1u

*first endcc1 nvin n1 1.4153p

rrin nvbias n1 1k

llg n1 n3 3.2n *2.857n

cc3 n3 ns1 0.15p


lls ns1 0 1n

lld nd2 nvdd1 5n

rrd nvdd1 nvdd 30



*second end




cc3s n3s ns1s 0.15p




llss ns1s 0 1n

llds nd2s nvdd1s 5n

rrds nvdd1s nvdd 30



vdd nvdd 0 1.8

vbias nvbias 0 .55



vin nvin 0 ac 5m sin(0 5m 4.5g 0.0002n 0 0)

*rrc c 0 1000

rrcd cs 0 200



.print v(nvout)

.measure avg_pow AVG power from=.005n to=10n

.end

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Differntial LNA Design