Linear Dropout Regulator based Power Distribution Design under Worst Loading

Amirali Shayan, Xiang Hu

Chung-Kuan Cheng

University of California San Diego

Wenjian Yu

Tsinghua University

Christopher Pan

Huawei

Page 2

Introduction and Motivation

LDO based PDN Design under Worst Loading

Worst case current synthesis

Poles/Zeros based Methodology

Experimental Results and Trade offs Conclusion Remarks

Agenda

Page 3

Introduction

LDO design will enable:– Localized on die regulation

– Relax off chip impedance

– Power saving

– Finer grain power management

LDO design challenges– Power consumption

– Area of the power MOSFET

– Stability of the feedback loop

– Physical design

Page 4

LDO based PDN Optimization under Worst Loading

Die

VRM

Bulkcaps MB

caps

Motherboard

Package

Integrated On-die LDO Shortens the PDN loop

Adv #1: Better dynamic power management through reduced response timeAdv #2: Maintain low package cost while provide adequate power delivery

|z|

Freq

Virtually eliminate 1st and 2nd droops

LDO

RPCB RDIERPKG TRVR

Power saving opportunity

RDIE TRLDORPCB RPKG

4

OriginalOptimize PackageWith LDO

Page 5

LDO-PDN Model of Design (1)

Operation region of the power MOSFET depends on the Vds=Vext-Vout comparison with (Vgs-Vth).

In our analysis, power MOSFET is in the linear region.

Page 6

LDO-PDN (2) – Model Approximation

ampop

loopopen

loopclosed

extbiasLDO

bias

Gain

fZfZ

VddIP

IRon

1

)()(

1

Vout

Iload

Rdie

Cdie Cint

RparOn Chip

Cext

Lpar

Rext

n2

Off Chip

n3

n4

Ron LDO

Page 7

Proposed Flow for Worst Case Loading LDO Optimization

LDO model PDN model

Zclose loop(f)

Poles/Zeros LDO PDN

Step Response

Worst Stimuli

Max Voltage Drop

Optimization

Optimum PLDO / Con chip

Page 8

Problem Formulation

P = LDO Power

C = Decoupling Capacitor

P0 = Power limit

I peak = Peak loading current of functional block

Vmax = Worst voltage drop based on rogue wave

Z LDO-PDN = impedance profile of ldo-pdn

peakstepload

chipon

LDO

loadstep

ItI

CCC

PPtoSubject

sZsIFtVMinimize

||)(||

)}()({)(

10

0

1

max

Page 9

LDO-PDN Output Impedance

impedance zero =

– Z1=-2.0011 x 1e9

– Z4,5= -0.0107 ± 0.0156i × 1e9

impedance pole =

– p1=-1.8177

– p4,5= -0.0125 ± 0.0142i × 1e9

Impedance k= 0.0091

0.0142i) 0.01251.8177)(s(s

)0156.00.01072.0011)(s0.009(s)(

i

sz

Page 10

Step Response of the LDO-PDN

BiAippppp

zpzpzpk

BiAippppp

zpzpzpk

ppppp

zpzpzpk

ppp

zzzk

ps

k

ps

k

ps

k

s

ksZ

ssV

1396.00002.0))((

))()((

1396.00002.0))((

))()((

1011.0))((

))()((

)(1

)(

23133

332313

4

32122

322212

3

31211

312111

2

321

321

1

3

4

2

3

1

21

Page 11

Analytical Worst Step Response

])0017.0

003.0[arctan(

10

1012.20

10014.0

100125.0

)]sin()cos([2)(

arg

9

0

9

9

1

21

ktt

v

tt

v

tBtAeekktV

k

elist

samllist

ttp

2048.11

1.

)001.0/002.0arctan()sin()cos(202

0121

e

ektB

ktA

tAe

tpekk

wcV

Page 12

“Rogue Wave” Phenomenon

Worst-case noise response: The maximum noise is formed when a long and slow oscillation followed by a short and fast oscillation.

Rogue wave: In oceanography, a large wave is formed when a long and slow wave hits a sudden quick wave.

0 0.5 1 1.5 2

x 10-6

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

0.04

Time (sec)

Vol

tage

(V

)

Low-frequency oscillation corresponds to the resonance of the 2nd stage

High-frequency oscillation corresponds to the resonance of the 1st stage

Page 13

Ideal Worst-Case PDN Noise

Problem formulation I

PDN noise:

Worst-case current [Xiang ’09]:

max ( )

s.t. 0 i(t) b

v t

0

( ) ( ) ( )t

v t h i t d ( ): PDN impulse responseh

( ) for ( ) 0i t b h ( ) 0 for ( ) 0i t h

Zero current transition time. Unrealistic!

Page 14

Rogue Wave based Current Vector Synthesis

14

Vector based Current Activity

Impedance of the PDN

FFT based convolution

Max partition

Synthesized Stimuli

Sign Off

Max Voltage Drop

Synthesized Stimuli

Synthesized Stimuli

PartitionImpulse

Response

Page 15

for i = 0 to N-window_sizeBegin sum each current peak of current pattern(i, i+window_size - 1)Endsorted_list_des = sorting the sum of the intervals of current peak descendingsorted_list_asc = sorting the sum of the intervals of current peak ascending

//here is for worst-case calculatingfor i = 0 to N-window_size and i is increased by window_size //N isthe size of impulse_reseponseif impulse_response(i) > 0 current_list = sorted_list_deselse current_list = sorted_list_ascEndfor j = 0 to M - window_size + 1 //M is the size of current patternidx_current = current_list(j)tmp_val = convolution of impulse_response(i, i + window_size - 1) andcurrent_pattern(idx_current, idx_current + window_size -1)if tmp_val > max_val max_val = tmp_val max_current(i, i+window_size -1) = current_pattern(idx_current,idx_current + window_size - 1)else breakendend //end of for jend //end of for i

Algorithm for Vector-based Rogue Wave Generation

Complexity of algorithm = N= Impulse response size m= Current windows size

)log(2 mN

Page 16

Vector-based Synthetic Rogue Wave

Page 17

Rogue-wave Synthesis Resolution Window Sensitivity to Vmax

For the rest of analysis, window resolution = 3nsec is chosen.

Page 18

Vmax LDO-PDN Voltage Drop (Overshoot)

Overshoot is a main concern for:Reliability of devicesHold margins

Page 19

Vmin LDO-PDN Voltage Drop (Undershoot)

undershoot is a main concern for:Functional failures

Optimum Configuration: Optimal Decap = 350pF Optimal Power= 20uW Noise = ~10mV

Page 20

Conclusion and Summary

Introduced a design flow for worst case loading based on LDO poles and zeros.

Proposed an optimization based on the step response and rogue wave in LDO system.

Analyzed LDO power and decap area trade off in the LDO based system.

Experimental result show the target voltage drop budget will be met under worst loading with optimum LDO power and decoupling value.