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Lecture 4 Design Rules,Layout and Stick DiagramPradondet Nilagupta [email protected] Department of Computer Engineering Kasetsart University

Acknowledgement

This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I cant remember where those slide come from. However, Id like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide cant be finished.

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Roadmap for the term: major topics

VLSI Overview CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools Systems Design using Verilog HDL Design Project: Complete ChipJanuary 9, 2012 3

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Review - CMOS Mask Layers

Determine placement of layout objects Color coding specifies layers Layout objects:

Rectangles Polygons Arbitrary shapes Absolute (micron) Scaleable (lambda)n well

Grid types P substrate wafer

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Mask Generation

Mask Design using Layout Editor user specifies layout objects on different layers output: layout file Pattern Generator Reads layout file Generates enlarged master image of each mask layer Image printed on glass Step & repeat camera Reduces & copies image onto mask One copy for each die on wafer Note importance of mask alignmentJanuary 9, 2012 5

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Symbolic Mask Layers

Key idea: Reduce layers to those that describe design Generate physical layers as needed Magic Layout Editor: "Abstract Layers metal1 (blue) - 1st layer metal (equiv. to physical layer) Poly (red) - polysilicon (equivalent to physical layer) ndiff (green) - n diffusion (combination of active, nselect) ntranistor (green/red crosshatch) - combined poly, ndiff pdiff (brown) - p diffusion (combination of active, pselect) ptransistor (brown/red crosshatch) - combined poly, pdiff contacts: combine layers, cut mask

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About Magic

Scalable Grid for Scalable Design Rules

Grid distance: Plambda) Value is process-dependent: P= 0.5 X minimum transistor length Paint squares on grid for each mask layer Layers to interact to form components (e.g. transistors)

Painting metaphor

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Mask Layers in Magic

Poly (red) N Diffusion (green) P Diffusion (brown) Metal (blue) Metal 2 (purple) Well (cross-hatching) Contacts (X)

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Magic User-Interface

Graphic Display Window

Cursor

Cursor Box - specifies area to paint

Command window (not shown)

accepts text commands Box :paint poly : paint red :paint ndiff :paint green Paint :write (poly) prints error & status messagesJanuary 9, 2012

Paint(ntransistor)

Paint(pdiff)

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Layer Interaction in Magic

Transistors - where poly, diffusion cross poly crosses ndiffusion - ntransistor poly crosses pdiffusion - ptransistor Vias - where layers connect Metal 1 connecting to Poly - polycontact Metal 1 connecting to P-Diffusion (normal) - pdc Metal 1 connecting to P-Diffusion (substrate contact) psc Metal 1 connecting to N-Diffusion (normal) - ndc Metal 1 connecting to N-Diffusion (substrate contact) nsc Metal 1 connecting to Metal 2 - viaJanuary 9, 2012 10

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Magic Layers - Examplensc p-transistor metal1 nwell polycontact poly polycontact poly metal1 psc ndc ndc ntransistor metal1

pdc

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Why we need design rules

Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.

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Manufacturing problems

Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.

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Transistor problems

Varaiations in threshold voltage:

oxide thickness; ion implanatation; poly variations.

Changes in source/drain diffusion overlap. Variations in substrate.

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Wiring problems

Diffusion: changes in doping -> variations in resistance, capacitance. Poly, metal: variations in height, width -> variations in resistance, capacitance. Shorts and opens:

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Oxide problems

Variations in height. Lack of planarity -> step coverage.metal 2 metal 2 metal 1

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Via problems

Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short.

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MOSIS SCMOS design rules

Designed to scale across a wide range of technologies. Designed to support multiple vendors. Designed for educational use. Ergo, fairly conservative.

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P and design rules

P is the size of a minimum feature. Specifying P particularizes the scalable rules. Parasitics are generally not specified in Punits

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Design Rules

Typical rules: Minumum size Minimum spacing Alignment / overlap Composition Negative features

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Types of Design Rules

Scalable Design Rules (e.g. SCMOS) Based on scalable coarse grid - P (lambda) Idea: reduce P value for each new process, but keep rules the same Key advantage: portable layout Key disadvantage: not everything scales the same Not used in real life Absolute Design Rules Based on absolute distances (e.g. 0.75m) Tuned to a specific process (details usually proprietary) Complex, especially for deep submicron Layouts not portableJanuary 9, 2012 21

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SCMOS Design Rules

Intended to be Scalable

Original rules: SCMOS Submicron: SCMOS-SUBM Deep Submicron: SCMOS-DEEP

Pictorial Summary: Book Fig. 2-24, p. 27 Authoritative Reference: www.mosis.org

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SCMOS Design Rule Summary

Line size and spacing: metal1: Minimum width=3P, Minimum Spacing=3P metal2: Minimum width=3P, Minimum Spacing=4P poly: Minimum width= 2P, Minimum Spacing=2P ndiff/pdiff: Minimum width= 3P, Minimum Spacing=3P minimum ndiff/pdiff seperation=10P wells: minimum width=10P, min distance form well edge to source/drain=5P Transistors: Min width=3P Min length=2P Min poly overhang=2PJanuary 9, 2012 23

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SCMOS Design Rule Summary

Contacts (Vias) Cut size: exactly 2P X 2P Cut separation: minimum 2P Overlap: min 1P in all directions Magic approach: Symbolic contact layer min. size 4P X 4P Contacts cannot stack (i.e., metal2/metal1/poly) Other rules cut to poly must be 3P from other poly cut to diff must be 3P from other diff metal2/metal1 contact cannot be directly over poly negative features must be at least 2P in size CMP Density rules (AMI/HP subm): 15% Poly, 30% MetalJanuary 9, 2012 24

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Design Rule Checking in Magic

Design violations displayed as error paint Find which rule is violated with ":drc whyPoly must overhang transistor by at least 2 (MOSIS rule #3.3)

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Scaling Design Rules

Effects of scaling down are positive See book, p. 78-79 - if everything scales, scaling circuit by 1/x increases performance by x Problem: not everything scales proportionally

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Aside - About MOSIS

MOSIS - MOS Implementation Service Rapid-prototyping for small chips Multi-project chip idea - several designs on the same wafer Reduced mask costs per design Accepts layout designs via email Brokers fabrication by foundries (e.g. AMI, Agilent, IBM, TSMC) Packages chips & ships back to designers Our designs will use AMI 1.5m process (more about this later)January 9, 2012 27

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Aside - About MOSIS

Some Typical MOSIS Prices (from www.mosis.org) AMI 1.5m Tiny Chip (2.2mm X 2.2mm) $1,080 AMI 1.5m 9.4mm X 9.7mm $17,980 AMI 0.5m 0-5mm2 $5,900 TSMC 0.25m 0-10mm2 $15,550 TSMC 0.18m 0-7mm2 $24,500 TSMC 100-159mm2 $63,250 + $900 X size MOSIS Educational Program (what we use) AMI 1.5m Tiny Chip (2.2mm X 2.2mm) FREE* AMI 0.5mm Tiny Chip (1.5mm X 1.5mm) FREE*

*sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., | AMI, Inc., DuPont Photomasks, and MOSIS

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Layout Considerations

Break layout into interconnected cells Use hierarchy to control complexity Connect cells by

Abutment Added wires Minimize size of overall layout Meet performance constraints Meet design time deadlinesJanuary 9, 2012 29

Key goals:

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Hierarchy in Layout

Chips are constructed as a hierarchy of cells

Leaf cells - bottom of hierarchy Root cells - contains overall cell Pad frame - ring that contains I/O pads Core - contains logic organized as subcellsShift register FSM Other cells

Example - hypothetical UART

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Hierarchy Example

Root Cell: UARTRoot Cell: UART

Pad Frame

Core

Pad 1

Pad 2

...

Pad N

Shift Register

FSM

Other Cells

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Wires

6 3 3 3 2204424 Digital Design Automation

metal 3 metal 2 metal 1 pdiff/ndiff polyJanuary 9, 2012 32

Transistors

2 3 2 3 1 5

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Vias

Types of via: metal1/diff, metal1/poly, metal1/metal2.

4 1 2

4

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Metal 3 via

Type: metal3/metal2. Rules:

cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2

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Tub tie

4 1

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Spacings

Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4

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Overglass

Cut in passivation layer. Minimum bonding pad: 100 Qm. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2/3: 30 Minimum pad spacing to unrelated metal1, poly, active: 15

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Stick diagrams (1/3)

A stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

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Stick Diagrams (2/3)

Key idea: "Stick figure cartoon" of a layout Useful for planning layout

relative placement of transistors assignment of signals to layers connections between cells cell hierarchy

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Stick Diagrams (3/3)

Layers Metal (BLUE) Polysilicion (RED ) N-Diffusion (Green) P -Diffusion (Brown) Contact / Via

Connection Rules poly n-diff p-diff metal poly n-diff p-diff metal S N S P X S NC NC NC S

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Example - Stick Diagrams (1/2)

A

B

Alternatives - Pull-up NetworkA

B

Circuit Diagram.

Pull-Down Network (The easy part!)

Complete Stick Diagram

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Example - Stick Diagrams (2/2)

Vdd

Vdd A

In

Out

B

Out

Gnd Inverter

Gnd NAND Gate

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Dynamic latch stick diagramVDD

in

out

VSS phi204424 Digital Design Automation

phiJanuary 9, 2012 44

Stick Diagram XOR Gate Examples

VddA A A B B

AA Out A A

B

B A A

Out

B

B

B

B

A B Gnd Exclusive OR Gate

B

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Hierarchical Stick Diagrams

Define cells by outlines & use in a hierarchy to build more complex cellsVdd A B Vdd Vdd A NAND B Vdd

Out

Out

Gnd

Gnd

Gnd

Gnd

NAND Cell Stick Diagram

NAND Cell Outline

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Cell Connection Schemes

External connection - wire cells together Abutment - design cells to connect when adjacent Reflection, mirroring - use to make abutment possible

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Example: 2-input multiplexer

First cut:Vdd AA S OUT B SVdd A Vdd Out

NAND

S

B Gnd

Gnd

Vdd A

Vdd Out

NAND

Out

B OUT = A*S + B*S S Gnd

Vdd A

Vdd Out

B Gnd

Gnd

NANDB Gnd Gnd

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Sticks design of multiplexer

Start with NAND gate:+

out b a

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NAND sticksVDD a

out

b

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Refined one-bit Mux Design

Use NAND cell as black box Arrange easy power connections Vertical connections for allow multiple bitsselectVdd A B Vdd A Out Vdd

selectVdd A Out Vdd Vdd A Out Out Vdd

NANDGnd B Gnd Gnd

NANDB Gnd Gnd

NANDB Gnd Gnd

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3-bit mux sticksselect a2 b2 ai bi select select select

m2(one-bit-mux)

VDD oi VSS

o2

a1 b1

ai bi

select

select

m2(one-bit-mux)select select

VDD oi VSS VDD oi VSS

o1

a0 b0

ai bi

m2(one-bit-mux)

o0

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Multiple-Bit Mux

selectVdd A0 A0 Vdd A Out Vdd

selectVdd A Out Vdd Vdd A Out Out0 Vdd

NANDGnd B Gnd Gnd

NANDB Gnd Gnd

NANDB Gnd Gnd

Vdd A1 B1

Vdd A

Vdd Out

Vdd A

Vdd Out

Vdd A

Vdd Out Out1

NANDGnd B Gnd Gnd

NANDB Gnd Gnd

NANDB Gnd Gnd

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Cell Mirroring, Overlap

Use mirroring, overlap to save areaVdd A0 B0 Vdd A Out Vdd Vdd A Out Vdd Vdd A Out Vdd

NANDGnd B Gnd Gnd

NANDB Gnd Gnd

NANDB Gnd Gnd

B1 A1 Vdd

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Example: Layout / Stick Diagram

Create a layout for a NAND gate given constraints:

Use minimum-size transistors Assume power supply lines pass through cell from left to right at top and bottom of cell Assume inputs are on left side of cell Assume output is on right side of cell Optimize cell to minimize width Optimize cell to minimize overall area

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Layout Example

Vdd!A B

Vdd!

AA

OUT

B

B

Gnd!

Gnd!

Circuit Diagram.

Exterior of Cell

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Example - Magic Layout

Overall Layout: 52 X 16

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Review - VLSI Levels of AbstractionSpecification(what the chip does, inputs/outputs)

Architecturemajor resources, connections

Register-Transferlogic blocks, FSMs, connections

Logicgates, flip-flops, latches, connections

Circuittransistors, parasitics, connections

You are Here

Layoutmask layers, polygons58

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Levels of Abstraction Perspective

Right now, were focusing on the low level:

Circuit level - transistors, wires, parasitics Layout level - mask objects Logic level - individual gates, latches, flip-flops Register- transfer level - Verilog HDL Behavior level - Specifications

Well work upward to higher levels:

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The Challenge of Design

Start: higher level (spec) Finish: lower level (implementation) Must meet design criteria and constraints

Design time - how long did it take to ship a product? Performance - how fast is the clock? Cost - NRE + unit cost

CAD tools - essential in modern design

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CAD Tool Survey: Layout Design

Layout Editors Design Rule Checkers (DRC) Circuit Extractors Layout vs. Schematic (LVS) Comparators Automatic Layout Tools

Layout Generators ASIC: Place/Route for Standard Cells, Gate Arrays

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Layout Editors

Goal: produce mask patterns for fabrication Grid type:

Absolute grid (MAX, LASI, LEdit, Mentor ICStation, other commercial tools) Magic: lambda-based grid - easier to learn, but less powerful Absolute mask (one layer for each mask) Magic: symbolic masks (layers combine to generate actual mask patterns)January 9, 2012 62

Mask description:

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Design Rule Checkers

Goal: identify design rule violations Often a separate tool (built in to Magic) General approach: scanline algorithm Computationally intensive, especially for large chips

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Circuit Extractors

Goal: extract netlist of equivalent circuit

Identify active components Identify parasitic componentsCapacitors Resistors

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Layout Versus Schematic (LVS)

Goal: Compare layout, schematic netlists

Compare transistors, connections (ignore parasitics) Issue error if two netlists are not equivalent Important for large designs

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Automatic Layout Tools

Layout Generators - produce cell from spec.

Simple: Procedural specification of layout (see book Fig. 2-33, p. 95) Complex: Netlist - places & wires individual transistors Standard Cells - use predefined cells as "cookie cutters" Gate Arrays - configurable pre-manufactured gates (only change metal masks) FPGAs - electrically configurable array of gatesJanuary 9, 2012 66

ASIC - Place, route modules with fixed shape

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Layout design and analysis tools

Layout editors are interactive tools. Design rule checkers are generally batch--identify DRC errors on the layout. Circuit extractors extract the netlist from the layout. Connectivity verification systems (CVS) compare extracted and original netlists.

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Automatic layout

Cell generators (macrocell generators) create optimized layouts for ALUs, etc. Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing.

Sea-of-gates allows routing over the cell.

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Standard cell layout

routing area routing area

routing area

routing area

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