Lecture04-2005 Drc Rules

8/18/2019 Lecture04-2005 Drc Rules

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Lecture 4 Design Rules,Layout and

Stick Diagram

Pradondet Nilagupta

[email protected]

Department of Computer Engineering

Kasetsart University


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Acknowledgement

'his lecture note has (een summari)ed fromlecture note on *ntroduction to +,-* Design!+,-* Circuit Design all over the orld. * can/t

remem(er here those slide come from.0oever! */d like to thank all professors hocreate such a good ork on those lecturenotes. 1ithout those lectures! this slide can/t

(e finished.


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Roadmap for the term: majortopics

+,-* 3vervieC43- Processing 5 6a(rication

Components7 'ransistors! 1ires! 5 Parasitics

Design 8ules 5 ,ayoutCom(inational Circuit Design 5 ,ayout

-e9uential Circuit Design 5 ,ayout

-tandard:Cell Design ith CAD 'ools-ystems Design using +erilog 0D,

Design Pro;ect7 Complete Chip


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P substrate

Review - CMOS Mask Layers

Determine placement oflayout o(;ects

Color coding specifieslayers

,ayout o(;ects7 8ectangles

Polygons

Ar(itrary shapes

micron?

-calea(le =>lam(da? wafer

n well


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Mask eneration

4ask Design using ,ayout Editor user specifies layout o(;ects on different layers

output7 layout file

Pattern


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Sym!olic Mask Layers

Key idea7 8educe layers to those that descri(e design


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A!o"t Magic

-cala(le


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Mask Layers in Magic

Poly =redN Diffusion =green

P Diffusion =(ron

4etal =(lue4etal " =purple

1ell =cross:hatching

Contacts =F


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Magic #ser-$nterface


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Layer $nteraction in Magic

'ransistors : here poly! diffusion cross poly crosses ndiffusion : ntransistor

poly crosses pdiffusion : ptransistor

+ias : here layers connect

4etal $ connecting to Poly : polycontact4etal $ connecting to P:Diffusion =normal : pdc

4etal $ connecting to P:Diffusion =su(strate contact : psc

4etal $ connecting to N:Diffusion =normal : ndc

4etal $ connecting to N:Diffusion =su(strate contact : nsc4etal $ connecting to 4etal " : via


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Magic Layers - %&ample

nwell

nsc

psc

p-transistor

ntransistor

metal1

metal1

metal1

poly

poly

ndc ndc

polycontact

polycontact

pdc


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'hy we need design r"les

4asks are tooling for manufacturing.4anufacturing processes have inherent

limitations in accuracy.

Design rules specify geometry of maskshich ill provide reasona(le yields.

Design rules are determined (y eIperience.


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Man"fact"ring pro!lems

Photoresist shrinkage! tearing.+ariations in material deposition.

+ariations in temperature.

+ariations in oIide thickness. *mpurities.

+ariations (eteen lots.

+ariations across a afer.


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(ransistor pro!lems

+araiations in threshold voltage7oIide thicknessJ

ion implanatationJ

poly variations.Changes in sourcedrain diffusion overlap.

+ariations in su(strate.


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'iring pro!lems

Diffusion7 changes in doping : variations inresistance! capacitance.

Poly! metal7 variations in height! idth :

variations in resistance! capacitance.-horts and opens7


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O&ide pro!lems

+ariations in height. ,ack of planarity : step coverage.

metal 1metal 2

metal 2


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)ia pro!lems

+ia may not (e cut all the ay through.Undesi)e via has too much resistance.

+ia may (e too large and create short.


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MOS$S SCMOS design r"les

Designed to scale across a ide range oftechnologies.

Designed to support multiple vendors.

Designed for educational use.Ergo! fairly conservative.


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and design r"les

λ is the si)e of a minimum feature.-pecifying λ particulari)es the scala(le rules.

Parasitics are generally not specified in

λ units.


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(ypes of *esign R"les

-cala(le Design 8ules =e.g. -C43- Hased on scala(le >coarse grid? : λ =lam(da

*dea7 reduce λ value for each ne process! (ut keep rulesthe same

Key advantage7 porta(le layoutKey disadvantage7 not everything scales the same

Not used in >real life?

A(solute Design 8ules

Hased on a(solute distances =e.g. #.Lm 'uned to a specific process =details usually proprietary

CompleI! especially for deep su(micron

,ayouts not porta(le


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SCMOS *esign R"les

*ntended to (e -cala(le3riginal rules7 -C43-

-u(micron7 -C43-:-UH4

Deep -u(micron7 -C43-:DEEPPictorial -ummary7 Hook 6ig. ":"&! p. "

Authoritative 8eference7 .mosis.org


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SCMOS *esign R"le S"mmary

,ine si)e and spacing7metal$7 4inimum idth2λ! 4inimum -pacing2λ

metal"7 4inimum idth2λ! 4inimum -pacing&λ

poly7 4inimum idth "λ! 4inimum -pacing"λ

ndiffpdiff7 4inimum idth 2λ! 4inimum -pacing2λ, minimum ndiffpdiff seperation$#λ

ells7 minimum idth$#λ!min distance form ell edge to sourcedrainλ

'ransistors7

4in idth2λ

4in length"λ

4in poly overhang"λ


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SCMOS *esign R"le S"mmary

Contacts =+ias Cut si)e7 eIactly "λ F "λ

Cut separation7 minimum "λ

3verlap7 min $λ in all directions

4agic approach7 -ym(olic contact layer min. si)e &λ F &λ Contacts cannot stack =i.e.! metal"metal$poly

3ther rules

cut to poly must (e 2λ from other poly

cut to diff must (e 2λ from other diff metal"metal$ contact cannot (e directly over poly

negative features must (e at least "λ in si)e

C4P Density rules =A4*0P su(m7 $M Poly! 2#M 4etal


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*esign R"le Checking in Magic

Design violationsdisplayed as error paint

6ind hich rule isviolated ith B:drc

why? Poly must overhang

transistor by at

least 2 (MOSIS rule

#3.3)


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Scaling *esign R"les

Effects of scaling don are positive-ee (ook! p. G: : if >everything? scales!

scaling circuit (y $I increases performance

(y IPro(lem7 not everything scales proportionally


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Aside - A!o"t MOS$S

43-*- : 43- *mplementation -ervice 8apid:prototyping for small chips

4ulti:pro;ect chip idea : several designs on the sameafer

8educed mask costs per design Accepts layout designs via email

Hrokers fa(rication (y foundries=e.g. A4*! Agilent! *H4! '-4C

Packages chips 5 ships (ack to designers

3ur designs ill use A4* $.Lm process=more a(out this later


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Aside - A!o"t MOS$S

-ome 'ypical 43-*- Prices =from .mosis.org A4* $.Lm >'iny Chip? ="."mm F "."mm $!#G#

A4* $.Lm .&mm F .mm $!G#

A4* #.Lm #:mm" !##

'-4C #."Lm #:$#mm" $!#

'-4C #.$GLm #:mm" "&!##

'-4C $##:$mm" %2!"# O ## F si)e

43-*- Educational Program =hat e use

A4* $.Lm >'iny Chip? ="."mm F "."mm 68EE

A4* #.mm >'iny Chip? =$.mm F $.mm 68EE

*sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., | AMI, Inc., DuPont Photomasks, and MOSIS


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Layo"t Considerations

Hreak layout into interconnected cellsUse hierarchy to control compleIity

Connect cells (y A(utment Added ires

Key goals7

4inimi)e si)e of overall layout4eet performance constraints

4eet design time deadlines


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+ierarchy in Layo"t

Chips are constructed as a hierarchy of cells,eaf cells : (ottom of hierarchy

8oot cells : contains overall cell

EIample : hypothetical >UA8'?Pad frame : >ring? that contains *3 pads

Core : contains logic organi)ed as su(cells-hift register

6-4

3ther cells


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+ierarchy %&ample

8oot Cell7 UA8'

Root Cell:UART

PadFrame

Core

Pad 1 Pad 2 ... Pad N ShiftRegister

FSM OtherCells


32/69

2"

'ires

metal 36

metal 23

metal 13

pdiff/ndiff 3

poly2


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(ransistors

2

3

1

32

5


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)ias

'ypes of via7 metal$diff! metal$poly!metal$metal".

4

1

4

2


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Metal , via

'ype7 metal2metal".8ules7 cut7 2 I 2

overlap (y metal"7 $minimum spacing7 2

minimum spacing to via$7 "


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Overglass

Cut in passivation layer.4inimum (onding pad7 $## µm.

Pad overlap of glass opening7 %

4inimum pad spacing to unrelated metal"272#

4inimum pad spacing to unrelated metal$!

poly! active7 $


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Stick diagrams ./,0

A stick diagram is a cartoon of a layout.Does sho all componentsvias =eIcept

possi(ly tu( ties! relative placement.

Does not sho eIact placement! transistorsi)es! ire lengths! ire idths! tu((oundaries.


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Stick *iagrams 1/,0

Key idea7 B-tick figure cartoonB of a layoutUseful for planning layout relative placement of transistors

assignment of signals to layers connections (eteen cells

cell hierarchy


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Stick *iagrams ,/,0

Metal (BLUE)

Polysilicion (RED)N-Diffusion (Green)

P-Diffusion (Brown)

Contact / Via

poly

n-diff

p-diff

metal

polyn-diffp-diffmetal

S N P NC

S X NC

S NC

S

Connection RulesLayers


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%&ample - Stick *iagrams ./10

A B

A

B

Circuit Diagram. Pull-Down Network(The easy part!)

Alternatives - Pull-up Network

Complete Stick Diagram


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*ynamic latch stick diagram

VDD

in

VSS

phi phi’

out

Sti k *i 2OR t


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Stick *iagram 2OR ate%&amples

Exclusive OR Gate

Vdd

A

Out

Gnd

B

A’ B’

A’

B’

B

A’

Out

A A’

B B’

A

B’

A

B

A’

B’

A’

B


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+ierarchical Stick *iagrams

Define cells (y outlines 5 use in a hierarchyto (uild more compleI cells

Vdd

A

Out

Gnd

B

Vdd

Gnd

Vdd

A

Out

Gnd

B

Vdd

Gnd

NAND

NAND CellStick Diagram NAND CellOutline


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Cell Connection Schemes

EIternal connection : ire cells together A(utment : design cells to connect hen

ad;acent

8eflection! mirroring : use to make a(utmentpossi(le


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%&ample: 1-inp"t m"ltiple&er

6irst cut7Vdd

A

Out

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

S

B

S’

Gnd

A

S

B

S’

OUT

OUT = A*S + B*S’


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Sticks design of m"ltiple&er

-tart ith NAND gate7


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3A3* sticks

VDD

a

VSS

out

b


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Refined one-!it M"& *esign

Use NAND cell as (lack (oI Arrange easy poer connections

+ertical connections for allo multiple (its

NAND

A

B

Gnd

Vdd

Gnd

Vdd

OutNAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

select’ select

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

VddAB

Gnd

Out


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M"ltiple-4it M"&

select’ select

NAND

A

B

Gnd

Vdd

Gnd

Vdd

OutNAND

A

B

Gnd

Vdd

Gnd

Vdd

OutNAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

VddA0A0

Gnd

Out0

NAND

A

BGnd

Vdd

Gnd

Vdd

OutNAND

A

BGnd

Vdd

Gnd

Vdd

OutNAND

A

BGnd

Vdd

Gnd

Vdd

Out

VddA1B1

Gnd

Out1


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Cell Mirroring5 Overlap

Use mirroring! overlap to save area

VddA0B0

Gnd

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

B1A1

Vdd


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%&ample: Layo"t / Stick *iagram

Create a layout for a NAND gate givenconstraints7Use minimum:si)e transistors

Assume poer supply lines >pass through? cellfrom left to right at top and (ottom of cell

Assume inputs are on left side of cell

Assume output is on right side of cell

3ptimi)e cell to minimi)e idth3ptimi)e cell to minimi)e overall area


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Layo"t %&ample

A B

A

B

A

B

OUT

Vdd!Vdd!

Gnd! Gnd!

Circuit Diagram. Exterior of Cell


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%&ample - Magic Layo"t

3verall ,ayout7 " F $%

Review - )LS$ Levels of


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Review - )LS$ Levels ofA!straction

Specification(what the chip does, inputs/outputs)

Architecturemajor resources, connections

Register-Transferlogic blocks, FSMs, connections

Circuittransistors, parasitics, connections

Layoutmask layers, polygons

Logicgates, flip-flops, latches, connections

You are Here

Levels of A!straction -


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Levels of A!straction -6erspective

8ight no! e/re focusing on the >lo level?7Circuit level : transistors! ires! parasitics

,ayout level : mask o(;ects

1e/ll ork upard to higher levels7,ogic level : individual gates! latches! flip:flops

8egister: transfer level : +erilog 0D,

Hehavior level : -pecifications


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(he Challenge of *esign

-tart7 higher level =spec 6inish7 loer level =implementation

4ust meet design criteria and constraints

Design time : ho long did it take to ship aproductQ

Performance : ho fast is the clockQ

Cost : N8E O unit cost

CAD tools : essential in modern design


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%$

CA* (ool S"rvey: Layo"t *esign

,ayout EditorsDesign 8ule Checkers =D8C

Circuit EItractors

,ayout vs. -chematic =,+- Comparators Automatic ,ayout 'ools,ayout


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Layo"t %ditors


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*esign R"le Checkers


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Circ"it %&tractors


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Layo"t )ers"s Schematic L)S0


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Layo"t design and analysis tools

,ayout editors are interactive tools.Design rule checkers are generally (atch:::

identify D8C errors on the layout.

Circuit eItractors eItract the netlist from thelayout.

Connectivity verification systems =C+-

compare eItracted and original netlists.


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A"tomatic layo"t

Cell generators =macrocell generators createoptimi)ed layouts for A,Us! etc.

-tandard cellsea:of:gates layout creates

layout from predesigned cells O customrouting.-ea:of:gates allos routing over the cell.


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Standard cell layo"t

#outin$ a#ea

#outin$ a#ea # o u t i n $ a

# e a

#outin

$

a#ea

Documents

Lecture04-2005 Drc Rules