Lecture 5: Scaled MOSFETS for ICs

MSE 6001, Semiconductor Materials LecturesFall 2006

5 MOSFETS and scaling

Silicon is a mediocre semiconductor, and several other semiconductors have better electrical andoptical properties. However, the very high quality of the electrical properties of the silicon-silicondioxide interface allows very good metal-oxide-semiconductor field-effect transistors (MOSFETs)to be fabricated. These devices have several properties, such as operation frequency and power con-sumption, that improve as their size is scaled down to smaller dimensions, which also allows moretransistors to be packed onto a chip. The smaller sizes are achieved using higher-resolution pho-tolithography, which is improved by steadily improving the fabrication technologies. The trends ofsteadily improving performance and greater integration density with time are generically refered toas “Moore’s Law”. Of course, scaling has to end eventually, somewhere before the scale of atomsis reached.

5.1 Basic MOSFET

MOSFETs turn on and off via the non-linear gate capacitor between the gate electrode and thesubstrate. The MOSFET of Fig. 1 controls the flow of electrons (an NMOSFET) from then-typesource electrode to then-type drain electrode.

A positive gate potential attracts a very thin layer of electrons to the surface of the substrate,at its interface with the oxide, forming a “channel” that allows current to be conducted from the

Transmission electron micrograph of MOSFET,

Intel 65 nm process

A 70 Mbit SRAM test vehicle with >0.5 billion transistors and incorporating all of the features described in this paper has been fabricated on this technology. The aggressive de-sign rules allow for a small 0.57!m2 6-T SRAM cell that is also compatible with high performance logic processing. A top view of the cell after poly patterning is shown in Figure 12. In addition to small size, this cell has a robust static noise margin down to 0.7V VDD to allow low voltage opera-tion (Fig. 13). Figure 14 is a Shmoo plot for the 70 Mb SRAM operating frequency vs voltage, showing the SRAM operates at 3.43 GHz at 1.2V. A die photo is shown in Fig-ure 15.

VII. Conclusion We have developed an industry leading 65nm CMOS tech-nology for high performance microprocessors with excel-lent transistor and interconnect performance, along with aggressive dimensional scaling. A high performance, high density 70 Mbit SRAM test vehicle has been successfully fabricated utilizing all of the 65nm process features. This 65nm technology is on track for high volume manufactur-ing in 2005.

References [1] K. Mistry, et al., Symp. VLSI Tech. Dig., 2004. [2] T. Ghani, et al., IEDM Tech. Dig., pp. 197-200, 2003. Layer Pitch

(nm) Thick (nm)

AspectRatio

Isolation 220 320 - Polysilicon 220 90 - Contacted gate pitch 220 - - Metal 1 210 170 1.6 Metal 2 210 190 1.8 Metal 3 220 200 1.8 Metal 4 280 250 1.8 Metal 5 330 300 1.8 Metal 6 480 430 1.8 Metal 7 720 650 1.8 Metal 8 1080 975 1.8 Table 1: Layer pitch, thickness and aspect ratio

0.1

1

10

1994 1996 1998 2000 2002 2004 2006

Con

tact

ed G

ate

Pitc

h (u

m)

0.1

1

10

SR

AM

Cel

l Are

a (u

m2)SRAM Cell Area

0.5x every 2 years

65nmContacted Gate Pitch

0.7x every 2 years

250nm

180nm

130nm

90nm

Figure 1: Intel contacted gate pitch and SRAM area trends

Figure 2: Transistor size trend for technology nodes.

Figure 3: TEM cross section of 35nm NMOS

PMOSPMOS

Figure 4: TEM cross section of 35nm PMOS

P. Bai, et al., “65 nm Logic Technology Featuring 35 nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD, and 0.57 µm2 SRAM Cell”, IEDM Proceedings, 2004

L = 35 nm

FIGURE 1: The MOSFET gate controls the conductivity between the source and drain.

5-1

thicknessof theburiedoxide.For thickburiedoxide, there isnobacksidescreeningofthedrainpotential,resultinginrelativelypoor scaling characteristics compared to other device types[10]–[13]. Since such devices are not likely to be used at thelimits of scaling they are not discussed here. We do, however,discuss the scaling advantages of the more novel double gatedtype of FD-SOI MOSFETs, wherein both the insulator on theback side of the Si channel layer and the Si layer itself are verythin so that both sides of the channel are gated. There are alsoin-between FD-SOI MOSFETs with buried oxide thin enoughto offer some screening, but not thin enough for use in activeswitching. These devices are interesting from a circuit point ofview since the back gate can be used to dynamically adjust thethresholdvoltage,butarenotdiscussedhereforlackofspace.

The outline of the paper is as follows. Section II ad-dresses some of the more fundamental limitations to thecontinued scaling of MOSFETs that appear to be on thehorizon. Based only on these fundamental limits, it maybe possible to scale FETs down to very small dimensions,e.g., 10-nm channel length or smaller. Section III describesresearch results related to this fundamental limit regime:very tiny one-of-a-kind FETs. In the more practical world ofmanufacturing, however, there are many types of variationsand fluctuations that require the design of MOSFETs withtolerances. In Section IV, we look at some of these practicallimitations and their consequences for device design. Sec-tion V describes how the concepts of the previous sectionsplay out when they are applied to meeting the needs ofspecific classes of applications. The paper ends in Section VIby summarizing all of the limits into a large table, followedby the conclusion in Section VII.

II. FUNDAMENTAL SCALING LIMITS

A. Scaling TheoryFor many years now, the shrinking of MOSFETs has been

governed by the ideas of scaling [14], [15]. The basic idea isillustrated in Fig. 1: a large FET is scaled down by a factor

to produce a smaller FET with similar behavior. When allof the voltages and dimensions are reduced by the scalingfactor and the doping and charge densities are increasedby the same factor, the electric field configuration inside theFET remains the same as it was in the original device. Thisis called constant field scaling, which results in circuit speedincreasing in proportion to the factor and circuit densityincreasing as . These scaling relations are shown in thesecond column of Table 1 along with the scaling behavior ofsome of the other important physical parameters.

Fig. 2 illustrates the actual past and projected futurescaling behavior of several of these parameters versus thechannel length [16]. As can be seen, the voltages have notbeen scaled at the same rate as the length, in violation of thesimple scaling rules outlined above. In earlier generations ofMOSFETs, this occurred because carrier velocities were in-creasing with increasing field, yielding higher performance,while deleterious high-field effects were kept in check bythe gradually descending voltage. More recently, carriervelocities have become saturated, but voltage scaling has

Fig. 1. Schematic illustration of the scaling of Si technology by afactor alpha. Adapted from [5].

Table 1Technology Scaling Rules for Three Cases

is the dimensional scaling parameter, is the electric field scalingparameter, and and are separate dimensional scaling parameters forthe selective scaling case. is applied to the device vertical dimensionsand gate length, while applies to the device width and the wiring.

been slow because of the nonscaling of the subthresholdslope and the OFF current. To accommodate this trend,more generalized scaling rules have been created, in whichthe electric field is allowed to increase by a factor [17].Furthermore, the device widths and wiring dimensions havenot been scaled as fast as the channel lengths, leading toa further scaling parameter for those dimensions. Thesegeneralized rules are also shown in Table 1 and are describedin more detail in [5], [9], and [18].

The preceding scaling rules do not tell a designer howshort he can make a MOSFET for given doping profiles andlayer thicknesses; they only describe how to shrink a knowngood design. Furthermore, since the built-in potentials arenot usually scaled, the rules are inaccurate anyway. To findthe minimum gate length at each generation of technology,one must analyze the two-dimensional (2-D) field effectsinside the FET. This is often done numerically using com-plex 2-D simulation tools, but the recent analytic analysisby Frank et al. [19] reveals the primary dependencies. Other

260 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

FIGURE 2: Scaling the size of a MOSFET.

source to drain. The gate lengthL is the separation between the source and drain. The smallestfeature that can be fabricated in an IC technology is approximated by the “half-pitch width”, whichcharacterizes the IC technology and is a measure ofL. For example, this year 65 nm technologyICs have been in full production, and 45 nm technology chips will be introduced. The gate lengthsfor the 65 nm technology is approximately 35 nm. The thin gate oxide, made from silicon dioxide,has a thicknesstox, which in the current advanced chips is approximately 2 nm thick.

5.2 Scaling

Figure 2 (Frank, et al., “Device scaling limits of Si MOSFETs and their application dependencies”,Proc. IEEE, 2001) depicts the effects of scaling and Fig. 3 tables the resulting changes in transistorand circuit properties.

Scaling will be limited by a number of issues. For a very thin gate oxide, less than about 1nm, electrons can quantum mechanically tunnel directly from the gate electrode to the conductingchannel, giving large leakage currents. For very short channels, electrons can tunnel directly fromthe source to drain, forL less than about 5 nm. Some of the smallest transistors made to date haveL ≈ 6 nm. Doping becomes a problem, because the random distribution of dopant atoms meansthat different MOSFETs have different numbers of dopants and thus different electrical properties.At the highest doping levels, which can approach 1019 cm−3, the dopant atom spacing is onlyabout 3 nm. The gate metal is also expected to change. Since approximately 1980, heavily-dopedpolycrystalline silicon (poly) has been the preferred gate “metal”. However, at oxide thicknessesbelow about 1.5 nm, the semiconducting properties of the poly become important, manifested as a∼ 1 nm scale depletion layer, and actual metals will need to be used.

5.3 25 nm MOSFET technologies

Within a few years, the semiconductor industry expects to produce 25 nm MOSFETs, where,by comparison, the current Intel 65 nm technology has 35 nm physical gate lengths, A genericdevice that has been studied is schematically given in Fig. 4 (Frank, et al.). This IC technology

5-2

thicknessof theburiedoxide.For thickburiedoxide, there isnobacksidescreeningofthedrainpotential,resultinginrelativelypoor scaling characteristics compared to other device types[10]–[13]. Since such devices are not likely to be used at thelimits of scaling they are not discussed here. We do, however,discuss the scaling advantages of the more novel double gatedtype of FD-SOI MOSFETs, wherein both the insulator on theback side of the Si channel layer and the Si layer itself are verythin so that both sides of the channel are gated. There are alsoin-between FD-SOI MOSFETs with buried oxide thin enoughto offer some screening, but not thin enough for use in activeswitching. These devices are interesting from a circuit point ofview since the back gate can be used to dynamically adjust thethresholdvoltage,butarenotdiscussedhereforlackofspace.

The outline of the paper is as follows. Section II ad-dresses some of the more fundamental limitations to thecontinued scaling of MOSFETs that appear to be on thehorizon. Based only on these fundamental limits, it maybe possible to scale FETs down to very small dimensions,e.g., 10-nm channel length or smaller. Section III describesresearch results related to this fundamental limit regime:very tiny one-of-a-kind FETs. In the more practical world ofmanufacturing, however, there are many types of variationsand fluctuations that require the design of MOSFETs withtolerances. In Section IV, we look at some of these practicallimitations and their consequences for device design. Sec-tion V describes how the concepts of the previous sectionsplay out when they are applied to meeting the needs ofspecific classes of applications. The paper ends in Section VIby summarizing all of the limits into a large table, followedby the conclusion in Section VII.

II. FUNDAMENTAL SCALING LIMITS

A. Scaling TheoryFor many years now, the shrinking of MOSFETs has been

governed by the ideas of scaling [14], [15]. The basic idea isillustrated in Fig. 1: a large FET is scaled down by a factor

to produce a smaller FET with similar behavior. When allof the voltages and dimensions are reduced by the scalingfactor and the doping and charge densities are increasedby the same factor, the electric field configuration inside theFET remains the same as it was in the original device. Thisis called constant field scaling, which results in circuit speedincreasing in proportion to the factor and circuit densityincreasing as . These scaling relations are shown in thesecond column of Table 1 along with the scaling behavior ofsome of the other important physical parameters.

Fig. 2 illustrates the actual past and projected futurescaling behavior of several of these parameters versus thechannel length [16]. As can be seen, the voltages have notbeen scaled at the same rate as the length, in violation of thesimple scaling rules outlined above. In earlier generations ofMOSFETs, this occurred because carrier velocities were in-creasing with increasing field, yielding higher performance,while deleterious high-field effects were kept in check bythe gradually descending voltage. More recently, carriervelocities have become saturated, but voltage scaling has

Fig. 1. Schematic illustration of the scaling of Si technology by afactor alpha. Adapted from [5].

Table 1Technology Scaling Rules for Three Cases

is the dimensional scaling parameter, is the electric field scalingparameter, and and are separate dimensional scaling parameters forthe selective scaling case. is applied to the device vertical dimensionsand gate length, while applies to the device width and the wiring.

been slow because of the nonscaling of the subthresholdslope and the OFF current. To accommodate this trend,more generalized scaling rules have been created, in whichthe electric field is allowed to increase by a factor [17].Furthermore, the device widths and wiring dimensions havenot been scaled as fast as the channel lengths, leading toa further scaling parameter for those dimensions. Thesegeneralized rules are also shown in Table 1 and are describedin more detail in [5], [9], and [18].

The preceding scaling rules do not tell a designer howshort he can make a MOSFET for given doping profiles andlayer thicknesses; they only describe how to shrink a knowngood design. Furthermore, since the built-in potentials arenot usually scaled, the rules are inaccurate anyway. To findthe minimum gate length at each generation of technology,one must analyze the two-dimensional (2-D) field effectsinside the FET. This is often done numerically using com-plex 2-D simulation tools, but the recent analytic analysisby Frank et al. [19] reveals the primary dependencies. Other

260 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

FIGURE 3: Scaling properties of silicon MOSFETs.

should enable many new applications, as tabled in Fig. 5, including, for example, the ability totranslate languages in real time that will only require 0.2 cm2 of chip area and need only 10 mW ofpower. Human intelligence-scale computation power would require some tens-of-square meters,according to Frank, et al.,Device Research Conference, 1999.

5.4 New materials needed for scaling

Since the early 1980s, the materials used for integrated MOSFETS on silicon substrates have notchanged greatly. The gate “metal” is made from highly-doped polycrystalline silicon. The gateoxide is silicon dioxide. For the smallest devices, these materials will need to be replaced.

5.4.1 New gate oxides

The capacitance per area of the gate oxide is

Cox =εox

tox

=Kεo

tox

, (1)

whereεox is the permitivity of the oxide,εo the permitivity of the vacuum, andK the dielectricconstant. Scaled MOSFETs require largerCox, which has been achieved with smallertox. Increas-ing K can also increaseCox, and other oxides, “high K dielectrics” are being developed, includingfor example, mixtures of HfO2 and Al2O3.

5-3

Fig. 15. Source, drain, and superhalo doping contours in a 25-nmnMOSFET design. The channel length is defined by the pointswhere the source–drain doping concentration falls to 2 10 cm .Dashed lines show the potential contours for zero gate voltage anda drain bias of 1.0 V. refers to the midgap energy level of thesubstrate. From [27].

Fig. 16. Subthreshold currents for channel lengths from 30 to15 nm. A/cm (1 nA/ m) for 20, 25, and 30 nmdevices. From [27].

of about 2 10 cm [48]. Any source–drain doping thatextends beyond this point into the channel tends to compen-sate or counterdope the channel region and aggravate theshort-channel effect. The abruptness requirements of boththe source–drain and the halo doping profiles dictate abso-lutely minimum thermal cycles after the implants. Note thata raised source–drain structure may help making contacts,but does not by itself satisfy the abruptness requirementdiscussed here.

As discussed in Section II-B, a key issue with the highp-type doping level and narrow depletion regions in this25-nm design is the band-to-band tunneling through thehigh-field region between the p-halo and the drain. For thepeak field intensity (1.75 MV/cm) at high drain and zerogate biases shown in Fig. 15, the tunneling current density ison the order of 1 A/cm (Fig. 9). This should not constitutea major component of the device leakage current given thenarrow width of the high-field region, 15 nm according toFig. 15.

The threshold design in Fig. 17 assumes dual n /pSi work function gates for nMOS/pMOS, respectively. Amidgap work function metal gate would clearly result in

Fig. 17. Short-channel threshold rolloff for superhalo andretrograde (nonhalo) doping profiles. Threshold voltage is definedas the gate voltage where A/ m. From [27].

threshold voltage magnitudes far too high for both devices[48]. With doped poly-Si gates, a frequently raised issueis the effect of poly-Si depletion on CMOS performance.Depletion effects occur in polysilicon in the form of athin-space charge layer near the gate oxide interface, whichacts to reduce the gate capacitance and inversion chargedensity for a given gate drive. The percentage of gate ca-pacitance attenuation becomes more significant as the oxidethickness is scaled down. Actually, the net performance lossdue to poly-Si depletion effects is much less severe thanis suggested by – measurements. As it happens, thedelay of intrinsic, unloaded circuits is only slightly degraded( 5%) because although poly-Si depletion causes a loss inthe drive current, it also decreases the charge needed forthe next stage. These two effects tend to cancel each other.For the heavily loaded case in which the devices drive alarge fixed capacitance, the delay degradation approachesthose of the ON currents ( 15%). This can be compensatedto some extent by using wider devices. On the average, theperformance loss due to poly-Si depletion effect is about10% for partially loaded 25-nm CMOS circuits with a1.5-nm-thick oxide [27].

Extensive 3-D statistical simulations have been carried outon the effects of dopant fluctuations on threshold voltage forthe above 25-nm device design [49]. Some of the details arepresented in Section IV-C.

To evaluate the potential ON-state performance of25-nm CMOS, detailed Monte Carlo simulations wereperformed using the simulator DAMOCLES [50]. Both n-and p-channel MOSFETs have been simulated, yieldinglow-output conductance high-performance – charac-teristics for both device types [27]. The transconductanceexceeds 1500 mS/mm for this nFET, with an estimatedhigher than 250 GHz. Transient Monte Carlo simulationswere also done for a three-stage chain of 25-nm CMOS in-verters. Fig. 18 shows the output waveforms. The estimateddelay time is 4–4.5 ps, about three to four times faster than100-nm CMOS operated at 1.5 V.

One way to go beyond 25-nm bulk CMOS is to cool theCMOS chip to low temperatures as discussed in connectionto the 11-nm bulk MOSFET described in Section III. This is

FRANK et al.: DEVICE SCALING LIMITS OF Si MOSFETs AND THEIR APPLICATION DEPENDENCIES 271

FIGURE 4: 25 nm gate length MOSFET (Frank, et al., “Device scaling limits of Si MOSFETs andtheir application dependencies”,Proc. IEEE, 2001).

0.5

0.4

0.3 0.2

0.1

0 - -0.1

-0.2 -0.3

x i = 25 nm I I

20 30 40 50

-0.4

-0.5 10

- v& = 1 .o v -

Lateral S/D gradient:

-

-

d 16 nmldec.

Super-Halo

- - -

Channel Length (nm)

101 ' " " " ' I I 10 100

Dielectric Constant

Fig. 9 Scale length versus dielectric constant for three val- ues of equivalent oxide thickness. Adapted from 171.

Fig. 7 Dependence of short channel effect on lateral doping gradient. From [3].

DoubleGate. V, = 1.0 V

10 100

Electric Field (MVlcm)

Fig. 8 Band-to-band tunneling current density (at 1 V applied) versus electric field. Adapted from [3].

Gate Length (L,,) [nm]

Fig. 10 VT rolloff characteristics of double-gated MOSFETs. From [SI.

Application

Speech recognition (to text)

Real time language translation

Video encoding QClF (174 x 144, 10 fps)

CCIR 601 (720 x 480.30 fps)

Vew hiah res. 1920 x 1200.30 fos)

2-way video wrist watch

PDA

Tablet

Factoring 5 12 bit numbers Deep Blue chess OM-based device simulation

petaFLOPS computing challenges

Table 1. Selected possible applications of 25 nm CMOS technology and their estimated requirements. Power estimates are for general purpose processors (GPP) and special purpose DSP-like processors. Adapted from [ 13.

21

FIGURE 5: Future applications enabled by 25 nm gate length MOSFET (Frank, et al.,DeviceResearch Conference, 1999).

5.4.2 New gate metal

The doped polycrystalline silicon used for gates has a very thin depletion layer, approximately 1nm thick, which causes scaling problems for small devices. Other metals are being investigatedfor replacing the silicon gates, including tungsten and molybdenum.

5-4

l

ll

ll

l

ll

l

ll

ll

ll

l

t

t

t

tt

tt

tt

tt

tt

tt

t

2000 2005 2010 2015 2020

10

20

50

100

Year

feat

ure

size

[nm

]

l polysilicon half-pitch printed gate L

s physical gate L

poly half-pitch

FIGURE 6: The ITRS roadmap for the gate length and polysilicon half-pitch in DRAMs. (ITRS2004 update: http://public.itrs.net/)

5.4.3 Removing the substrate: Silicon on insulator

For high-frequency circuits (about 5 GHz and above), capacitive coupling to the silicon substratelimits the switching frequency. Also, leakage into the substrate from the small devices can causeextra power dissipation. These problems are being avoided by making circuits on insulating sub-strates (either sapphire or silicon dioxide) that have a thin, approximately 100 nm layer of crys-talline silicon, in which the MOSFETs are fabricated.

5.5 The Roadmap

The semiconductor industry collaborates on predicting and determining the future changes to ICtechnology, contained in the International Technology Roadmap for Semiconductors (ITRS). Fig-ure 6 gives an example from the 2004 update for dynamic random access memory (DRAM) MOS-FETs. The gate length is projected to drop below 10 nm in about 10 years.

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