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Lecture 330 – High Speed Comparators (3/28/10) Page 330-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 330 – HIGH SPEED COMPARATORSLECTURE ORGANIZATION
Outline• Speed limitations of comparators• High speed comparators• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 461-464 and 483-487
Lecture 330 – High Speed Comparators (3/28/10) Page 330-2
CMOS Analog Circuit Design © P.E. Allen - 2010
SPEED LIMITATIONS OF COMPARATORSSpeed Limitations of ComparatorsThe speed of a comparator is limited by either:
• Linear response – response time is inversely proportional to the magnitude of poles
060810-01
jω
σIncrease for
speed Increasebandwidth
Gain
ω
vout
VOH
VOL
PropagationTime Delay
t
• Slew rate – delay is proportional to capacitance and inversely proportional tocurrent sinking or sourcing capability
VDD
060810-02
voutCL
ISource
ISink+
−
dvoutdt
= ICL
voutVOH
VOL
PropagationTime Delay
t
Lecture 330 – High Speed Comparators (3/28/10) Page 330-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Maximizing the Linear ResponseConsider the amplifier of Example 270-3 given below:
060711-01
VDD
Vout +−
Vin+
−
Μ1 Μ2Μ3 Μ4Μ5
VNB1
VPB1 VPB1
Μ6
Μ7
I7
I3 I4I5 I6
I1 I2
One stage of this amplifier had a gain of 10 and a dominant pole at 551MHz. Theresponse of this amplifier to a step input is
Vout(t) = 10Vin (1-e-p1t)
If the output signal swing is 1V and the step is 0.1V, the propagation time delay is,
Vin(min) = 1/10 = 0.1V k = 1
tp = 1
p1 ln
2k2k-1 =
12 ·551x106 ln
22-1 = 0.20 ns
Lecture 330 – High Speed Comparators (3/28/10) Page 330-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Trading Speed for Sensitivity (Gain)In the previous example, the gain was too small for good sensitivity. To enhance thesensitivity, cascade three of the gain of 10 stages. The result is,
+
−
+
−
10V/Vp1=551MHz
A1+
−
+
−
10V/Vp1=551MHz
A2+
−
+
−
10V/Vp1=551MHz
A3 VoutVin
The frequency response of this amplifier is,Vout(s)Vin(s) =
1000(1 + s/p1)3
The step response of this amplifier is
vout(t) = Ao2 Vinp13t2e-p1t
Ao2 Vinp13t2[1 - p1t + p12t2 - ···]
Ao2 Vinp13t2 if p1t<1
The propagation delay time is
tp2 = VOH-VOL
Ao
1Vinp13 =
1kp13 tp = 0.0049 ps if k = 1
The speed of the amplifier will be limited by the slew capability!
Lecture 330 – High Speed Comparators (3/28/10) Page 330-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Maximizing Speed for Slew Rate LimitationThe key is to make the sourcing/sinking current large and the capacitance small.Best possible sinking/sourcing circuit in CMOS is:
VDD
060810-03
vIN vOUT
M1
M2
CL
ISource
ISink
Assuming a W/L ratio of 42 for M1 and 200 for M2, if the input can swing to VDD(=2.5V) and ground, the sourcing and sinking currents are:
ISourcing = Kp'W
2L (VDD – |VTP|)2 = 25·200
2 (2.5V-0.5)2 μA = 10.0 mA
ISinking = Kn'W
2L (VDD – VTN)2 = 120·42
2 (2.5V-0.5)2 μA = 10.1 mA
If larger currents are required, cascaded stages can be used to optimize the delay versusthe current output.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Driver Delay of a Push-Pull InverterIf too much current is required, the device sizes become large and the driver delay
increases. For the previous example, the input capacitance for the driver assuming Cox
6fF/μm2 and the channel lengths are 0.5μm, is,Cin = Cgs1 + Cgs2 = 2·(2/3) Cox(W1L1 + W2L2)
= 1.33·6fF/μm2(121μm2) = 0.968 pF
M1
M2200µm 0.5µm
42µm0.5µm
CLoadCin
Driver
070510-02
If the effective resistance of the driver is 30k , then the delay is 29 ns which is much toolarge.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Optimizing the Delay of a Chain of Push-Pull InvertersFor a series of N inverters as shown below, the W/L is increased by a factor of f for eachsucceeding stage.
Cin
W/L = 1
CLoad = fNCin
f f 2 f N-2 f N-1
070510-01
From the above figure we see that CLoad = f NCin _ N = ln(CLoad /Cin)
ln f
The delay of a single, push-pull inverter can be expressed as,
tinv = inv
CjCj-1 + inv
where
inv = ReffCin (Reff is the effective output resistance of the inverter)
inv = CselfCin
= Cjunction
Cin(Cjunction is the bulk-drain capacitances)
Lecture 330 – High Speed Comparators (3/28/10) Page 330-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Optimizing the Delay of a Chain of Push-Pull Inverters – ContinuedThe total delay of the chain of inverters is
ttotal = N inv
CjCj-1 + inv
Setting f = Cj
Cj-1 gives
ttotal = ln(CLoad /Cin)
ln f inv (f + inv)
Plotting the total delay versus f for various values of inv shows that the optimum value off lies in the range of 2.5 to 4†.
† D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd ed., McGraw-
Hill Book Co., 2004, Chapter 6.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 330-1 – Finding the Optimum Delay for a Chain of InvertersAssume that CLoad is 5pf, Cin = 50fF, inv = 10ps , and inv = 0.5. If f = 3.6, find theoptimal number of stages and the total delay of this chain of inverters.Solution
From above we get the optimal number of stages as,
N = ln(CLoad /Cin)
ln f =
ln(100)ln 3.6
= 3.59
If we choose N = 4, then f can be recomputed as
ln f = 1
4 ln(100) f = 3.16
The total delay is,
ttotal = N inv
CjCj-1 + inv = 4·10ps(3.16 + 0.5) = 146ps
Lecture 330 – High Speed Comparators (3/28/10) Page 330-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Self-Biased Differential Amplifier†
Not as good as the push-pull inverter but interesting.
Advantage:Large sink or source current with out a large quiescent current.
Disadvantage:Poor common mode range (vin+ slower than vin-)
† M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.1991, pp. 165-168.
M1 M2
M3 M4
M6
M5
VDD
VSS
vin+ vin-vout
M3 M4
M6
VDD
M1 M2
M5
VSS
vin+ vin-
VBias
VBias Extremelylarge sourcingcurrent
Fig. 8.3-4
Lecture 330 – High Speed Comparators (3/28/10) Page 330-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage Comparator with Increased SpeedClamp the input stage with 1/gm loads to decrease the signal swing and avoid slew ratelimitation in the first stage.
060808-06
Metal
vnM1 M2
M3
M4
M5
M6
vout
VDD
VBias+
-
CL
M9
M8
M7
vp
Comments:• Gain reduced Larger input resolution• Push-pull output Higher slew rates• Can increase the current drive by cascading the output stage
Lecture 330 – High Speed Comparators (3/28/10) Page 330-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Comparators that Can Drive Large Capacitive Loads
060808-08
vnM1 M2
M3 M4
M5
M6
M7
vout
VDD
VNB1+
-
CL
M8
M9
M10
M11
vp
Comments:• Slew rate = 3V/μs into 50pF• Linear rise/fall time = 100ns into 50pF• Propagation delay time 1μs• Loop gain 32,000 V/V• The quiescent dc currents in the output stages are not well defined• Use the principle of optimizing the delay in cascaded inverters
Lecture 330 – High Speed Comparators (3/28/10) Page 330-13
CMOS Analog Circuit Design © P.E. Allen - 2010
HIGH SPEED COMPARATORSA Study in ExponentialsThe step response of an amplifier with a gain of Ao and a dominant pole at A is,
vout(t) = Ao[1 – exp(- At)] Vin
060810-04t
vout
AoVin
0Fast rising
Slow rising
The latch response to a step input of Vin is,
vout(t) = Vin expt
tL
060810-05t
vout
2.72Vin
0
Fast rising
Slow rising
τL
Lecture 330 – High Speed Comparators (3/28/10) Page 330-14
CMOS Analog Circuit Design © P.E. Allen - 2010
A High-Speed Comparator ArchitectureCascade an amplifier with a latch to take advantage of the exponential characteristics ofthe previous slide.
060810-06
Preamplifier
Latch+
−Vin Vo1
+
−
+
−VoutAo
In order to keep the bandwidth of the amplifier large, the gain will be small. To achieve
060810-08
Preamplifier n
Latch+
−Von
+
−
+
−Vout
+
−
Preamplifier 1
+
−Vin
Preamplifier 2
Vo1
+
−Vo2 Von-1Ao
1/n Ao1/n Ao
1/n
Gain = Ao
Therefore, the question is how many stages of the amplifier and what is the gain of eachstage for optimum results?
Lecture 330 – High Speed Comparators (3/28/10) Page 330-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Ex. 330-2 – Optimizing the Propagation Time DelayA comparator consists of an amplifier cascaded with a latch as shown below. Theamplifier has a voltage gain of 10V/V and f-3dB = 100MHz and the latch has a time constantof 1ns. The maximum and minimum voltage swings of the amplifier and latch are VOH andVOL. When should the latch be enabled after the application of a step input to the amplifierof 0.05(VOH-VOL) to get minimum overall propagation time delay? What is the value of theminimum propagation time delay?
vin = 0.05(VOH-VOL) voutAmplifierAv(0)=10V/V
f-3dB=100MHz
LatchτL=1ns
Comparator
voa
vil
Enable
t=0
070606-01
SolutionThe solution is based on the figure shown.We note that,
voa(t) = 10[1-e- -3dBt]0.05(VOH-VOL).If we define the input voltage to the latch as,
vil = x·(VOH-VOL) then we can solve for t1 and t2 as follows:
VOH
VOL
Amplifier
Latch
t1
x(VOH-VOL)
t2t
S01E3S1
Lecture 330 – High Speed Comparators (3/28/10) Page 330-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 330-2 - Continuedx·(VOH-VOL) = 10[1-e- -3dBt1]0.05(VOH-VOL) x = 0.5[1-e- -3dBt1]
This gives,
t1 = 1-3dB
ln 1
1-2x
From the propagation time delay of the latch we get,
t2 = L ln VOH-VOL
2vil = L ln
12x
tp = t1 + t2 = 1-3dB
ln 1
1-2x + L ln 12x
dtp
dx = 0 gives
2x = 2 L -3dB
2+2 L -3dB =
0.42+0.4 = 0.3859 (x = 0.1930)
t1 = 10ns2 ln
11-0.3859 = 1.592ns·0.4875 = 0.7762 ns
and t2 = 1ns ln 1
0.3859 = 0.9522ns
tp = t1 + t2 = 0.776 ns + 0.952 ns = 1.728 ns
Lecture 330 – High Speed Comparators (3/28/10) Page 330-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Minimizing the Propagation Delay Time in ComparatorsFacts: • The input signal is equal to Vin(min) for worst case
• Amplifiers have a step response with a negative argument in the exponential • Latches have a step response with a positive argument in the exponential • If the amplifiers rise too quickly, they will be slew limitedApproach: • Use a cascade of low-gain, wide-bandwidth amplifiers to take a small input signal and
amplify it without suffering slew limit • Use a latch to take the amplified input and quickly reach 0.5(VOH-VOL)
Lecture 330 – High Speed Comparators (3/28/10) Page 330-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Minimization of the Propagation Delay TimeMinimization of tp:
Q. If the preamplifer consists of n stages of gain A having a single-pole response, what isthe value of n and A that gives minimum propagation delay time?A. n = 6 and A = 2.62 but this is a very broad minimum and n is usually 3 and A 6-7to save area.
070509-06
Preamplifier 3
Latch−
Vo3
+
−
+
−Vout
+
−
Preamplifier 1
+
−Vin
Preamplifier 2
Vo1
+Vo2Ao
1/3 Ao1/3 Ao
1/3
Gain = Ao
Lecture 330 – High Speed Comparators (3/28/10) Page 330-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Fully Differential, Three-Stage Amplifier and Latch ComparatorCircuit:
060810-08
+
- +
-
FB
FB
Reset
Cv1
Cv2
+
- +
-
FB
FB
Reset
Cv3
Cv4
+
- +
-
FB
FB
Cv5
Cv6
vout
+
-
Clock
+vin -
FB
FB
FB
FB
Reset
FB
FB Latch
Sample
Reset
Sample
Comments:• Autozero and reset phase followed by comparison phase• In the autozero phase, switches labeled “Reset” and “FB” are closed.
• In the sample phase, switches labeled “Sample” and “ FB ” are closed.
• Can run as high as 200Msps
Lecture 330 – High Speed Comparators (3/28/10) Page 330-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Preamplifier and Latch CircuitsGain:
Av = - gm1gm3
= - gm2gm4
= - KN’(W1/L1)Kp’(W3/L3)
Dominant Pole:
|pdominant| = gm3C =
gm4C
where C is the capacitance seen from theoutput nodes to ground.
If (W1/L1)/(W3/L3) = 100 and thebias current is 100μA, then A = -3.85and the bandwidth is 15.9MHz if C =0.5pF.Comments:• If a buffer is used to reduce the output
capacitance, one must take into account the loss of the buffer.• The use of a preamplifier before the latch reduces the latch offset by the gain of the
preamplifier so that the offset is due to the preamplifier only.
VDD
VBias
FB
FB
Reset
LatchEnable
M1
M2
M3 M4
M5 M6
Q
Q
Preamplifier Latch
Fig. 8.6-4
Lecture 330 – High Speed Comparators (3/28/10) Page 330-21
CMOS Analog Circuit Design © P.E. Allen - 2010
An Improved PreamplifierCircuit:
VDD
M1 M2
M3 M4M5 M6
M7 M8M10
M9
M11 M12
VBiasN
VBias
VBiasP VBiasP
vout+vout-
vin+ vin-
FB FB
Reset
Fig. 8.6-5
Gain:
Av = - gm1gm3
= - KN’(W1/L1)I1KP’(W3/L3)I3 = -
KN’(W1/L1)KP’(W3/L3) 1+
I5I3
If I5 = 24I3, the gain is increased by a factor of 5
Lecture 330 – High Speed Comparators (3/28/10) Page 330-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Improved Frequency Response of the AmplifierIf the ratio of transconductance W/L is much larger than the load W/L, the frequency
response will suffer. Using the technique of the previous slide, we can keep the ratio ofthe W/Ls to a more reasonable value. The result is higher frequency response.Amplifier of Example 270-3:
060711-01
VDD
Vout +−
Vin+
−
Μ1 Μ2Μ3 Μ4Μ5
VNB1
VPB1 VPB1
Μ6
Μ7
I7
I3 I4I5 I6
I1 I2
Gain = 20dBf-3dB = 551MHz
Lecture 330 – High Speed Comparators (3/28/10) Page 330-23
CMOS Analog Circuit Design © P.E. Allen - 2010
High-Speed CMOS ComparatorThe comparator used in a 12-bit, 200 Msps ADC is shown below†. The comparator isused in each of the 4-bit pipeline stages which requires 15 comparators.The comparators consist of three stages including (a.) differential input pairs, (b.) a cross-coupled latch, and (c.) an SR latch to hold the comparator output until the next clockcycle.
Vref1
vin1 vin2
Vref2VNB1
iout1
iout2
iin1iin2
VDD
φ1φ1
φ1
φ2
vout1
vout2
VDD
S
R Q
Q
NMOS Input Pair Latch SR-Latch 070511-01
† T. Liechti, “Design of a High-Seed 12-bit Differential Pipelined A/D Converter,” Diploma Project, Feb. 2004, Microelectronic Systems Laboratory,Swiss Federal Institute of Technology, Lausanne.
Lecture 330 – High Speed Comparators (3/28/10) Page 330-24
CMOS Analog Circuit Design © P.E. Allen - 2010
High Speed CMOS Comparator – ContinuedSchematic of the fully differential comparator:
Clock waveforms:
Mean comparator powerdissipation is 140μWunder typical conditions
Lecture 330 – High Speed Comparators (3/28/10) Page 330-25
CMOS Analog Circuit Design © P.E. Allen - 2010
High Speed CMOS Comparator – ContinuedTransistor sizes:Transistor M0a,
M0b,M0c,M0d
M1a,M1b
M2a,M2b,M2c,M2d
M3a,M3b
M4a,M4b
M5a,M5b
M6a,M6b
M7 M8a,M8b
M9a,M9b
M10a,M10b
M11aM11b
W(μm) 1.5 6 3.6 3 1 1 0.24 0.5 2 2.5 3 0.24L(μm) 1 2.5 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18
Comparator offsets (worst case):
Lecture 330 – High Speed Comparators (3/28/10) Page 330-26
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Comparators are limited in speed either by bandwidth or slew rate• Increasing the magnitude of the poles improves the bandwidth limitations• Increasing the current sinking/sourcing ability improves the slew rate limitation• Most high speed comparators use a combination of preamplifier followed by a latch
- The preamplifier uses bandwidth to quickly build up the input- The latch uses positive feedback to take the signal to its final state