Lecture 3 - Politechnika Śląskadb.zmitac.aei.polsl.pl/KT/Lecture3.pdf · 2003-10-24 · • Implemented for compatibility with 8086 processor. Real-address model Offset Linear address

Assembler Programming

Lecture 3

Lecture 3

• Memory models. I/O addressing. Interrupts and exclusions. Data types. Format of theinstruction.

Memory models• Physical memory:

– memory that processor addresses on its bus,– organized as a sequence of bytes.

• Linear memory:– memory appeared to a program as a single,

continuous address space.• Three memory models:

– flat,– segmented, – real-address mode.

Segmented model

• Memory is divides into segments.• Code, data and stack are separated.• Logical address:

– segment selector,– displacement – offset.

• Up to 16383 segments of 4G size each.• Logical address is translated into a linear

address.

Segmented model

Offset

SegmentsLinear address space

Logical address

Segment selector

Flat model

• Flat model operates directly on linear addressspace.

• Single continuous address space of 4G size.

Flat modelLinear address space

Linear address

Real-address model

• Segments of up to 64KB each.• Maximum size of linear space is 1MB.• Implemented for compatibility with 8086

processor.

Real-address model

Offset

Linear address space

Logical address

Segment selector

I/O addressing

• Two concepts of I/O addressing– separate I/O and memory addressing space– memory mapped I/O addressing

• PC computers have separate addressing spaces– 64k 8-bit ports in I/O space– ports can be also 16 or 32-bit– direct addressing or indirect addressing using

register

direct I/O addressing

AX

AL one byteout 080h, al

low byte

high byte

080h

in ax, 060h

060h061h

Indirect I/O addressing

DX

ALdatain al, dx

Interrupts• Interrupt is the event caused usually by the I/O

device external to the processor.• Interrupt is signaled with the special signal.• Interrupt is handled by operating system or

user’s subroutine.

Exceptions• Exception is the event caused usually by the

software in cases of errors.• Exception can be signaled internally within

processor.• Exception is usually handled by the operating

system.

Interrupt handling

• Interrupts are handled by the subroutines.• While interrupt occurs the processor:

– stops executing actual program– pushes actual value of the flags register– pushes address of next instruction on the stack– calls the interrupt subroutine (handler)

• when subroutine is finished – returns to stopped program popping actual address

from the stack– pops the flags register

Interrupt handling

InterruptInterrupthandler

Program

Fundamental data types

Word

Byte

Doubleword

Quadword

Double quadword

07

15

31

63

127

0

0

0

0

Data storing

byte at address 9hcontaining 1Fh

36h

A4h23h

1Fh

7AhFEh06h

CBh31h

0Bh

74h

FhEhDhChBhAh9h8h7h6h5h4h3h2h1h0h

word at address 2hcontaining 74CBh

doubleword at address Ahcontaining 7AFE0636h

word at address 1hcontaining CB31h

quadword at address 6hcontaining

7AFE06361FA4230Bh

Integer data types

Word

Byte

Doubleword

Quadword

07

15

31

63

0

0

0

Word

Byte

Doubleword

Quadword

06

15

30

63

0

0

0

Unsigned types

Signed types

62

31

14

7

Floating point data types

31

63

0

0

Double extendedprecision

Single precision

Double precision

30 23 22

62 52 51

63 06279 64

BCD data types

BCD

03

BCD Integer

79 0

47

BCD

03

BCD

47

Packed BCD Integer

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17

7180-bit packed BCD Integer

Pointers

Offset

Segment Offset

Near Pointer

Far Pointer

Format of the instruction

• Instruction prefix• Opcode• MODR/M byte• SIB byte (Scale Index Base byte)• Displacement• Immediate data

ImmediateDisplacementSIBModR/MOpcodePrefix

Prefix – Group1ImmediateDisplacementSIBModR/MOpcodePrefix

• Up to four prefixes of one byte each.• Group1 – lock and repeat prefixes.

– F0h – LOCK– F2h – REPNE/REPNZ (string instructions)– F3h – REP (string instructions)– F3h – REPE/REPZ (string instructions)– F3h – Streaming SIMD Extensions

Prefix – Group2ImmediateDisplacementSIBModR/MOpcodePrefix

• Segment override prefixes.– 2Eh – CS segment override– 36h – SS segment override– 3Eh – DS segment override– 26h – ES segment override– 64h – FS segment override– 65h – GS segment override

• Branch hints– 2Eh – branch not taken– 3Eh – branch taken

Prefix – Group3 and Group4ImmediateDisplacementSIBModR/MOpcodePrefix

• Group3 - Operand size override prefix.– 66h – overrides the default size of the operand

• Group4 – Address size override prefix.– 67h – overrides the default size of the address

Format of the instructionImmediateDisplacementSIBModR/MOpcodePrefix

• Opcode is one or two byte length.• Optional additional 3-bit field in ModR/M byte.


• Mod - Mode. This 2-bit field gives the register/memory mode with displacement.

• Reg - Register. This 3-bit field specifies one of the general-purpose registers.

• R/M - Register/memory. This 3-bit field specifies a register or memory r/m operand.

R/MReg/OpcodeMod


R/MReg/OpcodeMod

001000001000

R/M

001000001000

ECX/CX/CL/MM1/XMM111EAX/AX/AL/MM0/XMM011[BX+DI]+disp1610[BX+SI]+disp1610[BX+DI]+disp801[BX+SI]+disp801[BX+DI]00[BX+SI]00operandMod


R/MReg/OpcodeMod

DI111SI110BP101SP100BX011DX010CX001AX000registerreg


• Byte SIB is used only in 32-bit mode.• Scale - This two-bit field specifies the scaling

factor.• Index - This three-bit field specifies one of the

index registers.• Base - This 3-bit field specifies the base

register.

BaseIndexScale


BaseIndexScale

000011111011111011011011Base

000000100000

Index

001000001000

[EAX][EAX*8]11[EBX][EAX*8]11[EDI] (index=none)10[EBX][EAX*4]10[EDI][ECX*2]01[EBX][EAX*2]01[EBX][ECX]00[EBX][EAX]00operandScale


• Displacement gives the offset for memory operands.

• It can be 0,1,2 or 4 bytes long.


• Immediate gives the actual value for constants.• It can be 0,1,2 or 4 bytes long.

Example of the instruction

ImmediateDisplacementSIBModR/MOpcodePrefix

mov EBX,[EAX+EAX*2+1000]

E8 03 00 00409C8B67 66

• 67 – Address size override• 66 – Operand size override• 8B – Opcode

– mov r16, r/m16• 9C – 10 011 100

– 10 – mod: disp32– 011 – reg: EBX– 100 – r/m: SIB byte is

present

• 40 – 01 000 000– 01 – scale: *2– 000 – index: EAX– 000 – base: EAX

• E8 03 00 00 – displacement(000003E8 = 1000)

• No immediate• In 32-bit mode there are no

prefixes

Documents

Lecture 3 - Politechnika Śląskadb.zmitac.aei.polsl.pl/KT/Lecture3.pdf · 2003-10-24 · • Implemented for compatibility with 8086 processor. Real-address model Offset Linear address