Lecture 17 MOS Transistors

8/10/2019 Lecture 17 MOS Transistors

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Basic MOS Device Physics

Lecture 17

MSE 515


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Topics

MOS Structure

MOS IV Characteristics

CCD


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Revolution and Evolution in Electronics

Source: IntelSource: Intel

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Source: IntelSource: Intel

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100,000100,000

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NMOS Structure

LDis caused by side diffusion

Source: the terminal that providescharge carriers.(electrons in NMOS)

Drain: the terminal that collectscharge carriers.

Substrate contact--toreverse bias the pn junctionConnect to most negative supply voltage

in mostcircuits.


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Although no current should ideally conduct before threshold, a small

percentage of electrons with energy greater than or equal to a few kT havesufficient energy to surmount the potential barriers!

Subthreshold Characteristics

Short-Channel MOSFETs

As a result, there is a slight amount of current conduction below VT


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Potential contours in a long channel MOSFET.

In a long channel MOSFET,

the potential is uniform andparallel to the gate.



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Narrow Width Effect

If the Polysilicon gate is atop the region of a LOCOS isolation where the oxide isincreasing in thickness.

It is possible to form a channel under LOCOS away from the thin gate oxide!This is quite important for devices with L < 1 m.



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CMOS Structure

PMOSNMOS

Reverse bias the pnjunction

Reverse bias the pnjunction

Connect to most positive

supply voltage in mostcircuits.


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MOS IV Characteristics

Threshold Voltage

Derivation of I/V Characteristics

I-V curve

Transconductance

Resistance in the linear region

Second Order Effect

Body Effect

Channel Length Modulation

Subthreshold conduction


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Threshold Voltage

1. Holes are expelled from the gate area2. Depletion region (negative ions) is

created underneath the gate.

3. No current flows because no chargecarriers are available.


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MOSFET as a variable resistor

The conductive channel between S and D can be viewed

as resistor, which is voltage dependent.


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Threshold Voltage (3)

When the surface potential increases to acritical value, inversionoccurs.1. No further change in the width of the

depletion region is observed.2. A thin layer of electrons in the depletion

region appear underneath the oxide.3.

A continuous n-type (hence the nameinversion) region is formed between thesource and the drain. Electrons can nobe sourced from S and be collected atthe drain terminal. (Current, however,

flows from drain to source)4. Further increase in VG will fruther incrase

the charge density.

The voltage VG required to provide an

inversion layer is called the thresholdvoltage.


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Implantation of p+ dopants toalter the threshold

Threshold voltage can be adjusted by implantingDopants into the channel area during fabrication.

E.g. Implant p+ material to increase threshold voltage.


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Formation of Inversion Layer in aPFET

The VGS must be sufficient

negative to produce an inversionlayer underneath the gate.


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I-V Characteristics


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Channel Charge

A channel is formed when VGis increased to the point

that the voltage difference between the gate andthe channel exceeds VTH.


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Application of VDS

What happens when you introduce a voltage at the drain terminal?


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Channel Potential Variation

VXthe voltage along the channel

VXincreases as you move from S to D.

VG-VXis reduced as youmove from S to D.

E.g. VS=0, VG=0.6, VD=0.6At x=0, VG-VX=0.6 (more than VTH)At x=L, VG-VX=0 (less than VTH)


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Pinch Off

Small VDS

Large VDS

No channel

Electrons reaches the D

via the electric field in thedepletion region

SaturationRegion

LinearRegion


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MOSFET as a controlled linearresistor

1. Take derivative of IDwith respect to V

DS

2. For small VDS, the drain resistance is


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Transistor in Saturation Region

I-V characteristics

Transconductance

Output resistance Body transconductance


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Saturation of Drain Current


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Transconductance

Analog applications:How does Idsrespond to changes in VGS?


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IDS vs VGS

0.13 um NMOSVDS=0.6 VW/L=12um/0.12 umVB=VS=0

Y axis: IdsX axis: Vgs


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Different Expressions ofTransconductance


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Channel Length Modulation

As VDS increases, L1 will move towards the source, sincea larger VDSwill increase VX .

L is really L1

ID will increase as VDS increases.The modulation of L due to VDSis called channel length modulation.


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Controlling channel modulation

For a longer channel length, the relative change in L andHence ID for a given change in VDS is smaller.

Therefore, to minimize channel length modulation, minimum

length transistors should be avoided.


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Output resistance due to gds


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MOS Device Layout


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MOS Capacitances

D t t l


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Detector zoology

X-ray Visible NIR MIR

[m]

Silicon CCD & CMOS

0.3 1.10.9 2.5 5 20

HgCdTe

InSb

STJ

0.1

Si:As

In this course, we concentrate on 2-D focal plane arrays. Optical silicon-based (CCD, CMOS) Infrared IR material plus silicon CMOS multiplexer

Will not address:APD (avalanche photodiodes)STJs (superconducting tunneling junctions)


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Step 2: Charge Generation

Silicon CCD

Similar physics for IRmaterials


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CCD Introduction

A CCD is a two-dimensional array of metal-oxide-semiconductor (MOS) capacitors.

The charges are stored in the depletion region ofthe MOS capacitors.

Charges are moved in the CCD circuit bymanipulating the voltages on the gates of thecapacitors so as to allow the charge to spill fromone capacitor to the next (thus the namecharge-coupleddevice).

An amplifier provides an output voltage that canbe processed.

The CCD is a serial device where charge packetsare read one at a time.


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Potential in MOS Capacitor


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CCD Phased Clocking:Summary


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1

2

3

CCD Phased Clocking: Step 3

+5V

0V

-5V

+5V

0V

-5V

+5V

0V

-5V

1

2

3


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CCD output circuit


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Charge Transfer Efficiency

When the wells are nearly empty, charge can be trapped byimpurities in the silicon. So faint images can have tails in thevertical direction.

Modern CCDs can have a charge transfer efficiency (CTE) pertransfer of 0.9999995, so after 2000 transfers only 0.1% of thecharge is lost.

good CTE bad CTE


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Threshold Voltage

VG=0.6 V

VD=1.2 V

CMOS: 0.13 um

W/L=12um/0.12 um NFET


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I-V characteristic Equation forPMOS transistor


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More on Body Effect

Example

Analysis

gmbs


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Variable S-B Voltage

constant


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gm as function of region

saturation

0.13 um NMOSVGS=0.6 VW/L=12um/0.12 um

VB=VS=0Y axis: gmX axis: vds

linear


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gds

saturation

0.13 um NMOSVGS=0.6 VW/L=12um/0.12 um

VB=VS=0Y axis: gmX axis: vds

linear

Slope due tochannel lengthmodulation


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Body Effect

The n-type inversion layer connects the source to the drain.The source terminal is connected to channel. Therefore,

A nonzero VSB introduces charges to the Cdep.The math is shown in the next slide.

A nonzero VSB for NFET or VBS for PFET has the net effectOf increasing the |VTH|

E i t l D t f B d


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Experimental Data of BodyEffect


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W/L=12 um/0.12umCMOS: 0.13 um processVDS=50 mVSimulator: 433 mVAlternative method: 376 m


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Subthreshold current

Subtresholdregion

As VG increases, the surfacepotential will increase.

There is very little majority carriers

underneath the gate.

There are two pn junctions. (B-S and B-D)

The density of the minority carrierdepends on the difference in the

voltage across the two pn junction diode.

A diffusion current will result the electron densities

at D and S are not identical.

Conceptual Visualization of


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Conceptual Visualization ofSaturation and Triode(Linear)

Region

NMOS

PMOS

I V Ch t i ti E ti f


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I-V Characteristic Equations forNMOS transistor

(Triode Region:VDSVGS-VTH

To produce a channel (VGS>VTH)


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VTHas a function of VSB

(VTH0: with out body effect)

Body effect coefficient

VSB dependent


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Sensitivity of IDSto VSB

(chain rule)

gm

=1/3 to 1/4, bias dependent


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Bias dependent CGSand CGD

C l t NMOS S ll Si l


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Complete NMOS Small SignalModel

C l t PMOS S ll Si l


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Complete PMOS Small SignalModel

Transcond ctance in the triode


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Transconductance in the trioderegion

(Triode region)

For amplifier applications, MOSFETs are biased in saturation


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Small signal model of an NMOS


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Small Signal Model

If the bias current and voltages of aMOSFET are only disturbed slightly bysignals, the nonlinearamd largesignal

model an be reduced to linearandsmallsignal representation.

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Lecture 17 MOS Transistors