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Lecture 12 PicoBlaze Overview. ECE 448 – FPGA and ASIC Design with VHDL. Required reading. P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, PicoBlaze Overview Chapter 15, PicoBlaze Assembly Code Development. Recommended reading. - PowerPoint PPT Presentation
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ECE 448 – FPGA and ASIC Design with VHDL
Lecture 12
PicoBlaze Overview
2ECE 448 – FPGA and ASIC Design with VHDL
Required reading• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 14, PicoBlaze Overview
Chapter 15, PicoBlaze Assembly Code Development
Recommended readingPicoBlaze 8-bit Embedded Microcontroller User Guide
for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs
(search for it using Google or Xilinx website documentation search)
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Block diagram of a Single-Purpose Processor (FSMD – Finite State Machine with Datapath)
ECE 448 – FPGA and ASIC Design with VHDL
ctrl
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Block diagram of a General-Purpose Processor (Microcontroller)
ECE 448 – FPGA and ASIC Design with VHDL
5ECE 448 – FPGA and ASIC Design with VHDL
PicoBlaze
PicoBlaze Overview
Register File of PicoBlaze
0
1
7
77
00
0
Address
7 0
7 0
7 07 0
7 0
16 Registers
8-bit
7 0F
s0s1s2s3s4s5s6s7
234567
sf
Definition of Flags
Z = 1 if result = 0 0 otherwise
Zero flag - Z zero condition
Example*
C = 1 if result > 28-1 or
result < 0
0 otherwise*Applies only to addition or subtraction related instructions,
refer to following slides otherwise
Carry flag - C overflow, underflow, or various conditions
Flags are set or reset after ALU operations
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Interface of PicoBlaze
ECE 448 – FPGA and ASIC Design with VHDL
KCPSM = constant (K) coded programmable state machine
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Interface of PicoBlaze
ECE 448 – FPGA and ASIC Design with VHDL
Name Direction Size Functionclk input 1 System clock signal.
reset input 1 Reset signal.
address output 10 Address of the instruction memory.Specifies address of the instruction to be retrieved.
instruction input 18 Fetched instruction.
port_id output 8 Address of the input or output port.
in_port input 8 Input data from I/O peripherals.
read_strobe output 1 Strobe associated with the input operation.
out_port output 8 Output data to I/O peripherals.
write_strobe output 1 Strobe associated with the output operation.
interrupt input 1 Interrupt request from I/O peripherals.
interrupt_ack output 1 Interrupt acknowledgment to I/O peripherals
11ECE 448 – FPGA and ASIC Design with VHDL
Development
Flow of a
System
with PicoBlaze
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PicoBlaze Programming Model
ECE 448 – FPGA and ASIC Design with VHDL
Syntax and Terminology
Syntax Example Definition
sX
KK
PORT(KK)
PORT((sX))
RAM(KK)
s7
ab
PORT(2)
PORT((sa))
RAM(4)
Value at register 7
Value ab (in hex)
Input value from port 2
Input value from port specified by register a
Value from RAM location 4
Addressing modes
Direct mode
INPUT s5, 2a
ADD sa, sf
PORT(2a) s5
sa + sf sa
Indirect modeINPUT s9, (s2)
STORE s3, (sa)
PORT((s2)) s9
s3 RAM((sa))
s2 + 08 + C s2
s7 – 7 s7
Immediate mode
ADDCY s2, 08
SUB s7, 7
PicoBlaze ALU Instruction Set Summary (1)
PicoBlaze ALU Instruction Set Summary (2)
PicoBlaze ALU Instruction Set Summary (3)
Logic instructions1. AND AND sX, sY
sX and sY => sX AND sX, KK
sX and KK => sX
2. OR OR sX, sY
sX or sY => sX OR sX, KK
sX or KK => sX
3. XOR XOR sX, sY
sX xor sY => sX XOR sX, KK
sX xor KK => sX
IMM, DIR
C Z
IMM, DIR
IMM, DIR
0
0
0
Arithmetic Instructions (1)
Addition
ADD sX, sY
sX + sY => sX
ADD sX, KK
sX + KK => sX
ADDCY sX, sY
sX + sY + CARRY => sX
ADDCY sX, KK
sX + KK + CARRY => sX
IMM, DIR
C Z
Arithmetic Instructions (2)
SubtractionSUB sX, sY
sX – sY => sX
SUB sX, KK
sX – KK => sX
SUBCY sX, sY
sX – sY – CARRY => sX
SUBCY sX, KK
sX – KK – CARRY => sX
IMM, DIR
C Z
Test and Compare Instructions
TEST TEST sX, sY
sX and sY => none
TEST sX, KK
sX and KK => none
COMPARE COMPARE sX, sY
sX – sY => none
COMPARE sX, KK
sX – KK => none
C ZIMM, DIR
IMM, DIR
C = odd parity of
the result
Data Movement Instructions (1)
LOAD
LOAD sX, sY
sY => sX
LOAD sX, KK
KK => sX
IMM, DIRC Z
- -
FETCH
FETCH sX, KK
RAM(KK) => sX
FETCH sX, (sY)
RAM((sY)) => sX
Data Movement Instructions (2)
DIR, IND
C Z
- -STORE
STORE sX, KK
sX => RAM(KK)
STORE sX, (sY)
sX => RAM((sY))
DIR, IND
- -
Data Movement Instructions (3)
INPUT
INPUT sX, KK
sX <= PORT(KK)
INPUT sX, (sY)
sX <= PORT((sY))
OUTPUT
OUTPUT sX, KK
PORT(KK) <= sX
OUTPUT sX, (sY)
PORT((sY)) <= sX
DIR, IND
DIR, IND
C Z- -
- -
Edit instructions - Shifts
*All shift instructions affect Zero and Carry flags
Edit instructions - Rotations
*All rotate instructions affect Zero and Carry flags
Program Flow Control Instructions (1)
JUMP AAA
PC <= AAA
JUMP C, AAA
if C=1 then PC <= AAA else PC <= PC + 1
JUMP NC, AAA
if C=0 then PC <= AAA else PC <= PC + 1
JUMP Z, AAA
if Z=1 then PC <= AAA else PC <= PC + 1
JUMP NZ, AAA
if Z=0 then PC <= AAA else PC <= PC + 1
Program Flow Control Instructions (2)
CALL AAA
TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA
CALL C | Z , AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1
CALL NC | NZ , AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1
Program Flow Control Instructions (3)
RETURN
PC <= STACK[TOS] + 1; TOS <= TOS - 1
RETURN C | Z if C | Z =1 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1
RETURN NC | NZ if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1
Subroutine Call Flow
Interrupt Related InstructionsRETURNI ENABLE
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 1; C<= PRESERVED C; Z<= PRESERVED Z
RETURNI DISABLE
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 0; C<= PRESERVED C; Z<= PRESERVED Z
ENABLE INTERRUPT
I <=1;
DISABLE INTERRUPT
I <=0;
Interrupt Flow
ECE 448 – FPGA and ASIC Design with VHDL
33
PicoBlaze Development Environments
ECE 448 – FPGA and ASIC Design with VHDL
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KCPSM3 Assembler Files
ECE 448 – FPGA and ASIC Design with VHDL
35
Directives of Assembly Language
ECE 448 – FPGA and ASIC Design with VHDL
Equating symbolic name
for an I/O port ID.
keyboard DSIN $0E
switch DSIN $0F
LED DSOUT $15
N/A
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Differences between Mnemonics of Instructions
ECE 448 – FPGA and ASIC Design with VHDL
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Differences between Mnemonics of Instructions
ECE 448 – FPGA and ASIC Design with VHDL
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Differences between Programs
ECE 448 – FPGA and ASIC Design with VHDL
