21
ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview

Lecture 12 PicoBlaze Overview

  • Upload
    naeva

  • View
    67

  • Download
    1

Embed Size (px)

DESCRIPTION

Lecture 12 PicoBlaze Overview. ECE 448 – FPGA and ASIC Design with VHDL. Required reading. P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, PicoBlaze Overview. Recommended reading. K. Chapman , PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6). - PowerPoint PPT Presentation

Citation preview

Page 1: Lecture 12 PicoBlaze Overview

ECE 448 – FPGA and ASIC Design with VHDL

Lecture 12

PicoBlaze Overview

Page 2: Lecture 12 PicoBlaze Overview

2ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• P. Chu, FPGA Prototyping by VHDL Examples

Chapter 14, PicoBlaze Overview

Recommended reading

• K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and

7-Series (KCPSM6)

Page 3: Lecture 12 PicoBlaze Overview

3

Block diagram of a Single-Purpose Processor (FSMD – Finite State Machine with Datapath)

ECE 448 – FPGA and ASIC Design with VHDL

ctrl

Page 4: Lecture 12 PicoBlaze Overview

4

Block diagram of a General-Purpose Processor (Microcontroller)

ECE 448 – FPGA and ASIC Design with VHDL

Page 5: Lecture 12 PicoBlaze Overview

5ECE 448 – FPGA and ASIC Design with VHDL

PicoBlaze-3

Page 6: Lecture 12 PicoBlaze Overview

PicoBlaze-3 Overview

Page 7: Lecture 12 PicoBlaze Overview

PicoBlaze-6 Overview

Page 8: Lecture 12 PicoBlaze Overview

Size of PicoBlaze-6 in Spartan 6

1. Resource Utilization in CLB Slices

?

2. Number of PicoBlaze-6 cores fitting inside of the Spartan-6

FPGA (XC6SLX16) used in the Nexys3 FPGA board

?

Make an educated guess

Page 9: Lecture 12 PicoBlaze Overview

Size of PicoBlaze-6 in Spartan 6

1. Resource Utilization in CLB Slices

• 26 CLB Slices

• 1.1% of Spartan-6 used in Nexys3

2. Number of PicoBlaze-6 cores fitting inside of the Spartan-6

FPGA (XC6SLX16) used in the Nexys3 FPGA board

• 87 PicoBlaze cores

Page 10: Lecture 12 PicoBlaze Overview

Speed of PicoBlaze-6 in Spartan 6

1.Maximum Clock Frequency

?

2.Maximum number of instructions per second

?

Make an educated guess

Page 11: Lecture 12 PicoBlaze Overview

Speed of PicoBlaze-6 in Spartan 6

1.Maximum Clock Frequency

• 105 MHz

2.Maximum number of instructions per second

• 52.5 millions of instructions per second (MIPS)

Page 12: Lecture 12 PicoBlaze Overview

Register File of PicoBlaze-3

0

1

7

7

7

0

0

0

Address

7 0

7 0

7 0

7 0

7 0

16 Registers

8-bit

7 0F

s0s1s2s3s4s5s6s7

234567

sF

Page 13: Lecture 12 PicoBlaze Overview

Register File of PicoBlaze-6

• Instructions

REGBANK A

REGBANK B

used to switch between banks

• Only one set of flags

Z, C, I

• Very useful for

interrupt service routines

Page 14: Lecture 12 PicoBlaze Overview

Definition of Flags

Z = 1 if result = 0 0 otherwise

Zero flag - Z zero condition

Example*

C = 1 if result > 28-1 (for addition) or

result < 0 (for subtraction)

0 otherwise

*Applies only to addition or subtraction related instructions, refer to the following slides otherwise

Carry flag - C overflow, underflow, or various conditions

Flags are set or reset after ALU operations

Page 15: Lecture 12 PicoBlaze Overview

15

Interface of PicoBlaze-3

ECE 448 – FPGA and ASIC Design with VHDL

KCPSM = constant (K) coded programmable state machine

Page 16: Lecture 12 PicoBlaze Overview

16

Interface of PicoBlaze-3

ECE 448 – FPGA and ASIC Design with VHDL

Name Direction Size Function

clk input 1 System clock signal.

reset input 1 Reset signal.

address output 12 Address of the instruction memory.Specifies address of the instruction to be retrieved.

instruction input 18 Fetched instruction.

port_id output 8 Address of the input or output port.

in_port input 8 Input data from I/O peripherals.

read_strobe output 1 Strobe associated with the input operation.

out_port output 8 Output data to I/O peripherals.

write_strobe output 1 Strobe associated with the output operation.

interrupt input 1 Interrupt request from I/O peripherals.

interrupt_ack output 1 Interrupt acknowledgment to I/O peripherals

Page 17: Lecture 12 PicoBlaze Overview

17

Interface of PicoBlaze-6

ECE 448 – FPGA and ASIC Design with VHDL

Page 18: Lecture 12 PicoBlaze Overview

18

Additional Ports of PicoBlaze-6

ECE 448 – FPGA and ASIC Design with VHDL

Name Direction Size Function

bram_enable output 1 Read enable for the program memory. This signal should be connected to the enable input of the program memory and is used to reduce the power consumption associated with the BRAM(s).

k_write_strobe output 1 This output will pulse High for one clock cycle when KCPSM6 executes an ‘OUTPUTK’ instruction and the peripheral logic should capture the data provided on ‘out_port’ into the intended destination defined by the value of ‘port_id[3:0]’. Note that only the lower 4-bits of ‘port_id’ are used during ‘OUTPUTK’.

sleep input 1 Active High sleep control. When driven High KCPSM6 will complete the current instruction and then enter a sleep mode in which all activity stops. Whilst in the sleep mode all strobes are inactive and the ‘bram_enable’ is Low to disable the program memory resulting in minimum power consumption. All inputs except ‘reset’ are ignored. When ‘sleep’ is returned Low, KCPSM6 resumes execution from the point that it stopped.

Page 19: Lecture 12 PicoBlaze Overview

19

Generics of PicoBlaze-6

ECE 448 – FPGA and ASIC Design with VHDL

Name Default Range Function

hwbuild X”00” X”00”..X”FF” can be used to define any 8-bit value in the range ‘00’ to ‘FF’. It is then possible to load any KCPSM6 register with this value using the ‘HWBUILD sX’ instruction

interrupt vector “X3FF” X”00”..X”FFF” When an interrupt occurs (and interrupts are enabled) then KCPSM6 inserts and executes a special form of CALL instruction to a fixed address known as the interrupt vector. By defaultthis address is ‘3FF’ (the last location of a 1K program memory).

scratch_pad_memory_size

64 64, 128, 256 Size of the scratch pad memory. Increasing the default size to 128 (256) bytes, increases the resource utilizationby 2 slices (6 slices).

Page 20: Lecture 12 PicoBlaze Overview

20

PicoBlaze-6 Instantiation

ECE 448 – FPGA and ASIC Design with VHDL

Page 21: Lecture 12 PicoBlaze Overview

21ECE 448 – FPGA and ASIC Design with VHDL

Development

Flow of a

System

with PicoBlaze