LECT05

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Electrical & Computer EngineeringElectrical & Computer Engineering Dr. D. J. Jackson Lecture 5-1Electrical & Computer EngineeringElectrical & Computer Engineering

Digital Systems Design

Programmable Device Technologies and Introduction to the

Altera Cyclone IV FPGA


Logic gates and

programmableswitches

Inputs

(logic variables) Outputs

(logic functions)

Programmable Logic Device Black Box

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x x x

f 1

AND plane OR plane

Input buffers

inverters and

P 1

P k

f m

1 2 n

x 1 x 1 x n x n

General PLA Structure


f1

P1

P2

f2

x1 x2 x3

OR plane

Programmable

AND plane

connections

P3

P4

Gate Level PLA Structure

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f 1

P 1

P 2

f 2

x 1 x 2 x 3

OR plane

AND plane

P 3

P 4

Customary Schematic of a PLA


f1

To AND plane

D Q

Clock

SelectEnable

Flip-flop

Typical PLA Output Circuitry

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Structure of a CPLD

PAL-likeblock

I/O b

lock

PAL-likeblock

I/O block

PAL-likeblock

I/O b

lock

PAL-likeblock

I/O block

Interconnection wires


A Section of a CPLD

D Q

D Q

D Q

PAL-like block (details not shown)

PAL-like block

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VHDL code for the function f = m(0,2,4,5,6)

library ieee;use ieee.std_logic_1164.all;

entity func3 isport ( x1,x2,x3 : in std_logic;

f : out std_logic);end func3;

architecture logicfunc of func3 isbeginf <= (not x1 and not x2 and not x3) or

(not x1 and x2 and not x3) or(x1 and not x2 and not x3) or(x1 and not x2 and x3) or(x1 and x2 and not x3);

end logicfunc;


VHDL Implementation of f =m(0,2,4,5,6)

D Q

PAL-like block

(from interconnection wires)

x 1 x 2 x 3 unused

0

0 1

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Structure of an FPGA

Logic block Interconnection switches

I/O block

I/O block

I/O block I/O

blo

ck


A Two-Input Lookup Table

(a) Circuit for a two-input LUT

x 1

x 2

f

0/1

0/1

0/1

0/1

0

0

1

1

0

1

0

1

1

0

0

1

x 1 x 2

(b) f 1 x 1 x 2 x 1 x 2 + =

(c) Storage cell contents in the LUT

x 1

x 2

1

0

0

1

f 1

f 1

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A Three-Input Lookup Table

f

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

x 2

x 3

x 1


Inclusion of a flip-flop With an LUT

Out

D Q

Clock

Select

Flip-flop In1

In2

In3

LUT

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A Section of a Programmed FPGA

0 1 0 0

0 1 1 1

0 0 0 1

x 1

x 2

x 2

x 3

f 1

f 2

f 1 f 2

f

x 1

x 2

x 3 f


Pass transistor Switches in an FPGA

1 0

V f 1

V A

0

0 0 0 1

x 1

x 2

f 1

SRAM SRAM SRAM

(to other wires)

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Cyclone IV General Features

• Contain a two-dimensional row- and column-based architecture to implement custom logic

• Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks, and embedded multipliers

• The logic array consists of LABs, with 16 logic elements (LEs) in each LAB– An LE is a small unit of logic providing efficient

implementation of user logic functions. LABs are grouped into rows and columns across the device


Cyclone IV E Device Packaging Information

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Cyclone IV General Features (continued)

• Cyclone IV devices provide a global clock network and up to eight phase-locked loops (PLLs)– Consists of up to 30 global clock lines that drive

throughout the entire device– Can provide clocks for all resources within the device,

such as input/output elements (IOEs), LEs, embedded multipliers, and embedded memory blocks

– Global clock lines can also be used for other high fan-out signals

• Cyclone IV PLLs provide general-purpose clocking with clock synthesis and phase shifting– i.e. frequency and phase control


Cyclone IV General Features (continued)

• M9K memory blocks are true dual-port memory blocks with 8K bits of memory plus parity (9216 bits total)– Provide dedicated true dual-port, simple dual-port, or single-port

memory– Arranged in columns across the device in between certain LABs

• Each Cyclone IV device I/O pin is fed by an IOE located at the ends of LAB rows and columns around the periphery of the device

– Cyclone IV I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals

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Altera Cyclone IV Programmable Device


Cyclone IV Logic Element (LE)

• A four-input look-up table (LUT), which is a function generator that can implement any function of four variables

• A programmable register• A carry chain connection

– A fast interconnect between adjacent LABs

• A register chain connection– A fast, registered, connection between adjacent LEs

• The ability to drive all types of interconnects:– Local, row, column, register chain, and direct link interconnects

• Support for register packing– Combining a register with combinational logic in a design

• Support for register feedback– Feedback from flip-flop output back into the LUT

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Cyclone IV Logic Element (LE)


Cyclone IV LAB Structure

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Embedded Memory (M9K Block)

• 9,216 RAM bits

• Memory Configuration– True dual-port memory

– Simple dual-port memory

– Single-port memory

• Byte enable

• Common Functions– RAM

– ROM

– Shift register

– FIFO buffer

Dual Port Memory Configuration

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