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8/10/2019 Lect05 Diode
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Advanced VLSI Design CMPE 640Diode Details
Physical Representation
Abrupt junction betweenpand nmaterials creates a concentration gradient among the car-
riers.
Electrons diffusefrom ntopwhile holes diffuse frompto n.
The diffusion leaves behind bound chargein the lattice.
The bound charge sets up an electric field that counteracts the diffusion.
Electrons driftfrompto nwhile holes drift from ntop.
p
n
SiO2acceptor (boron) holes
donor (phosphorus) electrons
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Advanced VLSI Design CMPE 640Diode Details
Charge Distribution, Electric Field and Electrostatic Potential
- --
- -
+ ++
+ +
Hole diffusionElectron diffusion
Electron drift
Hole drift
p n
NA>ND
pregion more heavily
doped,
Charge Density
-
+
Electric Field
Potential0
neutral regionneutral regionplateplate
Distance
Distance
Distance
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Advanced VLSI Design CMPE 640Diode Details
Built-In Potential and I-V Characteristics
Build-in potential:
For example:
Forward bias
Raising potential of thep w.r.t ncauses current to flow frompto n.
Lowers potential barrier and diffusiondominates drift.
Minority carriers injected into neutral region and diffuse toward plates.
Recombine with majority carrier causing a net flow of current.
0
T
lnN
AN
D
n
i
2-----------------= where T
kT
q-------= = 26mV at 300K (Thermal V)
ni 1.5
10
10 carriers/cm3
=
N
A10
15carriers/cm
3=
0 2610
1510
16
2.2520
10--------------------------ln 638mV= =
ND
1016
carriers/cm3
=
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Advanced VLSI Design CMPE 640Diode Details
I-V Characteristics
Reverse bias
Raising potential of the nw.r.tpcauses current to flow from ntop.
Driftdominates diffusion.
However, current is small since the number of minority carriers (e.g., electrons inp
neutral region) is small.
For forward bias, the current is exponentiallyrelated to applied bias.
Current increases by a factor of 10 for every 60mV (2.3fT) of forward bias.
10
-15
10-10
10-510
0
0.0
ID(A)
0.2 0.4 0.6 0.8
2.3TV/decade
VD
0.5
1.0
1.5
0.5 1.0
VD
ID(mA)
Log scaleLinear scale
Small deviation
due to recombinationin depletion region.
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Advanced VLSI Design CMPE 640Diode Details
Static Behavior
Reverse BiasIdeal diode equation predicts diode current approaches the saturation current as VD
gets much smallerthan the thermal voltage.
Concentration of minority carriers at depletion-region approaches 0 under sufficient
reverse bias.
VD
T
>forID IS
Metalcontacttopregio
n
Metalcontacttonregion
-Wp p-region -W1 0 W2 n-region Wn x
np(x)
pn(x)
pn0
np0
Minority carrier concentration
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Advanced VLSI Design CMPE 640Diode Details
Static Behavior
Simple models of the diode.Left model based on ideal diode but is strongly non-linear and approximated by a sim-
ple model on the right.
Example: Assume VS= 3V and RS= 10kW and IS= 0.5X10-16.
+
-
VD
ID IS e
VD
T
1
=+
-
ID
VDonVD
+
-
Ideal diode model For a fully conducting diode, voltage drop
First order approx.
across diode is ~0.7V
+
-
VSRS VD
ID
Assuming VD=0.7V yields ID=0.23mA
Using non-linear model yields:
VD=0.757V and ID=0.224mA
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Advanced VLSI Design CMPE 640Diode Details
Dynamic Behavior
Dynamic behavior determines the maximum operational frequency.
It is dependent on how fast charge can be moved around.
Two capacitances
Depletionand diffusion.
Depletionregion andJunctioncapacitance:
Under the ideal model, the depletion region is void of mobile carriers.
Its charge is determined by the immobile donor and acceptor ions.
Intuitively:
Forward bias: Potential barrier is reduced which means that lessspace chargeis
needed to produce the potential difference.
This corresponds to a reduceddepletion-region width.
Reverse bias: Potential barrier increased, increase in space charge, widerdepletion
width.
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Advanced VLSI Design CMPE 640Diode Details
Dynamic Behavior
Expressions that convey this fact.Depletion region charge(VDis positive for forward bias):
Depletion-region width:
Maximum electric field:
The ratio of the n-side versus p-side depletion region width is determined by the dopinglevel ratios:
Qj
AD
2si
qN
AN
D
NA
ND
+-----------------------
0
VD
( )= (1)
Wj
W2
W1
2si
q----------
NA
ND
+
NA
ND
-----------------------
0
V D( )= =(2)
Ej
2q
si
-------
NA
ND
NA
ND
+-----------------------
0
VD
( )=where
si 11.7 1.05312
10 F/cm=
W2
W 1
-----------------
NA
ND
--------=
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Advanced VLSI Design CMPE 640Diode Details
Dynamic Behavior
The model (for an abrupt junction):
Imagine the depletion region as the dielectricof a capacitor with dielectric constant of
silicon.
And the n- and p-neutral regions act as the capacitor plates:
A small change in the voltage applied to the junction (dVD) causes a change in the spacecharge (dQj).
- --
- -
+ ++
+ +
p n
neutral regionneutral regionplateplate
Forward bias, cap increases
Reverse bias, cap decreases
insulator
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Advanced VLSI Design CMPE 640Diode Details
Dynamic Behavior
Depletionlayer capacitance:
Junction capacitance is easily computed by taking the derivative of equation (1) with
respect to VD. For an abrupt junction:
Cj0is the capacitance underzero-biasconditions and is only a function of the physical
parametersof the device:
The same result can be obtained using the standard parallel-plate capacitor equation:
Cj
dQj
dVD
----------- AD
si
q
2----------
NA
ND
NA
ND
+----------------------- 0 V D( ) 1
Cj0
1 VD
0
--------------------------------= = =
Cj0
AD
si
q
2----------
NA
ND
NA
ND
+-----------------------
01
=
Cj
si
AD
Wj
--------
= where Wjis given by equation (2).
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Advanced VLSI Design CMPE 640Diode Details
Dynamic Behavior
Junctioncapacitance plotted as a function of applied voltage bias:
Capacitance decreases with an increasingreverse bias.
For -5V, the cap. is reduced by more than a factor of 2 over the zero bias case.:
0.0
0.5
1.0
1.5
2.0
Cj(fF)/um
2
-4.0 -2.0 0.0VD
Strongly non-linearAbrupt junctionm = 0.5
Linear junctionm = 0.33
Cj0
Cj0
23
10 F/m2=
0
0.64V=
AD
0.5um2
= then a reverse bias of -2.5V yields
0.9fF um2
0.5um
2 0.45fF=
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Advanced VLSI Design CMPE 640Diode Details
Dynamic Behavior
For the general case:
Where mis the grading coefficient.
For an abrupt junction, m = 1/2.
For a linearly graded junction, m = 1/3 (see previous figure).
For digital circuits, operating voltages tend to move rapidly over wide ranges.
In these cases, we can replace the voltage-dependent, nonlinear capacitance Cj with anequivalent, linear capacitanceCeq.
Cj
Cj0
1 VD
0
( )m
-------------------------------------=
Ceq
Qj
VD
------------
Qj
Vhigh
( ) Qj
Vlow
( )
V
high
V
low
---------------------------------------------------------- Keq
Cj0
= = =
Keq
0m
Vhigh
V low( ) 1 m( )---------------------------------------------------------------
0V high( )
1 m
0V low( )
1 m=
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Advanced VLSI Design CMPE 640Diode Details
Dynamic Behavior
For example:
Cj0
0.5fF um2
=
0 0.64V=
AD
12um2
=
Compute the average junction capacitance if
this diode is switched between 0 and -5V.
Keq
0.64 0.5
0 5 V( ) 1 0.5( )---------------------------------------------------- 0.64 0( )
1 0.50.64 5( )( )
1 0.50.502= =
m 0.5=
AverageCj
0.502 0.5fF/ um2
0.25fF
um2-----------= =
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Advanced VLSI Design CMPE 640Diode Details
Secondary Effects
Actual diode current is less than what is predicted by the ideal eq.
Not all of the applied bias voltage falls across the junction, some falls across the neu-
tral regions.
However, the resistivity of the neutral regions is generally small (1 to 100 Ohms).This is usually modeled with a series resistance at the contacts.
Avalanche breakdown(MOS and bipolar processes):
ID(A)
0.1
-0.1-25 -15 -5 0 5
VD(V)
Breakdownvoltage
Increased reverse bias increases electric field across
the junction to Ecrit.
Electron-hole pairs are created on collision with
immobile silicon atoms.
Non-destructive but increases power consumption
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Advanced VLSI Design CMPE 640Diode Details
Secondary Effects
Operating temperature effects
The thermal voltageis linearly dependent upon temperature (increasing fTcauses the
current to drop).
The thermal equilibrium carrier concentrations increasewith increasing temperaturecausing ISto increase.
Experimentally, the reverse current doubles every 8 degrees C.
These have a dramatic effect on the operation of the circuit.Current levels can increase substantially (~2X every 12 degrees C).
The increase in leakage current through reverse-biased diodes decreases isolation qual-
ity.
ID
IS
eVD
T
1
=TkT
q-------=
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Advanced VLSI Design CMPE 640Diode Details
SPICE Models
The preceding discussion presented a model for manual analysis.
If second-order effects or more accuracy (better model) is desired, simulation is required.
The standard SPICE model:
RSmodels the series resistanceof the neutral regions (reducing current).
RS
CDVD
+
-
ID
IS
eVD
nT
1
=
ID
Extra parameter n is called the emission coefficient
It is equal to 1 for most diodes.
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Advanced VLSI Design CMPE 640Diode Details
SPICE Models
The dynamic behavior is modeled by thenonlinear
capacitance CD.Two different charge storage effects are combined in the diode:
excess minority carrier charge(not discussed, forward bias only)
depletion-region charge
Table 1: First-order SPICE diode model parameters
Parameter name Symbol SPICE Name Units Default Value
Saturation Current IS IS A 1.0E-14
Emission Coefficient n N - 1
Series Resistance RS RS 0
Transit Time T TT s 0Zero-bias Junction Cap Cj0 CJ0 F 0
Grading Coefficient m M - 0.5
Junction Potential 0 VJ V 1
CD
T
I
sT
-----------e
VD n
T
Cj0
1 VD
0
( )m---------------------------------------+= T transit time=where: