Lect 14 Class CCP

8/2/2019 Lect 14 Class CCP

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Microprocessor &Microcontroller Based System

Shahid S. Jan

Assistant Professor

.

05/02/12 1PAF KIET MMBS


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CAPTURE/COMPARE MODULE

PIC16C74A has two CCP Modules

CCP1 & CCP2

Each CCP module contains a 16 bitregister (two 8-bit registers) and can

operate in one of the three modes

16-bit capture

16-bit compare

10-bit Pulse Width Modulation (PWM).

05/02/12 PAF KIET MMBS 2


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CCP1 Module:

Consists of two 8-bit registers, viz.,CCPR1L (low byte) and CCPR1H (high

byte).

The CCP1CON register controls the

operation of CCP1 Module.



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CCP2 Module:

Consists of two 8 bit registers, CCPR2L (Low

byte) and CCPR2H (high byte).

The CCP1CON register controls the operation of

CCP2 Module. Both CCP1 and CCP2 modules are identical in

operation with the exception of the operation of special

event trigger.



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Timer resources for the CCP Mode. CCP1CON Register (Address 17H )


CCP MODE TIMER USED

CAPTURE TIMER 1

COMPARE TIMER 1

PWM TIMER 2


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CCP2CON Register is exactly similar to

CCP1CON register.

CCP2CON Register address is 1DH.

CCP1CON controls CCP module1 whereas CCP2CON controls CCP Module2.



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CAPTURE MODULE

Capture Mode (CCP1):

Capture Mode captures the 16-bit value of TMR1 into

CCPR1H:CCPR1L register pair in response to an eventoccurring on RC2/CCP1 pin.

Capture Mode for CCP2 is exactly similar to that of CCP1.



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CAPTURE MODULE

An event on RC2/CCP1 pin is defined as

follows:

Every falling edge

Every rising edge.

Every 4th rising edge.

Every 16th rising edge.

Decided by bit 3-0 of CCP1CON register



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CAPTURE MODULE

Capture mode of operation

Required condition for capture mode

1.RC2/CCP1 pin to be configured input by

setting TRISC (bit 2).

2. Timer 1 should be operated from the

internal clock (fosc/4), i.e., timer mode

or in synchronized counter mode.05/02/12 PAF KIET MMBS 9


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CAPTURE MODULE


Capture operation


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COMPARE MODULE

Compare mode for CCP2 similar to CCP1 Except that in special event trigger mode, CCP1 resets TMR1only, whereas CCP2 resets TMR1 and starts A/D conversion if

A/D module is enabled.

In compare mode, the 16-bit CCPR1 register value iscompared against TMR1 register pair (TMR1H and

TMR1L) value.

When a match occurs, the RC2/CCP1 pin is driven high ordriven low or remains unchanged as decided by

CCP1CON bits.



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COMPARE MODULE


Required conditions for compare mode

1.RC2/CCP1 pin must be configured as an output

by clearing TRISC bit.

2. Timer-1 should be operated in timer mode (i.e.,

internal clock source of fosc/4) or insynchronized counter mode.


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COMPARE MODULE Compare operation

In special event trigger mode, both CCP1 and CCP2 initiates an

A/D conversion.



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PWM MODE

Both CCP1 and CCP2 have similar operation in

PWM mode.

In PWM mode, the CCP1 pin produces upto a10-bit resolution Pulse Width Modulation (PWM)

output.

RC2/CCP1 pin should be configured in the

output mode by clearing TRISC bit.



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PWM OPERATION



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PWM OPERATION

PR2 (Period Register, 8 bit) decides the PWM period

CCPR1L (8-bits) and CCP1CON (2-bits) decide

the PWM duty cycle.

When TMR2 equals PR2, the SR latch is set andRC2/CCP1 pin is pulled high.

In the same time, TMR2 is cleared and the duty cycle

value available in CCPR1L is latched to CCPR1H.

CCPR1H, CCP1CON decide the duty cycle when this 10-bit equals the TMR2+2 prescaler or Q-bits,

the SR latch is set and RC2/CCP1 pin is driven low.



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PWM


A PWM output as shown has a time period. The time for which the

output stays high is called duty cycle.


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PWM PERIOD

PWM period is specified by writing to PR2 register.

PWM period can be calculated using the following

formula:

PWM period = [( PR2) + 1] 4 T osc (TMR2 prescale value)

PWM frequency = 1/ PWM period

When TMR2 is equal to PR2, the following events occur

on the next increment cycle.

TMR2 is cleared

CCP1 pin is set

PWM duty cycle is latched from CCPR1L into CCPR1H



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PWM DUTY CYCLE

PWM duty cycle is specified by writing to the CCPR1L

register and to CCP1CON < 5 : 4 > bits.

Up to 10-bit resolution is available where CCPR1L

contains the eight MSBs & CCP1CON < 5 : 4 > contains

the two LSB's.

10-bit value represented by CCPR1L : CCP1CON < 5 : 4

>.

The PWM duty cycle is given by

PWM duty cycle = (CCPR1L : CCP1CON < 5 : 4 > ). T osc.

(TMR2 prescale value)



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PWM DUTY CYCLE


10-bit counter configuration from Timer-2

Counting mechanism of Timer-2


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PWM DUTY CYCLE

If the prescaler is 1, the 10-bit counter is configured as

follows

Prescaler set to divide by one



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PWM DUTY CYCLE

If the prescaler is 4, the 10-bit counter is configured as

follows.

Pre-scaler programmed to divide by four



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PWM DUTY CYCLE

If the prescaler is 16, the 10-bit counter is realized as

follows.

Prescaler programed to divide by 16



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PWM DUTY CYCLE

CCPR1L and CCP1CON < 5 : 4 > can be written anytime,

the duty cycle value is not latched into CCPR1H until a

match between PR2 and TMR2 occurs.

In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used

to double buffer the PWM duty cycle.



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PWM DUTY CYCLE

This double buffering is essential for glitch less

PWM operation.

When the CCPR1H and 2-bit latch match TMR2concatenated with an internal 2-bit Q clock or 2-

bits of prescaler, the CCP1 pin is cleared.



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PWM DUTY CYCLE

Maximum PWM resolution (bits) for a given PWM

frequency can be calculated as

Resolution = bits

If the PWM duty cycle is longer than the PWM period,

then the CCP1 pin will not be cleared.



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PWM PERIOD AND DUTY CYCLE

CALCULATION

Example:

Desired PWM frequency = 78.125 kHz

fosc

= 20MHz

TMR2 Prescalar = 1

Find the maximum resolution of duty cycle that can be

used with a 78.124 kHz frequency and 20 MHz oscillator.



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PWM PERIOD AND DUTY CYCLE

CALCULATION

256 = 2PWM Resolution

At most, an 8-bit resolution duty cycle can be obtained

from a 78.125 kHz frequency and 20 MHz oscillator

ie, 0 CCPR1L : CCP1CON 255 .

Any value greater than 255 will result in a 100 % duty

cycle. The following table gives the PWM frequency fPWM if

fosc = 20MHz



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END OF LECTURE


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Lect 14 Class CCP