Design for Manufacturability and Power EstimationLecture 25Alessandra NardiThanks to Prof. Jan Rabaey and Prof. K. Keutzer

Physical issues verification (DSM)InterconnectsSignal IntegrityP/G integrity Substrate coupling CrosstalkParasitic Extraction Reduced Order ModelingManufacturabilityPower Estimation

OutlineDesign for ManufacturabilityYieldParametric YieldDefect-related yieldStatistical Design

Power EstimationPower consumption mechanismsDifferent level of abstractionStatic or dynamic analysis

Physical issues verification (DSM)ManufacturabilityIC manufacturing process is affected by random disturbances different silicon dioxide growth rates, mask misalignement, drift of fabrication equipment operation, etc.These disturbances are often uncontrollable and affect the circuit performanceHow good is my chips performance?How many of my chips will work?Yield: percentage of manufactured products that pass all performance specificationsYield loss mechanismsParametric yield (process variations)Defect-related yield (defects)

Parametric YieldProcess variations

Process Variations SPICE modelProcess variations are reflected into a statistical SPICE modelUsually only a few parameters have a statistical distribution (e.g. : {DL, DW, TOX,VTn, VTp}) and the others are set to a nominal value The nominal SPICE model is obtained by setting the statistical parameters to their nominal value

Global Variations (Inter-die)Process variations Performance variations

Critical path delay of a 16-bit adderAll devices have the same set of model parameters value

Local Variations (Intra-die)Each device instance has a slightly different set of model parameter values (aka device mismatch)The performance of some analog circuits strongly depends on the degree of matching of device propertiesDigital circuits are in general more immune to mismatch, but clock distribution network is sensitive (clock skew)

Statistical DesignNeed to account for process variations during design phase

Statistical designNominal designYield optimizationDesign centering

Statistical Design

Design for Manufacturability (DFM)Approaches1) Worst-Case Approach: choose the SPICE model giving the worst possible behaviorTraditional choice is pessimistic and lead to circuit overdesign (neglects any kind of correlation)Other techniques to choose the SPICE model values (accounting for correlation)

2) Probability Density Function Approach: keep track of the whole distributionExpensive: need smart ways to do it

Defect-related YieldManufacturing process may introduce some defects in the layoutFrom W. Maly Computer-aided design for VLSI circuit manufacturability, IEEE Proc. 1990.

Defect-related YieldDefect-layout relationshipYield in terms of area and design rulesLarger area lower yieldSmaller geometries higher sensitivity to defects trade-off: yield loss must be expressed in terms of the defect size and layout characteristics rather than in terms of area aloneMore relaxed layoutMore aggressive layout

Defect-related YieldCritical areaModel relationship between defect characteristics (density and size distribution) and the probability of the defectThe critical area, for a defect radius R, is defined as the area on the layout where, if the center of a defect is deposited a fault occurs:From W. Maly Computer-aided design for VLSI circuit manufacturability, IEEE Proc. 1990.

Physical issues verification (DSM)Power EstimationHigher speed and shrinking geometries Increased power consumption and heat dissipationHigher packaging costsHigher on-chip electric fieldDecreased reliability

power dissipation of VLSI circuits becomes a critical concern

Accurate and efficient power estimation (and optimization) techniques are required

Low Power ChallengesMultifaceted approach adopted:Reducing chip capacitance through process scalingReducing voltageEmploying better architectural and circuit design techniques

From 2D to 3D optimization problemFrom D. Singh et al Power Conscious CAD Tools and Methodologies: A Perspective, IEEE Proc. 1995.

Power and Synthesis FlowAccuracy of Power EstimationPotential for Power SavingsBehavioralRTLGateSwitch20%400%50%10% 1997 Jan M. Rabaey

Design Abstraction LevelsBehavioralSynthesisRTLSynthesisLogicOptimizationTransistorOptimizationPlace & RouteHDLPowerAnalysisPowerAnalysisPowerAnalysisPowerAnalysis 1997 Jan M. Rabaey

Power Consumption Mechanisms in CMOSStatic ConsumptionSmall component (increasing importance for DSM)Leakage diodes and transistors

Dynamic ConsumptionDue to load capacitanceLargest componentDue to direct-path currents

CMOS Power Consumption MechanismsStatic consumptionIdeally zeroDue to:Leakage current through reverse biased diode junctionbetween source (or drain) and the substrateSubthreshold current of the transistor Digital Integrated Circuits2nd

CMOS Power Consumption MechanismsDynamic consumption Load CapacitanceMajor componentEnergy/transition:

Power=Energy/transition:

if the gate is switched on and off f times per second

Note: it is not a function of gate size! Digital Integrated Circuits2nd

CMOS Power Consumption MechanismsDynamic consumption Switching activity Digital Integrated Circuits2nda01 is called the switching activityCeff = a01 CL is called the effective capacitance

CMOS Power Consumption MechanismsDynamic consumption Short Circuit currentIdeally zeroNot zero since rise and fall time (tr and tf) are not zeroPower=Energy/transition:

if the gate is switched on and off f times per secondIpeak determined by the saturation current of the devices Digital Integrated Circuits2nd

Power Consumption Mechanisms in CMOSVDDInOutCL Dynamic Dissipation Short-Circuit Currents Static DissipationISC 1997 Jan M. RabaeyComplete power model provides infrastructure for analysis and optimization Concentrate on the estimation of a01

Power EstimationDynamic AnalysisSimulationrequires representative simulation vectorsDerived by designerAutomatic (Monte Carlo)Transitor level (PowerMill)Very accurate Much faster than SPICEGate level (Powergate, DesignPower)Faster than transistor levelStill very accurate due to good modeling of power dissipation at cell-level

Power EstimationStatic AnalysisPropagation of switching probabilitiesNo input vectors neededMuch faster than simulationLess accurate than simulationHard to model real delaysGlitches?

Power EstimationStatic Analysis Probability Propagation

AND gatesp(1) = sp1 * sp2tp(01) = sp * (1 - sp)

Examplesp = 0.5 * 0.5 = 0.25tp = 0.25 * (1 - 0.25) = 0.18751/21/21/21/21/41/47/16Propagate 1997 Jan M. Rabaey

Power EstimationStatic Analysis Probability PropagationIgnores Temporal and Spatial Correlations 1997 Jan M. Rabaey

Power EstimationStatic Analysis Probability Propagation: Problems0.50.50.750.375?0.5!Problem: Reconvergent Fan-out:Creates spatial correlation between signalsP(X) = P(B=1).(P(X=1 | B = 1) 1997 Jan M. Rabaey

Power OptimizationSupply voltage reductionMost effective: quadratic improvementImplies performance degradationUse of multiple-VDD (not below the sum of thresholds)Increase of leakage currentEffective capacitance reductionReduce physical capacitanceReduce switching activity

True at all levels of abstraction: trade-off between impact on the design and accuracy

SummaryDesign for ManufacturabilityYieldParametric YieldDefect-related yieldStatistical Design

Power EstimationPower consumptionmechanismsDifferent level of abstractionStatic or dynamic analysis

Class ReviewFundamentals of Circuit Simulation Formulation of circuit equations Solution of linear equations Solution of nonlinear equationsSolution of ordinary differential equationsAnalog Circuits SimulationAnalog Hardware Description LanguagesDigital Systems VerificationOverviewEquivalence CheckingFastMOS simulationTiming AnalysisHardware Description Languages System CPhysical Issues VerificationInterconnectsSignal IntegrityParasitic Extraction Reduced Order ModelingManufacturabilityPower Estimation