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Lec 12 Systems Architecture 1
Systems Architecture
Lecture 12: Design of the MIPS ALU
Jeremy R. JohnsonAnatole D. RuslanovWilliam M. Mongan
Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).
Lec 12 Systems Architecture 2
Introduction
• Objective: To learn what operations are performed by the Arithmetic Logic Unit (ALU) and to learn how the MIPS ALU is implemented.
• Topics– MIPS logical operations– Full Adder– 1-But ALU– The design of the MIPS 32-Bit ALU– Overflow and Overflow Detection– Carry Lookahead
Lec 12 Systems Architecture 3
Addition and Subtraction
• Carry-ripple adder
0000 0111
+ 0000 0110
0000 1101
0000 0111 0000 0111 0000 0110 0000 0110
- 0000 0110 +1111 1010 - 0000 0111 + 1111 1001
0000 0001 0000 0001 1111 1111 1111 1111
1
0
(0) 1
1
1
(1) 0
(0)
1
1
(1) 1
(1)
0
0
(0) 1
(1)
0
0
(0) 0
(0)
0
0
(0) 0
(0) (Carries)
97108/Patterson Fig 4.03
Lec 12 Systems Architecture 4
Overflow Detection
• Overflow occurs in the following situations
Operation A B ResultA+B >= 0 >= 0 < 0A+B < 0 < 0 >= 0A-B >= 0 < 0 < 0A-B < 0 >= 0 >= 0
Lec 12 Systems Architecture 5
Logical Operations
• Shift left << sll• Shift right >> srl• Shift right arithmetic sra• Bitwise and & and, andi• Bitwise or | or, ori• Bitwise complement (not) ~ not (pseudo)• Exclusive or ^ xor, xori
Lec 12 Systems Architecture 6
Representation of Shift Instruction
• Example
sll $t2, $s0, 8 # $t2 = $s0 << 8
$t2 = $10, $s0 = $16
000000 00000 10000 01010 01000 000000
op rs rt rd shamt func
Lec 12 Systems Architecture 7
Example use of Logical Operations
Int data;
struct {
unsigned int ready: 1;
unsigned int enable: 1;
unsigned int receivedByte: 8;
} receiver;
…
data = receiver.receivedByte;
receiver.ready = 0;
receiver.enable = 1;
• Assume data in $s0• receiver in $s1
• sll $s0, $s1, 22• srl $s0, $s0, 24
• andi $s1, $s1, 0xfffe• ori $s1, $s1, 0x0002
9 2 1 0
| receivedByte | enable | ready
Lec 12 Systems Architecture 8
Building Blocks
c = a . bba
000
010
001
111
b
ac
b
ac
a c
c = a + bba
000
110
101
111
10
01
c = aa
a0
b1
cd
0
1
a
c
b
d
1. AND gate (c = a . b)
2. OR gate (c = a + b)
3. Inverter (c = a)
4. Multiplexor (if d = = 0, c = a; else c = b)
Lec 12 Systems Architecture 9
Full Adder
• Sum = parity(a, b, CarryIn)– a xor b xor c + abc a xor b xor c
• CarryOut = majority(a, b, CarryIn)– bCarryIn + aCarryIn + ab + abCarryIn – bCarryIn + aCarryIn + ab
a b CarryIn Sum CarryOut0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Sum
CarryIn
CarryOut
a
b
b
CarryOut
a
CarryIn
b
a
CarryIn
Sum
Lec 12 Systems Architecture 11
Building a 32-Bit ALU
• Chain 32 1-Bit ALUs
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
Lec 12 Systems Architecture 12
Supporting Subtraction
• Subtraction is equivalent to adding the inverse– In two’s complement a + b + 1
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
Lec 12 Systems Architecture 13
Overflow and SLT• Modify last 1-Bit ALU
– SLT set if (a < b) a - b < 0– Check sign bit after subtraction– Check overflow in last 1-Bit
ALU– Need to take overflow into
account for SLT
0
3
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b 2
Less
0
3
Result
Operation
a
1
CarryIn
0
1
Binvert
b 2
Less
Set
Overflowdetection
Overflow
a.
b.
0
3
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b 2
Less
0
3
Result
Operation
a
1
CarryIn
0
1
Binvert
b 2
Less
Set
Overflowdetection
Overflow
a.
b.
Lec 12 Systems Architecture 14
Overflow and SLT• Overflow?
– How do we check for overflow?– What do we do with slt if we
encounter overflow?
0
3
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b 2
Less
0
3
Result
Operation
a
1
CarryIn
0
1
Binvert
b 2
Less
Set
Overflowdetection
Overflow
a.
b.
0
3
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b 2
Less
0
3
Result
Operation
a
1
CarryIn
0
1
Binvert
b 2
Less
Set
Overflowdetection
Overflow
a.
b.
Lec 12 Systems Architecture 15
Overflow and SLT
• When adding two positive numbers and a final carry out is produced, is this overflow?
– Yes! This is intuitive.
• When adding two negative numbers and a final carry out is produced, is this overflow?
– No! Recall 2’s complement sign extend proof and the (x + -x) example.– A final carry out is expected.
• Notice the carry in to the most significant (sign) bit ALU in each case and derive an overflow formula that will work in all cases.
• When overflow occurs, what happens to the SLT signal? Derive this as well.
Lec 12 Systems Architecture 16
32-Bit ALU with Sub and Slt
Seta31
0
ALU0 Result0
CarryIn
a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Binvert
CarryIn
Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
Lec 12 Systems Architecture 18
Final 32-Bit ALU
Seta31
0
Result0a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Bnegate
Zero
ALU0Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
Control Function000 and001 or010 add110 sub111 slt
ALU ResultZero
Overflow
a
b
ALU operation
CarryOut
Lec 12 Systems Architecture 19
Carry Lookahead Adder
• Why is it easy to add 12345 + 87654 in your head? Why is it harder to add 65345 + 89298?
• If there are no carries (or if we can figure them out a priori), we can compute the additions themselves in parallel.
• As it stands now, we must ripple the carries through each ALU, causing a linear time addition. This extra time is spent propagating the carry out to the next carry in.
• By computing the carry in advance, we can improve addition to logarithmic time.
Lec 12 Systems Architecture 20
Carry Lookahead Adder
• In binary addition there are only a few possible cases:– 1 + 1 (a = b = 1)– 0 + 0 (a = b = 0)– 0 + 1 or 1 + 0 (a xor b)
• Notice!– The a = b = 1 case will always produce a carry out (Cout = 1),
regardless of the carry in– The a = b = 0 case will never produce a carry out (Cout = 0), regardless
of the carry in– The a xor b case will result in Cout = Cin
• The result is the carry status (generate, kill, propagate)• Carry status signals can be combined (for example,
generate followed by a kill is a kill)
Lec 12 Systems Architecture 21
Carry Lookahead Adder
• if (ai-1 = bi-1=0) then ci = 0 “kill”
• if (ai-1 = bi-1=1) then ci = 1 “generate”
• if (ai-1 bi-1) then ci = ci-1 “propagate”
+ai-1
bi-1
ci-1
ci
a_{i-1} b_{i-1} Carry Status0 0 kill0 1 propagate1 0 propagate1 1 generate
Lec 12 Systems Architecture 22
Carry Lookahead Adder
• We can logically define these carry status signals as:– Generate Signal Gi = Ai AND Bi– Propagate Signal Pi = Ai XOR Bi
• Now how do we compute Carry Out?
Lec 12 Systems Architecture 23
Carry Lookahead Adder
• Couti = Gi OR (Pi AND Cini)
• But recall that Cini is really the previous Couti-1, and we can compute that as Gi-1 OR (Pi-1 AND Cini-1)
• How did we define G and P? Can you write the recursive formula in terms of A and B only?
• If so, we can compute this fast.
Lec 12 Systems Architecture 24
Combined Carry Status
• xi = kill if (ai-1 = bi-1)
• xi = generate if (ai-1 = bi-1)
• xi = propagate if (ai-1 bi-1)
• yi = yi-1 xi = x1 xi
otimes kill propagate generatekill kill kill generatepropagate kill propagate generategenerate kill generate generate
FAi-1
FAi
+ai
bi
ci+1
+ai-1
bi-1
ci-1
Lec 12 Systems Architecture 25
Calculating Carry from Carry Status
Lemma:– yi = kill ci = 0
– yi = generate ci = 1
– yi = propagate does not occur
Proof:1 yi = kill xi = kill ci = 0 or
– xi = propagate and yi-1 = kill and ci = majority(ci-1, ai, bi) = ci-1 = kill (by induction)
2 yi = generate xi = generate ci = 1 or
– xi = propagate and yi-1 = generate and ci = majority(ci-1, ai, bi) = 1 (by induction)
3 yi = propagate xi = propagate and yi-1 = propagate, which by induction leads to a contradiction