Lab5 Numaratoare Divizoare

7/28/2019 Lab5 Numaratoare Divizoare

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Laborator 5

Counters and Frequency dividers

Necessary Hardware and Software

- Nexys2 Development Boards + USB-Mini Cable

- ISE 12.2 or newer software

Laboratory exercises1. Four-bit counter. The initialization problem.

a. Create a new project on C:\Temp targeting the FPGA device present on thedevelopment board you have. Name the project Cnt4bit_group_name ,

b. Create a top-level module with the name and ports shown below:

Figure 1. Top-level module for a simple four-bit counterNOTE: Set the mode of the output port Q to wire. Create an internal signal with themode reg and name it Q_reg. Assign Q to Q_reg.

The code of the module is similar to the code of a shift register:

reg [3:0] Q_reg;

assign Q = Q_reg;

always @ (posedge CLK)Q_reg


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Also, if you apply the ucf constraints (connect CLK to BTN0, Q to LED and dontforget about the NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; constraint), the boardwill show correct counter behavior.

Why is this happening?

- When downloading a design to an FPGA, all of the internal registers are initializedto 0, if not otherwise specified. Therefore the counter will start from 0 and functionscorrectly

- This is also the role of the glbl module found in Post-translate and Post-routesimulations, to INITIALIZEthe internal registers. Its effect takes 100 time units .

This is also the reason for the #100; statement in the testbench template.Therefore, do not remove the #100; statement from the testbench code. Also writeany stimulus after the #100; statement.

However, in behavioral simulation the glbl module is not present and because theQ_reg signal is uninitialized , the behavioral simulator will consider that Q_reg has anunknown value. Obviously, unknown + 1 = unknown

c. Change the code of the counter module to initialize Q_reg as shown below:

reg [3:0] Q_reg= 4b0101;

If the design is simulated using either Behavioral, Post-Translate or Post-Routesimulation, the counter will start from 5 (4h5) and will work correctly. Also, if the designis downloaded to the board, the counter will start from 4h5. Note that ISEimplementation tools take into account the initial values.

However, counters often need to be initialized in runtime. This is usually done usingReset and/or Load signals.

2. Eight-bit reversible counter with synchronous Load and asynchronous Reset.a. Create a new project on C:\Temp targeting the FPGA device present on the

development board you have. Name the project Cnt8bitUnD_RL_group_name .b. Create a top-level module with the name and ports shown below:


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Figure 2. Top-level module for the 8-bit reversible counter with asynchronous reset

and synchronous loadNote: Und is the signal setting the count direction (Up not Down). The counter countsup when UnD = 1b1, otherwise counts down.

Also use Q in wire mode and define an internal reg mode Q_reg signal. The code of the

counter is very similar to the code of the eight-bit shift register with reset and load, onlythe operation on the output changes:

always @ (posedge CLK orposedge Reset)if (Reset) Q_reg


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Notes:- Reset and UnD have to be initialized to 1 instead of 0- Wait until Q rolls over counting up means that the testbench has to wait until Q,

counting up, becomes 8hFF then 8h00 (+ one more clock period, because the value of

Q will be visible by other component only at the next positive clock edge).Consequently, Wait until Q rolls over counting down means that the testbench has towait until q, counting down, becomes 8h00 then 8FF (+ one more clock period). Thiscan be achieved in the testbench code by waiting for the values of Q, as shown below:

//wait until Q rolls over@ (Q == 8hFF);@ (Q == 8h00);@ (posedge CLK);

Similarly the code of the testbench for waiting until Q rolls over counting down can bewritten.

Analyze the circuit versus the testbench stimulus in Figure 3 and describe its behavior byanswering to the questions in the table below! Simulate then the design using behavioral(or post-translate) simulation, and check your answers versus the simulation results!

Table 1. Eight-bit reversible counter analysis questions

QuestionAnswer afteranalyzing the

circuit

Answer aftersimulating the

circuit1. What will be the value of Q after Clock Edge 4?2. What will be the value of Q after Clock Edge 5?3. What will be the value of Q after Clock edge 7?4. What is the value of M, i.e. one clock periodafter Q rolls over (i.e. becomes 8h00), countingup?5. What is the value of N, i.e. one clock periodafter Q rolls over (i.e. becomes 8h00), countingdown?

Note: The easiest way to determine the value of M and N is to count the number of clockperiods. This can be done in the testbench by using another variable and a separate initialstatement in conjunction with a forever loop, as shown below:


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//at the signal declaration areainteger i;initial begin

i = 0;@ (negedge Reset);forever @ (posedge CLK) i = i+1;

end ;

Note that in a testbench all of the initial statements are executed simultaneously, onlyonce

Apply the ucf constraints for the board and try the functionality of the design on theboard. Connect:

CLK to btn0Reset to btn1Load to btn2UnD to btn3Din to the switchesQ to LEDs

3. Decode and display the outputs of the eight-bit counter on the seven-segment displaya. Create a new project on C:\Temp targeting the FPGA device present on the

development board you have. Name the project Cnt8bit_ssg_group_name b. Create a top-level module and name it Cnt8bit_ssg . Connect the components

according to the figure below. Reuse the cnt8UnD_RL counter from point 2 b_.Thesource file for the Ssg_decoder module can be found in the /Lab3 or /Lab5 folders:


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Figure 4. Top-level module schematic diagram for the counter connected to the seven-segment decoder

c. Apply the ucf constraints to the design. Connect:- SW to the switches, AN to the anodes and SEG to the seven-segment signals- SYSCLK to the system clock of the board. Do not use theCLOCK_DEDICATED_ROUTE constraint for SYSCLK!- BTNCLK to BTN0.Use the CLOCK_DEDICATED_ROUTE constraint for BTNCLK!

- Reset to BTN1, Load to BTN2 and UnD to BTN3

Try the functionality of the design on the board

d. Change the code of the counter to count in BCD code i.e in decimal only!

4. Use a frequency divider to make the counter to run automaticallyThe SYSCLK can be also sourced to the cnt8UnD_RL counter. However the SYSCLKfrequency is 50MHz, so the counter value will not be visible on the seven-segment display.Therefore the frequency of the SYSCLK has to be divided to 1..10HZ. This can be achieved,for example, by using the Freq_Div_gated divider module. The source of the module can bealso found in the /LAB5 folder.

a. Create a new project on C:\Temp targeting the FPGA device present on thedevelopment board you have. Name the projectCnt8bit_div_gated_ssg_group_name


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b. Create a top-level module and name it Top_Cnt8bit_div_gated . Connect thecomponents according to the figure below.

Figure 5. Top-level module schematic diagram for the counter with divided clock

c. Apply the ucf constraints to the design. Connect:- SW to the switches, AN to the anodes and SEG to the seven-segment signals- SYSCLK to the system clock of the board. Do not use theCLOCK_DEDICATED_ROUTE constraint for SYSCLK!- CLK_OUT to LED0

- Reset to BTN1, Load to BTN2 and UnD to BTN3

Try the functionality of the design on the board

d. Override the OUT_FREQUENCY_HZ parameter for the Freq_Div_gated divider withsome other value (for example, 2) and the REFRESH_RATE parameter for theSsg_decoder module (for example, 100) and download the design to the boardagain. What changes in the functionality?

Note that Place-and-Route returns a warning message:

Route:455 - CLK Net:CLK_OUT_OBUF may have excessive skew because 4 CLK pins and

1 NON_CLK pins failed to route using a CLK template.


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This is due the fact that the CLK_OUT signal was internally generated i.e. dividedfrom SYSCLK and no dedicated clocking components neither dedicated clock pins wereused for CLK_OUT.

If CLK_OUT was generated using combinational circuits, this is also referred as

GATED CLOCK. It is not recommended to use gated clocks in the design because:- Combinational circuits can present hazard i.e. glitches that can lead to extra

clock edges in the circuit- Gated clocks can not use the FPGA clocking resources; therefore the timing

delay on the clock nets can be very large, exceeding the timing delays of othersignals. Remember that digital circuit analysis for circuits with a single clock isbased on the assumption that the clock signal arrives to every circuit at thesame time i.e. faster than the other signals, assuming that the clock signal is notintentionally delayed between components

The recommended design practice is to use the main clock (in our case: SYSCLK) forevery component in the same clock domain. For components that run at lowerfrequency use a CLOCK ENABLE(CE) signal and enable component operation based onCE.

5. Eight-bit counter with clock enablea. Create a new project on C:\Temp targeting the FPGA device present on the

development board you have. Name the project Cnt8bit_CE_ssg b. Create a new module and name it Cnt8bit_CE . Reuse the code from the

cnt8UnD_RL module. Add the CE port as input and enable counting only if CE=1b1. The symbol of the Cnt8bit_CE module can be found in the figure below.

c. Create a top-level module and name it Top_Cnt8bit_CE . Connect the componentsaccording to the figure below. The source for the Freq_Div module can be alsofound in the /Lab5 folder:


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Figure 6. Top-level module schematic diagram for the counter clock enable

d. Apply the ucf constraints to the design. Try the functionality of the design on theboard

e. Note that Led0 does not lights up anymore. What is the difference between theoutputs of Freq_Div_gated and Freq_Div ?Create a testbench and include both frequency dividers in the testbench. Use asmall ration for CLK_FREQUENCY_HZ/OUT_FREQUENCY_HZ in order to avoid longsimulations (for example, less than 100). Simulate the two frequency dividers in

order to compare their outputs!

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Lab5 Numaratoare Divizoare