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8/19/2019 L4970A Design Considerations http://slidepdf.com/reader/full/l4970a-design-considerations 1/47 APPLICATION NOTE EASY APPLICATION DESIGN WITH THE L4970A, MONOLITHIC DC-DC CONVERTERS FAMILY by G. Gattavari and C. Diazzi THE TECHNOLOGY The technologyarchitecture is basedon the verti- cal DMOS silicon gate process that allows a channel length of 1.5 micron ; using a junction isolation technique it has been possible to mix on the same chip Bipolar and CMOS transistors along with the DMOS power components(Fig. 2). Figure 1 shows how this process brings a rapid increase in power IC complexity compared to conventionalbipolartechnology. In the 70’s class B circuits and DC circuits al- lowed output power in the range of 70W. By 1980, with the introduction of switching tech- niques in power ICs, output powers up to 200W were reached ; with BCD technology the output powerincreasedup to 400W. AN557/1297 The L497XA series of highcurrent switching regulator ICs exploit Multipower-BCD technologyto achieve very high output currents with low power dissipation – up to 10A in the Multiwatt power package and 3.5A in a DIP package . 1/47

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8192019 L4970A Design Considerations

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APPLICATION NOTE

EASY APPLICATION DESIGN WITH THE L4970AMONOLITHIC DC-DC CONVERTERS FAMILYby G Gattavari and C Diazzi

THE TECHNOLOGY

The technology architecture is basedon the verti-cal DMOS silicon gate process that allows achannel length of 15 micron using a junctionisolation technique it has been possible to mix onthe same chip Bipolar and CMOS transistorsalong with the DMOS power components(Fig 2)Figure 1 shows how this process brings a rapid

increase in power IC complexity compared toconventionalbipolar technology

In the 70rsquos class B circuits and DC circuits al-lowed output power in the range of 70W By1980 with the introduction of switching tech-niques in power ICs output powers up to 200Wwere reached with BCD technology the outputpower increased up to 400W

AN5571297

The L497XA series of high current switching regulator ICs exploit Multipower-BCD technology to achieve very high output currents with low power dissipation ndash up to 10A in the Multiwatt power package and 35A in a DIP package

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8192019 L4970A Design Considerations

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THE STEP-DOWN CONFIGURATION

Fig 3 shows the simplified block diagram of thecircuit realizing the step-down configuration Thiscircuit operates as follows Q1 acts as a switch atthe frequency f and the ON and OFF times aresuitably controlled by the pulse width modulatorcircuit When Q1 is saturated energy is absorbedfrom the input which is transferred to the outputthrough L The emitter voltage of Q1 VE is Vi-Vsat when Q is ON and -VF ( with VF the forward

voltage across the D diode as indicated) when Q1is OFF During this second phase the current cir-culates again through L and D Consequently arectangular shaped voltage appears on the emit-ter of Q1 and this is then filtered by the L-C-D net-work and converted into a continuousmean valueacross the capacitor C and therefore across theload The current through L consists of a continu-ous component ILOAD and a triangular-shapedcomponent super-imposed on it ∆IL due to thevoltage across L

Figure 1 BCD process and increase in power ICs complexity

Figure 2 Cross Section of the BCD Mixed Technology

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 4 shows the behaviour of the most significantwaveforms in different points of the circuit whichhelp to understand better the operation of thepower section of the switching regulator For thesake of simplicity the series resistance of the coilhas been neglected Fig 2a shows the behaviourof the emitter voltage (which is practically the volt-age across the recirculation diode) where thepower saturation and the forward VF drop acrossthe diode era taken into account

The ON and OFF timesare establishedby the fol-lowing expression

Vo = (Vi minus Vsat)TON

TON + TOFF

Fig 4b shows the current across the switchingtransistor The current shape is trapezoidal andthe operation is in continuousmode At this stagethe phenomena due to the catch diode that weconsider as dynamically ideal are neglected Fig4c shows the current circulating in the recircula-tion diode The sum of the currents circulating inthe power and in the diode is the current circulat-ing in the coil as shown in Fig 4e In balancedconditions the ∆IL

+current increase occuring dur-

ing TON has to be equal to the ∆IL ndash

decrease oc-curring during TOFF The mean value of IL corre-sponds to the charge current

The current ripple is given by the following for-mula

∆ IL+ = ∆ IL

minus = (Vi minus Vsat) minus VO

L TON =

Vo + VF

L TOFF

It is a good rule to respect to IoMIN ge IL 2 relation-ship that implies good operation in continuousmode When this is not done the regulator startsoperating in discontinuous mode This operationis still safe but variations of the switching fre-quency may occur and the output regulation de-creases

Fig 4d shows the behaviourof the voltage acrosscoil L In balanced conditions the mean value ofthe voltage across the coil is zero Fig 4f showsthe current flowing through the capacitor which isthe differencebetween IL and ILOAD

In balanced conditions the mean current is equalto zero and ∆IC = ∆IL The current IC through thecapacitor givesrise to the voltage rippleThis ripple consists of two components a capaci-tive component ∆VC and a resistive component∆VESR due to the ESR equivalent series resis-tance of the capacitor Fig 4g shows the capaci-tive component ∆VC of the voltage ripple which isthe integral of a triangular-shaped current as afunction of time Moreover it should be observedthat vC (t) is in quadrature with iC(t) and thereforewith the voltage VESR The quantity of charge ∆Q+

supplied to the capacitor is given by the area en-closedby the ABC triangle in Fig 4f

Figure 3 The Basic Step-down Switching RegulatorConfiguration

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8192019 L4970A Design Considerations

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Figure 4 Principal Circuit Waveforms of the figure 1 Circuit

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8192019 L4970A Design Considerations

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∆Q = 1

2 sdot T

2 sdot ∆IL

2

Which therefore gives

∆VC = Q

C =

∆IL8fc

Fig 4h shows the voltage ripple VESR due to theresistive component of the capacitorThis compo-nent is VESR (t) = iC (t) sdot ESR Fig 4i shows theoverall ripple Vo which is the sum of the two pre-vious components As the frequency increases (gt20kHz) which is required to reduce both the costand the sizes of L and C the VESR componentbecomes dominant Often it is necessary to usecapacitors with greater capacitance (or more ca-pacitors connected in parallel to limit the value ofESR within the requiredlevelWe will now examine the stepdown configurationin more detail referring to fig 1 and taking the be-haviour shown in Fig 4 intoaccount

Starting from the initial conditions where Q = ONvC = Vo and iL = iD = 0 using Kirckoff secondprin-ciple we may write the followingexpression

Vi = vL + vC (Vsat is neglectedagainst Vi)

Vi = L dIL

dt + vC = L

dIL

dt + Vo (1)

which gives

dIL

dt =

(Vi minus Vo)

L (2)

The current through the inductance is given by

IL = (Vi minus Vo)

L (3)

When Vi Vo and L are constant IL varies linearlywith t Therefore it follows that

∆IL+ =

(Vi minus Vo) TON

L

(4)

When Q is OFF the current through the coil hasreached its maximum value Ipeak and because itcannot very instantaneously the voltage acrossthe ased to allow the recirculation of the currentthroughthe load

When Q switches OFF the following situation ispresent

vC(t) = Vo iL (t) = iD (t) = Ipeak

And the equation associated to the following loopmay be written

VF + L dIL

dt + vC = 0 (5)

where

vC = Vo

dILdt

= minus (VF + Vo) L (6)

It follows therefore that

iL (t) = minus VF + Vo

T t (7)

The negative sign may be interpretated with thefact that the current is now decreasing Assumingthat VF may be neglected against Vo during the

OFF time the followingbehaviour occurs

IL = Vo

L t (8)

therefore

∆IL+

= Vo

L TOFF (9)

But because

∆IL+

= ∆IL ndash

if followsthat

(Vi minus Vo) TONL = Vo TOFF

L

which allows us to calculate Vo

Vo = ViTON

TON TOFF= Vi

TON

T (10)

where T is the switching period

Expression (10) links the output voltage Vo to theinput voltage Vi and to the duty cycle The rela-tion-shipbetween the currents is the following

IiDC = IoDC sdot TON

T

EFFICIENCY

The system efficiency is expressed by the follow-ing formula

η = Po

Pisdot 100

where Po = VoIo (with Io = ILOAD)

is the output power to the load and P i is the inputpower absorbed by the system Pi is given by Po

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8192019 L4970A Design Considerations

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plus all the other system losses The expressionof the efficiencybecomes therefore the following

η = Po

Po + Psat + PD + PL + Pq + psw

(12)

DC LOSSES

Psat saturation losses of the power transistor QThese losses increase as Vi decreases

Psat = Vsat sdot IoTON

T + Vsat Io

Vo

Vi(13)

where TON

T =

Vo

Viand Vsat is the power

transistorsaturation at current Io

PD losses due to the recirculationdiodeThese losses increase as Vi increasesas inthis case the ON time of the diode is greater

PD = VF IoVi minus Vo

Vi= VFIo (1 minus

Vo

Vi) (14)

where VF is the forward voltage of the recircula-tion diode at current Io

PL losses due to theseries resistance RS of thecoil

PL = RS Io2

(15)

Pq losses due to the stand-by current and to thepower driving current

Pq = Vi Iq (16)

in which Iq is the operating supply current at theoperating switching frequencyIq includes the oscillator current

SWITCHING LOSSES

Psw switching losses of the power transistor

Psw = Vi Iotr + tf2T

The switching losses of the recirculation diode areneglected (which are anyway negligible) as it isassumed that diode is used with recovery timemuch smaller than the rise time of the power tran-sistor

We can neglect losses in the coil (it is assumedthat ∆IL is very small compared to Io) and in theoutput capacitor which is assumed to show a lowESR

Calculationof the inductance value L

Calculation TON and TOFF through (4) and (9) re-spectively it follows that

TON = ∆IL+

sdot LVi minus VoTOFF = ∆IL

minus

sdot LVo

But because

TON + TOFF = T and ∆IL+

= ∆IL ndash

= ∆IL

it follows that

TON = ∆IL sdot LVi minus Vo

+ ∆IL sdot L

Vo= T (17)

Calculating L the previous relation becomes

L = (Vi minus Vo) Vo

Vi ∆ ILT (18)

Fixing the current ripple in the coil required by thedesign (for instance 30 of Io) and introducingthe frequency instead of the period it follows that

L = (Vi minus Vo) Vo

Vi sdot 03 sdot Io sdot f where L is in Henry and f in Hz

Calculationof the output capacitor C

From the outputnode in fig 3 it may be seen that

the current through the output capacitor is givenby

ic (t) = iL (t) ndash Io

Figure 5 EquivalentCircuit ShowingRecirculation when Q1 is Turned Off

APPLICATION NOTE

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8192019 L4970A Design Considerations

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From the behaviour shown in Fig 4 it may be cal-culated that the charge current of the output ca-pacitor within a period is ∆IL 4 which is suppliedfor a time T2 It follows therefore that

∆ VC = ∆IL

4C

T2

= ∆ IL T

8C =

∆ IL8fc

(19)

but remembering expression(4)

∆IL+ = (Vi minus Vo) TON

L and TON =

Vo

ViT

thereforeequation (19) becomes

∆ VC = (Vi minus Vo) Vo

8 Vi f2 L C

Finally calculating C it follows that

C = (Vi minus Vo) Vo

8 Vi ∆VC f2

L(20)

where L is in HenrysC is in Faradsf is in Hz

Finally the followingexpressionshould be true

ESRmax = ∆VCmax

∆IL(21)

It may happen that to satisfy relation (21) a ca-pacitance value much greater than the value cal-culated through (20) must be used

TRANSIENT RESPONSE

Sudden variations of the load current give rise toovervoltages and undervoltages on the outputvoltage Since ic = C (dvc dt) (22) where dvc =∆Vo the instantaneous variation of the load cur-rent ∆Io is supplied during the transient by theoutput capacitor During the transient also cur-rent through the coil tends to change its valueMoreover the following is true

vL = L diLdt

(23)

where diL = ∆Io

vL = Vi ndash Vo for a load increase

vL = Vo for a loaddecrease

Calculating dt from (22) and (23) and equalizingit follows that

L diLvL

= C dvC

iC

Calculating dvc and equalizing it to ∆Vo it followsthat

∆Vo = L∆Io

2

C (Vi minus Vo)

(24) for + ∆Io

∆Vo = L∆Io

2

C Vo(25) for - ∆Io

From these two expressions the dependence ofovershoots and undershoots on the L and C val-ues may be observedTo minimize ∆Vo it is there-fore necessary to reduce the inductance value Land to increase the capacitance value C Shouldother auxiliary functions be required in the circuitlike reset or crowbarprotections and very variableloadsmay be present it is worthwhile to take spe-cial care for minimizing these overshoots whichcould cause spurious operation of the crowbar

and the under-shoot which could trigger the resetfunction

DEVICE DESCRIPTION

For a better understanding of how the devicefunctions a descriptionwill be given of the princi-ple blocks that compose the device The blockdiagram of the device is shown in fig6

POWER SUPPLY

The device contains a stabilized regulator (Vstart= 12V) that provides power to the analogic anddigital control blocks as well as the section of thebootstrap The Vstart voltage also powers theblocks that operates the internal reference volt-age of 51V with a precision of +2 necessaryfor the feedback

OSCILLATOR SYNC AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wavesignal that sets the switching frequency of the

system This signal compared with the outputvoltage of the error amplifier generates the PWMsignal that will then sent to the power outputstage The oscillator also contains the voltagefeedforward function that being completely inte-grated does not require additional external com-ponents to function The VFF function operateswith supply voltages from 15V to 45V The ∆V ∆tof the sawtooh is directly proportional to the sup-ply voltage Vi

As Vi increases the conduction time (ton) of thepower transistor decreases in such way as to pro-vide to the coil and therefore to the load theproduct Volt x Sec constant

APPLICATION NOTE

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

APPLICATION NOTE

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

APPLICATION NOTE

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 2: L4970A Design Considerations

8192019 L4970A Design Considerations

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THE STEP-DOWN CONFIGURATION

Fig 3 shows the simplified block diagram of thecircuit realizing the step-down configuration Thiscircuit operates as follows Q1 acts as a switch atthe frequency f and the ON and OFF times aresuitably controlled by the pulse width modulatorcircuit When Q1 is saturated energy is absorbedfrom the input which is transferred to the outputthrough L The emitter voltage of Q1 VE is Vi-Vsat when Q is ON and -VF ( with VF the forward

voltage across the D diode as indicated) when Q1is OFF During this second phase the current cir-culates again through L and D Consequently arectangular shaped voltage appears on the emit-ter of Q1 and this is then filtered by the L-C-D net-work and converted into a continuousmean valueacross the capacitor C and therefore across theload The current through L consists of a continu-ous component ILOAD and a triangular-shapedcomponent super-imposed on it ∆IL due to thevoltage across L

Figure 1 BCD process and increase in power ICs complexity

Figure 2 Cross Section of the BCD Mixed Technology

APPLICATION NOTE

247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 347

Fig 4 shows the behaviour of the most significantwaveforms in different points of the circuit whichhelp to understand better the operation of thepower section of the switching regulator For thesake of simplicity the series resistance of the coilhas been neglected Fig 2a shows the behaviourof the emitter voltage (which is practically the volt-age across the recirculation diode) where thepower saturation and the forward VF drop acrossthe diode era taken into account

The ON and OFF timesare establishedby the fol-lowing expression

Vo = (Vi minus Vsat)TON

TON + TOFF

Fig 4b shows the current across the switchingtransistor The current shape is trapezoidal andthe operation is in continuousmode At this stagethe phenomena due to the catch diode that weconsider as dynamically ideal are neglected Fig4c shows the current circulating in the recircula-tion diode The sum of the currents circulating inthe power and in the diode is the current circulat-ing in the coil as shown in Fig 4e In balancedconditions the ∆IL

+current increase occuring dur-

ing TON has to be equal to the ∆IL ndash

decrease oc-curring during TOFF The mean value of IL corre-sponds to the charge current

The current ripple is given by the following for-mula

∆ IL+ = ∆ IL

minus = (Vi minus Vsat) minus VO

L TON =

Vo + VF

L TOFF

It is a good rule to respect to IoMIN ge IL 2 relation-ship that implies good operation in continuousmode When this is not done the regulator startsoperating in discontinuous mode This operationis still safe but variations of the switching fre-quency may occur and the output regulation de-creases

Fig 4d shows the behaviourof the voltage acrosscoil L In balanced conditions the mean value ofthe voltage across the coil is zero Fig 4f showsthe current flowing through the capacitor which isthe differencebetween IL and ILOAD

In balanced conditions the mean current is equalto zero and ∆IC = ∆IL The current IC through thecapacitor givesrise to the voltage rippleThis ripple consists of two components a capaci-tive component ∆VC and a resistive component∆VESR due to the ESR equivalent series resis-tance of the capacitor Fig 4g shows the capaci-tive component ∆VC of the voltage ripple which isthe integral of a triangular-shaped current as afunction of time Moreover it should be observedthat vC (t) is in quadrature with iC(t) and thereforewith the voltage VESR The quantity of charge ∆Q+

supplied to the capacitor is given by the area en-closedby the ABC triangle in Fig 4f

Figure 3 The Basic Step-down Switching RegulatorConfiguration

APPLICATION NOTE

347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 447

Figure 4 Principal Circuit Waveforms of the figure 1 Circuit

APPLICATION NOTE

447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 547

∆Q = 1

2 sdot T

2 sdot ∆IL

2

Which therefore gives

∆VC = Q

C =

∆IL8fc

Fig 4h shows the voltage ripple VESR due to theresistive component of the capacitorThis compo-nent is VESR (t) = iC (t) sdot ESR Fig 4i shows theoverall ripple Vo which is the sum of the two pre-vious components As the frequency increases (gt20kHz) which is required to reduce both the costand the sizes of L and C the VESR componentbecomes dominant Often it is necessary to usecapacitors with greater capacitance (or more ca-pacitors connected in parallel to limit the value ofESR within the requiredlevelWe will now examine the stepdown configurationin more detail referring to fig 1 and taking the be-haviour shown in Fig 4 intoaccount

Starting from the initial conditions where Q = ONvC = Vo and iL = iD = 0 using Kirckoff secondprin-ciple we may write the followingexpression

Vi = vL + vC (Vsat is neglectedagainst Vi)

Vi = L dIL

dt + vC = L

dIL

dt + Vo (1)

which gives

dIL

dt =

(Vi minus Vo)

L (2)

The current through the inductance is given by

IL = (Vi minus Vo)

L (3)

When Vi Vo and L are constant IL varies linearlywith t Therefore it follows that

∆IL+ =

(Vi minus Vo) TON

L

(4)

When Q is OFF the current through the coil hasreached its maximum value Ipeak and because itcannot very instantaneously the voltage acrossthe ased to allow the recirculation of the currentthroughthe load

When Q switches OFF the following situation ispresent

vC(t) = Vo iL (t) = iD (t) = Ipeak

And the equation associated to the following loopmay be written

VF + L dIL

dt + vC = 0 (5)

where

vC = Vo

dILdt

= minus (VF + Vo) L (6)

It follows therefore that

iL (t) = minus VF + Vo

T t (7)

The negative sign may be interpretated with thefact that the current is now decreasing Assumingthat VF may be neglected against Vo during the

OFF time the followingbehaviour occurs

IL = Vo

L t (8)

therefore

∆IL+

= Vo

L TOFF (9)

But because

∆IL+

= ∆IL ndash

if followsthat

(Vi minus Vo) TONL = Vo TOFF

L

which allows us to calculate Vo

Vo = ViTON

TON TOFF= Vi

TON

T (10)

where T is the switching period

Expression (10) links the output voltage Vo to theinput voltage Vi and to the duty cycle The rela-tion-shipbetween the currents is the following

IiDC = IoDC sdot TON

T

EFFICIENCY

The system efficiency is expressed by the follow-ing formula

η = Po

Pisdot 100

where Po = VoIo (with Io = ILOAD)

is the output power to the load and P i is the inputpower absorbed by the system Pi is given by Po

APPLICATION NOTE

547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 647

plus all the other system losses The expressionof the efficiencybecomes therefore the following

η = Po

Po + Psat + PD + PL + Pq + psw

(12)

DC LOSSES

Psat saturation losses of the power transistor QThese losses increase as Vi decreases

Psat = Vsat sdot IoTON

T + Vsat Io

Vo

Vi(13)

where TON

T =

Vo

Viand Vsat is the power

transistorsaturation at current Io

PD losses due to the recirculationdiodeThese losses increase as Vi increasesas inthis case the ON time of the diode is greater

PD = VF IoVi minus Vo

Vi= VFIo (1 minus

Vo

Vi) (14)

where VF is the forward voltage of the recircula-tion diode at current Io

PL losses due to theseries resistance RS of thecoil

PL = RS Io2

(15)

Pq losses due to the stand-by current and to thepower driving current

Pq = Vi Iq (16)

in which Iq is the operating supply current at theoperating switching frequencyIq includes the oscillator current

SWITCHING LOSSES

Psw switching losses of the power transistor

Psw = Vi Iotr + tf2T

The switching losses of the recirculation diode areneglected (which are anyway negligible) as it isassumed that diode is used with recovery timemuch smaller than the rise time of the power tran-sistor

We can neglect losses in the coil (it is assumedthat ∆IL is very small compared to Io) and in theoutput capacitor which is assumed to show a lowESR

Calculationof the inductance value L

Calculation TON and TOFF through (4) and (9) re-spectively it follows that

TON = ∆IL+

sdot LVi minus VoTOFF = ∆IL

minus

sdot LVo

But because

TON + TOFF = T and ∆IL+

= ∆IL ndash

= ∆IL

it follows that

TON = ∆IL sdot LVi minus Vo

+ ∆IL sdot L

Vo= T (17)

Calculating L the previous relation becomes

L = (Vi minus Vo) Vo

Vi ∆ ILT (18)

Fixing the current ripple in the coil required by thedesign (for instance 30 of Io) and introducingthe frequency instead of the period it follows that

L = (Vi minus Vo) Vo

Vi sdot 03 sdot Io sdot f where L is in Henry and f in Hz

Calculationof the output capacitor C

From the outputnode in fig 3 it may be seen that

the current through the output capacitor is givenby

ic (t) = iL (t) ndash Io

Figure 5 EquivalentCircuit ShowingRecirculation when Q1 is Turned Off

APPLICATION NOTE

647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 747

From the behaviour shown in Fig 4 it may be cal-culated that the charge current of the output ca-pacitor within a period is ∆IL 4 which is suppliedfor a time T2 It follows therefore that

∆ VC = ∆IL

4C

T2

= ∆ IL T

8C =

∆ IL8fc

(19)

but remembering expression(4)

∆IL+ = (Vi minus Vo) TON

L and TON =

Vo

ViT

thereforeequation (19) becomes

∆ VC = (Vi minus Vo) Vo

8 Vi f2 L C

Finally calculating C it follows that

C = (Vi minus Vo) Vo

8 Vi ∆VC f2

L(20)

where L is in HenrysC is in Faradsf is in Hz

Finally the followingexpressionshould be true

ESRmax = ∆VCmax

∆IL(21)

It may happen that to satisfy relation (21) a ca-pacitance value much greater than the value cal-culated through (20) must be used

TRANSIENT RESPONSE

Sudden variations of the load current give rise toovervoltages and undervoltages on the outputvoltage Since ic = C (dvc dt) (22) where dvc =∆Vo the instantaneous variation of the load cur-rent ∆Io is supplied during the transient by theoutput capacitor During the transient also cur-rent through the coil tends to change its valueMoreover the following is true

vL = L diLdt

(23)

where diL = ∆Io

vL = Vi ndash Vo for a load increase

vL = Vo for a loaddecrease

Calculating dt from (22) and (23) and equalizingit follows that

L diLvL

= C dvC

iC

Calculating dvc and equalizing it to ∆Vo it followsthat

∆Vo = L∆Io

2

C (Vi minus Vo)

(24) for + ∆Io

∆Vo = L∆Io

2

C Vo(25) for - ∆Io

From these two expressions the dependence ofovershoots and undershoots on the L and C val-ues may be observedTo minimize ∆Vo it is there-fore necessary to reduce the inductance value Land to increase the capacitance value C Shouldother auxiliary functions be required in the circuitlike reset or crowbarprotections and very variableloadsmay be present it is worthwhile to take spe-cial care for minimizing these overshoots whichcould cause spurious operation of the crowbar

and the under-shoot which could trigger the resetfunction

DEVICE DESCRIPTION

For a better understanding of how the devicefunctions a descriptionwill be given of the princi-ple blocks that compose the device The blockdiagram of the device is shown in fig6

POWER SUPPLY

The device contains a stabilized regulator (Vstart= 12V) that provides power to the analogic anddigital control blocks as well as the section of thebootstrap The Vstart voltage also powers theblocks that operates the internal reference volt-age of 51V with a precision of +2 necessaryfor the feedback

OSCILLATOR SYNC AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wavesignal that sets the switching frequency of the

system This signal compared with the outputvoltage of the error amplifier generates the PWMsignal that will then sent to the power outputstage The oscillator also contains the voltagefeedforward function that being completely inte-grated does not require additional external com-ponents to function The VFF function operateswith supply voltages from 15V to 45V The ∆V ∆tof the sawtooh is directly proportional to the sup-ply voltage Vi

As Vi increases the conduction time (ton) of thepower transistor decreases in such way as to pro-vide to the coil and therefore to the load theproduct Volt x Sec constant

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3347

CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 4 shows the behaviour of the most significantwaveforms in different points of the circuit whichhelp to understand better the operation of thepower section of the switching regulator For thesake of simplicity the series resistance of the coilhas been neglected Fig 2a shows the behaviourof the emitter voltage (which is practically the volt-age across the recirculation diode) where thepower saturation and the forward VF drop acrossthe diode era taken into account

The ON and OFF timesare establishedby the fol-lowing expression

Vo = (Vi minus Vsat)TON

TON + TOFF

Fig 4b shows the current across the switchingtransistor The current shape is trapezoidal andthe operation is in continuousmode At this stagethe phenomena due to the catch diode that weconsider as dynamically ideal are neglected Fig4c shows the current circulating in the recircula-tion diode The sum of the currents circulating inthe power and in the diode is the current circulat-ing in the coil as shown in Fig 4e In balancedconditions the ∆IL

+current increase occuring dur-

ing TON has to be equal to the ∆IL ndash

decrease oc-curring during TOFF The mean value of IL corre-sponds to the charge current

The current ripple is given by the following for-mula

∆ IL+ = ∆ IL

minus = (Vi minus Vsat) minus VO

L TON =

Vo + VF

L TOFF

It is a good rule to respect to IoMIN ge IL 2 relation-ship that implies good operation in continuousmode When this is not done the regulator startsoperating in discontinuous mode This operationis still safe but variations of the switching fre-quency may occur and the output regulation de-creases

Fig 4d shows the behaviourof the voltage acrosscoil L In balanced conditions the mean value ofthe voltage across the coil is zero Fig 4f showsthe current flowing through the capacitor which isthe differencebetween IL and ILOAD

In balanced conditions the mean current is equalto zero and ∆IC = ∆IL The current IC through thecapacitor givesrise to the voltage rippleThis ripple consists of two components a capaci-tive component ∆VC and a resistive component∆VESR due to the ESR equivalent series resis-tance of the capacitor Fig 4g shows the capaci-tive component ∆VC of the voltage ripple which isthe integral of a triangular-shaped current as afunction of time Moreover it should be observedthat vC (t) is in quadrature with iC(t) and thereforewith the voltage VESR The quantity of charge ∆Q+

supplied to the capacitor is given by the area en-closedby the ABC triangle in Fig 4f

Figure 3 The Basic Step-down Switching RegulatorConfiguration

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 4 Principal Circuit Waveforms of the figure 1 Circuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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∆Q = 1

2 sdot T

2 sdot ∆IL

2

Which therefore gives

∆VC = Q

C =

∆IL8fc

Fig 4h shows the voltage ripple VESR due to theresistive component of the capacitorThis compo-nent is VESR (t) = iC (t) sdot ESR Fig 4i shows theoverall ripple Vo which is the sum of the two pre-vious components As the frequency increases (gt20kHz) which is required to reduce both the costand the sizes of L and C the VESR componentbecomes dominant Often it is necessary to usecapacitors with greater capacitance (or more ca-pacitors connected in parallel to limit the value ofESR within the requiredlevelWe will now examine the stepdown configurationin more detail referring to fig 1 and taking the be-haviour shown in Fig 4 intoaccount

Starting from the initial conditions where Q = ONvC = Vo and iL = iD = 0 using Kirckoff secondprin-ciple we may write the followingexpression

Vi = vL + vC (Vsat is neglectedagainst Vi)

Vi = L dIL

dt + vC = L

dIL

dt + Vo (1)

which gives

dIL

dt =

(Vi minus Vo)

L (2)

The current through the inductance is given by

IL = (Vi minus Vo)

L (3)

When Vi Vo and L are constant IL varies linearlywith t Therefore it follows that

∆IL+ =

(Vi minus Vo) TON

L

(4)

When Q is OFF the current through the coil hasreached its maximum value Ipeak and because itcannot very instantaneously the voltage acrossthe ased to allow the recirculation of the currentthroughthe load

When Q switches OFF the following situation ispresent

vC(t) = Vo iL (t) = iD (t) = Ipeak

And the equation associated to the following loopmay be written

VF + L dIL

dt + vC = 0 (5)

where

vC = Vo

dILdt

= minus (VF + Vo) L (6)

It follows therefore that

iL (t) = minus VF + Vo

T t (7)

The negative sign may be interpretated with thefact that the current is now decreasing Assumingthat VF may be neglected against Vo during the

OFF time the followingbehaviour occurs

IL = Vo

L t (8)

therefore

∆IL+

= Vo

L TOFF (9)

But because

∆IL+

= ∆IL ndash

if followsthat

(Vi minus Vo) TONL = Vo TOFF

L

which allows us to calculate Vo

Vo = ViTON

TON TOFF= Vi

TON

T (10)

where T is the switching period

Expression (10) links the output voltage Vo to theinput voltage Vi and to the duty cycle The rela-tion-shipbetween the currents is the following

IiDC = IoDC sdot TON

T

EFFICIENCY

The system efficiency is expressed by the follow-ing formula

η = Po

Pisdot 100

where Po = VoIo (with Io = ILOAD)

is the output power to the load and P i is the inputpower absorbed by the system Pi is given by Po

APPLICATION NOTE

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8192019 L4970A Design Considerations

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plus all the other system losses The expressionof the efficiencybecomes therefore the following

η = Po

Po + Psat + PD + PL + Pq + psw

(12)

DC LOSSES

Psat saturation losses of the power transistor QThese losses increase as Vi decreases

Psat = Vsat sdot IoTON

T + Vsat Io

Vo

Vi(13)

where TON

T =

Vo

Viand Vsat is the power

transistorsaturation at current Io

PD losses due to the recirculationdiodeThese losses increase as Vi increasesas inthis case the ON time of the diode is greater

PD = VF IoVi minus Vo

Vi= VFIo (1 minus

Vo

Vi) (14)

where VF is the forward voltage of the recircula-tion diode at current Io

PL losses due to theseries resistance RS of thecoil

PL = RS Io2

(15)

Pq losses due to the stand-by current and to thepower driving current

Pq = Vi Iq (16)

in which Iq is the operating supply current at theoperating switching frequencyIq includes the oscillator current

SWITCHING LOSSES

Psw switching losses of the power transistor

Psw = Vi Iotr + tf2T

The switching losses of the recirculation diode areneglected (which are anyway negligible) as it isassumed that diode is used with recovery timemuch smaller than the rise time of the power tran-sistor

We can neglect losses in the coil (it is assumedthat ∆IL is very small compared to Io) and in theoutput capacitor which is assumed to show a lowESR

Calculationof the inductance value L

Calculation TON and TOFF through (4) and (9) re-spectively it follows that

TON = ∆IL+

sdot LVi minus VoTOFF = ∆IL

minus

sdot LVo

But because

TON + TOFF = T and ∆IL+

= ∆IL ndash

= ∆IL

it follows that

TON = ∆IL sdot LVi minus Vo

+ ∆IL sdot L

Vo= T (17)

Calculating L the previous relation becomes

L = (Vi minus Vo) Vo

Vi ∆ ILT (18)

Fixing the current ripple in the coil required by thedesign (for instance 30 of Io) and introducingthe frequency instead of the period it follows that

L = (Vi minus Vo) Vo

Vi sdot 03 sdot Io sdot f where L is in Henry and f in Hz

Calculationof the output capacitor C

From the outputnode in fig 3 it may be seen that

the current through the output capacitor is givenby

ic (t) = iL (t) ndash Io

Figure 5 EquivalentCircuit ShowingRecirculation when Q1 is Turned Off

APPLICATION NOTE

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From the behaviour shown in Fig 4 it may be cal-culated that the charge current of the output ca-pacitor within a period is ∆IL 4 which is suppliedfor a time T2 It follows therefore that

∆ VC = ∆IL

4C

T2

= ∆ IL T

8C =

∆ IL8fc

(19)

but remembering expression(4)

∆IL+ = (Vi minus Vo) TON

L and TON =

Vo

ViT

thereforeequation (19) becomes

∆ VC = (Vi minus Vo) Vo

8 Vi f2 L C

Finally calculating C it follows that

C = (Vi minus Vo) Vo

8 Vi ∆VC f2

L(20)

where L is in HenrysC is in Faradsf is in Hz

Finally the followingexpressionshould be true

ESRmax = ∆VCmax

∆IL(21)

It may happen that to satisfy relation (21) a ca-pacitance value much greater than the value cal-culated through (20) must be used

TRANSIENT RESPONSE

Sudden variations of the load current give rise toovervoltages and undervoltages on the outputvoltage Since ic = C (dvc dt) (22) where dvc =∆Vo the instantaneous variation of the load cur-rent ∆Io is supplied during the transient by theoutput capacitor During the transient also cur-rent through the coil tends to change its valueMoreover the following is true

vL = L diLdt

(23)

where diL = ∆Io

vL = Vi ndash Vo for a load increase

vL = Vo for a loaddecrease

Calculating dt from (22) and (23) and equalizingit follows that

L diLvL

= C dvC

iC

Calculating dvc and equalizing it to ∆Vo it followsthat

∆Vo = L∆Io

2

C (Vi minus Vo)

(24) for + ∆Io

∆Vo = L∆Io

2

C Vo(25) for - ∆Io

From these two expressions the dependence ofovershoots and undershoots on the L and C val-ues may be observedTo minimize ∆Vo it is there-fore necessary to reduce the inductance value Land to increase the capacitance value C Shouldother auxiliary functions be required in the circuitlike reset or crowbarprotections and very variableloadsmay be present it is worthwhile to take spe-cial care for minimizing these overshoots whichcould cause spurious operation of the crowbar

and the under-shoot which could trigger the resetfunction

DEVICE DESCRIPTION

For a better understanding of how the devicefunctions a descriptionwill be given of the princi-ple blocks that compose the device The blockdiagram of the device is shown in fig6

POWER SUPPLY

The device contains a stabilized regulator (Vstart= 12V) that provides power to the analogic anddigital control blocks as well as the section of thebootstrap The Vstart voltage also powers theblocks that operates the internal reference volt-age of 51V with a precision of +2 necessaryfor the feedback

OSCILLATOR SYNC AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wavesignal that sets the switching frequency of the

system This signal compared with the outputvoltage of the error amplifier generates the PWMsignal that will then sent to the power outputstage The oscillator also contains the voltagefeedforward function that being completely inte-grated does not require additional external com-ponents to function The VFF function operateswith supply voltages from 15V to 45V The ∆V ∆tof the sawtooh is directly proportional to the sup-ply voltage Vi

As Vi increases the conduction time (ton) of thepower transistor decreases in such way as to pro-vide to the coil and therefore to the load theproduct Volt x Sec constant

APPLICATION NOTE

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

APPLICATION NOTE

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8192019 L4970A Design Considerations

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

APPLICATION NOTE

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

APPLICATION NOTE

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

APPLICATION NOTE

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

APPLICATION NOTE

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 4: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 447

Figure 4 Principal Circuit Waveforms of the figure 1 Circuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 547

∆Q = 1

2 sdot T

2 sdot ∆IL

2

Which therefore gives

∆VC = Q

C =

∆IL8fc

Fig 4h shows the voltage ripple VESR due to theresistive component of the capacitorThis compo-nent is VESR (t) = iC (t) sdot ESR Fig 4i shows theoverall ripple Vo which is the sum of the two pre-vious components As the frequency increases (gt20kHz) which is required to reduce both the costand the sizes of L and C the VESR componentbecomes dominant Often it is necessary to usecapacitors with greater capacitance (or more ca-pacitors connected in parallel to limit the value ofESR within the requiredlevelWe will now examine the stepdown configurationin more detail referring to fig 1 and taking the be-haviour shown in Fig 4 intoaccount

Starting from the initial conditions where Q = ONvC = Vo and iL = iD = 0 using Kirckoff secondprin-ciple we may write the followingexpression

Vi = vL + vC (Vsat is neglectedagainst Vi)

Vi = L dIL

dt + vC = L

dIL

dt + Vo (1)

which gives

dIL

dt =

(Vi minus Vo)

L (2)

The current through the inductance is given by

IL = (Vi minus Vo)

L (3)

When Vi Vo and L are constant IL varies linearlywith t Therefore it follows that

∆IL+ =

(Vi minus Vo) TON

L

(4)

When Q is OFF the current through the coil hasreached its maximum value Ipeak and because itcannot very instantaneously the voltage acrossthe ased to allow the recirculation of the currentthroughthe load

When Q switches OFF the following situation ispresent

vC(t) = Vo iL (t) = iD (t) = Ipeak

And the equation associated to the following loopmay be written

VF + L dIL

dt + vC = 0 (5)

where

vC = Vo

dILdt

= minus (VF + Vo) L (6)

It follows therefore that

iL (t) = minus VF + Vo

T t (7)

The negative sign may be interpretated with thefact that the current is now decreasing Assumingthat VF may be neglected against Vo during the

OFF time the followingbehaviour occurs

IL = Vo

L t (8)

therefore

∆IL+

= Vo

L TOFF (9)

But because

∆IL+

= ∆IL ndash

if followsthat

(Vi minus Vo) TONL = Vo TOFF

L

which allows us to calculate Vo

Vo = ViTON

TON TOFF= Vi

TON

T (10)

where T is the switching period

Expression (10) links the output voltage Vo to theinput voltage Vi and to the duty cycle The rela-tion-shipbetween the currents is the following

IiDC = IoDC sdot TON

T

EFFICIENCY

The system efficiency is expressed by the follow-ing formula

η = Po

Pisdot 100

where Po = VoIo (with Io = ILOAD)

is the output power to the load and P i is the inputpower absorbed by the system Pi is given by Po

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 647

plus all the other system losses The expressionof the efficiencybecomes therefore the following

η = Po

Po + Psat + PD + PL + Pq + psw

(12)

DC LOSSES

Psat saturation losses of the power transistor QThese losses increase as Vi decreases

Psat = Vsat sdot IoTON

T + Vsat Io

Vo

Vi(13)

where TON

T =

Vo

Viand Vsat is the power

transistorsaturation at current Io

PD losses due to the recirculationdiodeThese losses increase as Vi increasesas inthis case the ON time of the diode is greater

PD = VF IoVi minus Vo

Vi= VFIo (1 minus

Vo

Vi) (14)

where VF is the forward voltage of the recircula-tion diode at current Io

PL losses due to theseries resistance RS of thecoil

PL = RS Io2

(15)

Pq losses due to the stand-by current and to thepower driving current

Pq = Vi Iq (16)

in which Iq is the operating supply current at theoperating switching frequencyIq includes the oscillator current

SWITCHING LOSSES

Psw switching losses of the power transistor

Psw = Vi Iotr + tf2T

The switching losses of the recirculation diode areneglected (which are anyway negligible) as it isassumed that diode is used with recovery timemuch smaller than the rise time of the power tran-sistor

We can neglect losses in the coil (it is assumedthat ∆IL is very small compared to Io) and in theoutput capacitor which is assumed to show a lowESR

Calculationof the inductance value L

Calculation TON and TOFF through (4) and (9) re-spectively it follows that

TON = ∆IL+

sdot LVi minus VoTOFF = ∆IL

minus

sdot LVo

But because

TON + TOFF = T and ∆IL+

= ∆IL ndash

= ∆IL

it follows that

TON = ∆IL sdot LVi minus Vo

+ ∆IL sdot L

Vo= T (17)

Calculating L the previous relation becomes

L = (Vi minus Vo) Vo

Vi ∆ ILT (18)

Fixing the current ripple in the coil required by thedesign (for instance 30 of Io) and introducingthe frequency instead of the period it follows that

L = (Vi minus Vo) Vo

Vi sdot 03 sdot Io sdot f where L is in Henry and f in Hz

Calculationof the output capacitor C

From the outputnode in fig 3 it may be seen that

the current through the output capacitor is givenby

ic (t) = iL (t) ndash Io

Figure 5 EquivalentCircuit ShowingRecirculation when Q1 is Turned Off

APPLICATION NOTE

647

8192019 L4970A Design Considerations

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From the behaviour shown in Fig 4 it may be cal-culated that the charge current of the output ca-pacitor within a period is ∆IL 4 which is suppliedfor a time T2 It follows therefore that

∆ VC = ∆IL

4C

T2

= ∆ IL T

8C =

∆ IL8fc

(19)

but remembering expression(4)

∆IL+ = (Vi minus Vo) TON

L and TON =

Vo

ViT

thereforeequation (19) becomes

∆ VC = (Vi minus Vo) Vo

8 Vi f2 L C

Finally calculating C it follows that

C = (Vi minus Vo) Vo

8 Vi ∆VC f2

L(20)

where L is in HenrysC is in Faradsf is in Hz

Finally the followingexpressionshould be true

ESRmax = ∆VCmax

∆IL(21)

It may happen that to satisfy relation (21) a ca-pacitance value much greater than the value cal-culated through (20) must be used

TRANSIENT RESPONSE

Sudden variations of the load current give rise toovervoltages and undervoltages on the outputvoltage Since ic = C (dvc dt) (22) where dvc =∆Vo the instantaneous variation of the load cur-rent ∆Io is supplied during the transient by theoutput capacitor During the transient also cur-rent through the coil tends to change its valueMoreover the following is true

vL = L diLdt

(23)

where diL = ∆Io

vL = Vi ndash Vo for a load increase

vL = Vo for a loaddecrease

Calculating dt from (22) and (23) and equalizingit follows that

L diLvL

= C dvC

iC

Calculating dvc and equalizing it to ∆Vo it followsthat

∆Vo = L∆Io

2

C (Vi minus Vo)

(24) for + ∆Io

∆Vo = L∆Io

2

C Vo(25) for - ∆Io

From these two expressions the dependence ofovershoots and undershoots on the L and C val-ues may be observedTo minimize ∆Vo it is there-fore necessary to reduce the inductance value Land to increase the capacitance value C Shouldother auxiliary functions be required in the circuitlike reset or crowbarprotections and very variableloadsmay be present it is worthwhile to take spe-cial care for minimizing these overshoots whichcould cause spurious operation of the crowbar

and the under-shoot which could trigger the resetfunction

DEVICE DESCRIPTION

For a better understanding of how the devicefunctions a descriptionwill be given of the princi-ple blocks that compose the device The blockdiagram of the device is shown in fig6

POWER SUPPLY

The device contains a stabilized regulator (Vstart= 12V) that provides power to the analogic anddigital control blocks as well as the section of thebootstrap The Vstart voltage also powers theblocks that operates the internal reference volt-age of 51V with a precision of +2 necessaryfor the feedback

OSCILLATOR SYNC AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wavesignal that sets the switching frequency of the

system This signal compared with the outputvoltage of the error amplifier generates the PWMsignal that will then sent to the power outputstage The oscillator also contains the voltagefeedforward function that being completely inte-grated does not require additional external com-ponents to function The VFF function operateswith supply voltages from 15V to 45V The ∆V ∆tof the sawtooh is directly proportional to the sup-ply voltage Vi

As Vi increases the conduction time (ton) of thepower transistor decreases in such way as to pro-vide to the coil and therefore to the load theproduct Volt x Sec constant

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

APPLICATION NOTE

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

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8192019 L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

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8192019 L4970A Design Considerations

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∆Q = 1

2 sdot T

2 sdot ∆IL

2

Which therefore gives

∆VC = Q

C =

∆IL8fc

Fig 4h shows the voltage ripple VESR due to theresistive component of the capacitorThis compo-nent is VESR (t) = iC (t) sdot ESR Fig 4i shows theoverall ripple Vo which is the sum of the two pre-vious components As the frequency increases (gt20kHz) which is required to reduce both the costand the sizes of L and C the VESR componentbecomes dominant Often it is necessary to usecapacitors with greater capacitance (or more ca-pacitors connected in parallel to limit the value ofESR within the requiredlevelWe will now examine the stepdown configurationin more detail referring to fig 1 and taking the be-haviour shown in Fig 4 intoaccount

Starting from the initial conditions where Q = ONvC = Vo and iL = iD = 0 using Kirckoff secondprin-ciple we may write the followingexpression

Vi = vL + vC (Vsat is neglectedagainst Vi)

Vi = L dIL

dt + vC = L

dIL

dt + Vo (1)

which gives

dIL

dt =

(Vi minus Vo)

L (2)

The current through the inductance is given by

IL = (Vi minus Vo)

L (3)

When Vi Vo and L are constant IL varies linearlywith t Therefore it follows that

∆IL+ =

(Vi minus Vo) TON

L

(4)

When Q is OFF the current through the coil hasreached its maximum value Ipeak and because itcannot very instantaneously the voltage acrossthe ased to allow the recirculation of the currentthroughthe load

When Q switches OFF the following situation ispresent

vC(t) = Vo iL (t) = iD (t) = Ipeak

And the equation associated to the following loopmay be written

VF + L dIL

dt + vC = 0 (5)

where

vC = Vo

dILdt

= minus (VF + Vo) L (6)

It follows therefore that

iL (t) = minus VF + Vo

T t (7)

The negative sign may be interpretated with thefact that the current is now decreasing Assumingthat VF may be neglected against Vo during the

OFF time the followingbehaviour occurs

IL = Vo

L t (8)

therefore

∆IL+

= Vo

L TOFF (9)

But because

∆IL+

= ∆IL ndash

if followsthat

(Vi minus Vo) TONL = Vo TOFF

L

which allows us to calculate Vo

Vo = ViTON

TON TOFF= Vi

TON

T (10)

where T is the switching period

Expression (10) links the output voltage Vo to theinput voltage Vi and to the duty cycle The rela-tion-shipbetween the currents is the following

IiDC = IoDC sdot TON

T

EFFICIENCY

The system efficiency is expressed by the follow-ing formula

η = Po

Pisdot 100

where Po = VoIo (with Io = ILOAD)

is the output power to the load and P i is the inputpower absorbed by the system Pi is given by Po

APPLICATION NOTE

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8192019 L4970A Design Considerations

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plus all the other system losses The expressionof the efficiencybecomes therefore the following

η = Po

Po + Psat + PD + PL + Pq + psw

(12)

DC LOSSES

Psat saturation losses of the power transistor QThese losses increase as Vi decreases

Psat = Vsat sdot IoTON

T + Vsat Io

Vo

Vi(13)

where TON

T =

Vo

Viand Vsat is the power

transistorsaturation at current Io

PD losses due to the recirculationdiodeThese losses increase as Vi increasesas inthis case the ON time of the diode is greater

PD = VF IoVi minus Vo

Vi= VFIo (1 minus

Vo

Vi) (14)

where VF is the forward voltage of the recircula-tion diode at current Io

PL losses due to theseries resistance RS of thecoil

PL = RS Io2

(15)

Pq losses due to the stand-by current and to thepower driving current

Pq = Vi Iq (16)

in which Iq is the operating supply current at theoperating switching frequencyIq includes the oscillator current

SWITCHING LOSSES

Psw switching losses of the power transistor

Psw = Vi Iotr + tf2T

The switching losses of the recirculation diode areneglected (which are anyway negligible) as it isassumed that diode is used with recovery timemuch smaller than the rise time of the power tran-sistor

We can neglect losses in the coil (it is assumedthat ∆IL is very small compared to Io) and in theoutput capacitor which is assumed to show a lowESR

Calculationof the inductance value L

Calculation TON and TOFF through (4) and (9) re-spectively it follows that

TON = ∆IL+

sdot LVi minus VoTOFF = ∆IL

minus

sdot LVo

But because

TON + TOFF = T and ∆IL+

= ∆IL ndash

= ∆IL

it follows that

TON = ∆IL sdot LVi minus Vo

+ ∆IL sdot L

Vo= T (17)

Calculating L the previous relation becomes

L = (Vi minus Vo) Vo

Vi ∆ ILT (18)

Fixing the current ripple in the coil required by thedesign (for instance 30 of Io) and introducingthe frequency instead of the period it follows that

L = (Vi minus Vo) Vo

Vi sdot 03 sdot Io sdot f where L is in Henry and f in Hz

Calculationof the output capacitor C

From the outputnode in fig 3 it may be seen that

the current through the output capacitor is givenby

ic (t) = iL (t) ndash Io

Figure 5 EquivalentCircuit ShowingRecirculation when Q1 is Turned Off

APPLICATION NOTE

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8192019 L4970A Design Considerations

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From the behaviour shown in Fig 4 it may be cal-culated that the charge current of the output ca-pacitor within a period is ∆IL 4 which is suppliedfor a time T2 It follows therefore that

∆ VC = ∆IL

4C

T2

= ∆ IL T

8C =

∆ IL8fc

(19)

but remembering expression(4)

∆IL+ = (Vi minus Vo) TON

L and TON =

Vo

ViT

thereforeequation (19) becomes

∆ VC = (Vi minus Vo) Vo

8 Vi f2 L C

Finally calculating C it follows that

C = (Vi minus Vo) Vo

8 Vi ∆VC f2

L(20)

where L is in HenrysC is in Faradsf is in Hz

Finally the followingexpressionshould be true

ESRmax = ∆VCmax

∆IL(21)

It may happen that to satisfy relation (21) a ca-pacitance value much greater than the value cal-culated through (20) must be used

TRANSIENT RESPONSE

Sudden variations of the load current give rise toovervoltages and undervoltages on the outputvoltage Since ic = C (dvc dt) (22) where dvc =∆Vo the instantaneous variation of the load cur-rent ∆Io is supplied during the transient by theoutput capacitor During the transient also cur-rent through the coil tends to change its valueMoreover the following is true

vL = L diLdt

(23)

where diL = ∆Io

vL = Vi ndash Vo for a load increase

vL = Vo for a loaddecrease

Calculating dt from (22) and (23) and equalizingit follows that

L diLvL

= C dvC

iC

Calculating dvc and equalizing it to ∆Vo it followsthat

∆Vo = L∆Io

2

C (Vi minus Vo)

(24) for + ∆Io

∆Vo = L∆Io

2

C Vo(25) for - ∆Io

From these two expressions the dependence ofovershoots and undershoots on the L and C val-ues may be observedTo minimize ∆Vo it is there-fore necessary to reduce the inductance value Land to increase the capacitance value C Shouldother auxiliary functions be required in the circuitlike reset or crowbarprotections and very variableloadsmay be present it is worthwhile to take spe-cial care for minimizing these overshoots whichcould cause spurious operation of the crowbar

and the under-shoot which could trigger the resetfunction

DEVICE DESCRIPTION

For a better understanding of how the devicefunctions a descriptionwill be given of the princi-ple blocks that compose the device The blockdiagram of the device is shown in fig6

POWER SUPPLY

The device contains a stabilized regulator (Vstart= 12V) that provides power to the analogic anddigital control blocks as well as the section of thebootstrap The Vstart voltage also powers theblocks that operates the internal reference volt-age of 51V with a precision of +2 necessaryfor the feedback

OSCILLATOR SYNC AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wavesignal that sets the switching frequency of the

system This signal compared with the outputvoltage of the error amplifier generates the PWMsignal that will then sent to the power outputstage The oscillator also contains the voltagefeedforward function that being completely inte-grated does not require additional external com-ponents to function The VFF function operateswith supply voltages from 15V to 45V The ∆V ∆tof the sawtooh is directly proportional to the sup-ply voltage Vi

As Vi increases the conduction time (ton) of thepower transistor decreases in such way as to pro-vide to the coil and therefore to the load theproduct Volt x Sec constant

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

APPLICATION NOTE

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

APPLICATION NOTE

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

APPLICATION NOTE

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

APPLICATION NOTE

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

APPLICATION NOTE

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 6: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 647

plus all the other system losses The expressionof the efficiencybecomes therefore the following

η = Po

Po + Psat + PD + PL + Pq + psw

(12)

DC LOSSES

Psat saturation losses of the power transistor QThese losses increase as Vi decreases

Psat = Vsat sdot IoTON

T + Vsat Io

Vo

Vi(13)

where TON

T =

Vo

Viand Vsat is the power

transistorsaturation at current Io

PD losses due to the recirculationdiodeThese losses increase as Vi increasesas inthis case the ON time of the diode is greater

PD = VF IoVi minus Vo

Vi= VFIo (1 minus

Vo

Vi) (14)

where VF is the forward voltage of the recircula-tion diode at current Io

PL losses due to theseries resistance RS of thecoil

PL = RS Io2

(15)

Pq losses due to the stand-by current and to thepower driving current

Pq = Vi Iq (16)

in which Iq is the operating supply current at theoperating switching frequencyIq includes the oscillator current

SWITCHING LOSSES

Psw switching losses of the power transistor

Psw = Vi Iotr + tf2T

The switching losses of the recirculation diode areneglected (which are anyway negligible) as it isassumed that diode is used with recovery timemuch smaller than the rise time of the power tran-sistor

We can neglect losses in the coil (it is assumedthat ∆IL is very small compared to Io) and in theoutput capacitor which is assumed to show a lowESR

Calculationof the inductance value L

Calculation TON and TOFF through (4) and (9) re-spectively it follows that

TON = ∆IL+

sdot LVi minus VoTOFF = ∆IL

minus

sdot LVo

But because

TON + TOFF = T and ∆IL+

= ∆IL ndash

= ∆IL

it follows that

TON = ∆IL sdot LVi minus Vo

+ ∆IL sdot L

Vo= T (17)

Calculating L the previous relation becomes

L = (Vi minus Vo) Vo

Vi ∆ ILT (18)

Fixing the current ripple in the coil required by thedesign (for instance 30 of Io) and introducingthe frequency instead of the period it follows that

L = (Vi minus Vo) Vo

Vi sdot 03 sdot Io sdot f where L is in Henry and f in Hz

Calculationof the output capacitor C

From the outputnode in fig 3 it may be seen that

the current through the output capacitor is givenby

ic (t) = iL (t) ndash Io

Figure 5 EquivalentCircuit ShowingRecirculation when Q1 is Turned Off

APPLICATION NOTE

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8192019 L4970A Design Considerations

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From the behaviour shown in Fig 4 it may be cal-culated that the charge current of the output ca-pacitor within a period is ∆IL 4 which is suppliedfor a time T2 It follows therefore that

∆ VC = ∆IL

4C

T2

= ∆ IL T

8C =

∆ IL8fc

(19)

but remembering expression(4)

∆IL+ = (Vi minus Vo) TON

L and TON =

Vo

ViT

thereforeequation (19) becomes

∆ VC = (Vi minus Vo) Vo

8 Vi f2 L C

Finally calculating C it follows that

C = (Vi minus Vo) Vo

8 Vi ∆VC f2

L(20)

where L is in HenrysC is in Faradsf is in Hz

Finally the followingexpressionshould be true

ESRmax = ∆VCmax

∆IL(21)

It may happen that to satisfy relation (21) a ca-pacitance value much greater than the value cal-culated through (20) must be used

TRANSIENT RESPONSE

Sudden variations of the load current give rise toovervoltages and undervoltages on the outputvoltage Since ic = C (dvc dt) (22) where dvc =∆Vo the instantaneous variation of the load cur-rent ∆Io is supplied during the transient by theoutput capacitor During the transient also cur-rent through the coil tends to change its valueMoreover the following is true

vL = L diLdt

(23)

where diL = ∆Io

vL = Vi ndash Vo for a load increase

vL = Vo for a loaddecrease

Calculating dt from (22) and (23) and equalizingit follows that

L diLvL

= C dvC

iC

Calculating dvc and equalizing it to ∆Vo it followsthat

∆Vo = L∆Io

2

C (Vi minus Vo)

(24) for + ∆Io

∆Vo = L∆Io

2

C Vo(25) for - ∆Io

From these two expressions the dependence ofovershoots and undershoots on the L and C val-ues may be observedTo minimize ∆Vo it is there-fore necessary to reduce the inductance value Land to increase the capacitance value C Shouldother auxiliary functions be required in the circuitlike reset or crowbarprotections and very variableloadsmay be present it is worthwhile to take spe-cial care for minimizing these overshoots whichcould cause spurious operation of the crowbar

and the under-shoot which could trigger the resetfunction

DEVICE DESCRIPTION

For a better understanding of how the devicefunctions a descriptionwill be given of the princi-ple blocks that compose the device The blockdiagram of the device is shown in fig6

POWER SUPPLY

The device contains a stabilized regulator (Vstart= 12V) that provides power to the analogic anddigital control blocks as well as the section of thebootstrap The Vstart voltage also powers theblocks that operates the internal reference volt-age of 51V with a precision of +2 necessaryfor the feedback

OSCILLATOR SYNC AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wavesignal that sets the switching frequency of the

system This signal compared with the outputvoltage of the error amplifier generates the PWMsignal that will then sent to the power outputstage The oscillator also contains the voltagefeedforward function that being completely inte-grated does not require additional external com-ponents to function The VFF function operateswith supply voltages from 15V to 45V The ∆V ∆tof the sawtooh is directly proportional to the sup-ply voltage Vi

As Vi increases the conduction time (ton) of thepower transistor decreases in such way as to pro-vide to the coil and therefore to the load theproduct Volt x Sec constant

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

APPLICATION NOTE

847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 947

1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

APPLICATION NOTE

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

APPLICATION NOTE

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

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8192019 L4970A Design Considerations

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From the behaviour shown in Fig 4 it may be cal-culated that the charge current of the output ca-pacitor within a period is ∆IL 4 which is suppliedfor a time T2 It follows therefore that

∆ VC = ∆IL

4C

T2

= ∆ IL T

8C =

∆ IL8fc

(19)

but remembering expression(4)

∆IL+ = (Vi minus Vo) TON

L and TON =

Vo

ViT

thereforeequation (19) becomes

∆ VC = (Vi minus Vo) Vo

8 Vi f2 L C

Finally calculating C it follows that

C = (Vi minus Vo) Vo

8 Vi ∆VC f2

L(20)

where L is in HenrysC is in Faradsf is in Hz

Finally the followingexpressionshould be true

ESRmax = ∆VCmax

∆IL(21)

It may happen that to satisfy relation (21) a ca-pacitance value much greater than the value cal-culated through (20) must be used

TRANSIENT RESPONSE

Sudden variations of the load current give rise toovervoltages and undervoltages on the outputvoltage Since ic = C (dvc dt) (22) where dvc =∆Vo the instantaneous variation of the load cur-rent ∆Io is supplied during the transient by theoutput capacitor During the transient also cur-rent through the coil tends to change its valueMoreover the following is true

vL = L diLdt

(23)

where diL = ∆Io

vL = Vi ndash Vo for a load increase

vL = Vo for a loaddecrease

Calculating dt from (22) and (23) and equalizingit follows that

L diLvL

= C dvC

iC

Calculating dvc and equalizing it to ∆Vo it followsthat

∆Vo = L∆Io

2

C (Vi minus Vo)

(24) for + ∆Io

∆Vo = L∆Io

2

C Vo(25) for - ∆Io

From these two expressions the dependence ofovershoots and undershoots on the L and C val-ues may be observedTo minimize ∆Vo it is there-fore necessary to reduce the inductance value Land to increase the capacitance value C Shouldother auxiliary functions be required in the circuitlike reset or crowbarprotections and very variableloadsmay be present it is worthwhile to take spe-cial care for minimizing these overshoots whichcould cause spurious operation of the crowbar

and the under-shoot which could trigger the resetfunction

DEVICE DESCRIPTION

For a better understanding of how the devicefunctions a descriptionwill be given of the princi-ple blocks that compose the device The blockdiagram of the device is shown in fig6

POWER SUPPLY

The device contains a stabilized regulator (Vstart= 12V) that provides power to the analogic anddigital control blocks as well as the section of thebootstrap The Vstart voltage also powers theblocks that operates the internal reference volt-age of 51V with a precision of +2 necessaryfor the feedback

OSCILLATOR SYNC AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wavesignal that sets the switching frequency of the

system This signal compared with the outputvoltage of the error amplifier generates the PWMsignal that will then sent to the power outputstage The oscillator also contains the voltagefeedforward function that being completely inte-grated does not require additional external com-ponents to function The VFF function operateswith supply voltages from 15V to 45V The ∆V ∆tof the sawtooh is directly proportional to the sup-ply voltage Vi

As Vi increases the conduction time (ton) of thepower transistor decreases in such way as to pro-vide to the coil and therefore to the load theproduct Volt x Sec constant

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

APPLICATION NOTE

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

APPLICATION NOTE

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3447

Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 7 shows the duty-cycle varies as a result ofthe changes in slope of the ramp with the inputvoltage Vi The output of the error amplifier

should not change to maintain the output voltagein regulationThis function allows for the increaseof speed in response to the rapid change of thesupply voltage and for a greatly reduced ouputripple at the mains frequency

In fact the slope of the ramp is modulated by theripple generally present in the order of severalvolts on the input of the regulator particularlywhen the solution with a mains transformer isused

Fig 8 shows the simplified electrical diagram ofthe oscillator

A resistor connected between the Rosc pin andGND sets the current that is internally reflected in

the pin Cosc in order to charge the external ca-pacitor to which it is connected The voltage tothe Rosc pin is not fixed but is tied to the instan-taneous value of Vi this is needed to achieve thefeedforward voltage function in which the slopeof the ramp is directly proportional to the supplyvoltage A comparator senses the voltage at theCosc capacitor When the voltage reaches thevalue present at the inverting input of the compa-rator the output from the comparator goes highand is sent to the two transistorsQ1 and Q2

Q1 is responsible for discharging the externalCosc capacitor with a current of approx 20mAwhile Q2 imposes at the inverted input of thecomparator a voltage of 2Vbe (approx 13V) thatis the low-threshold of the ramp Some useful for-mulas for calculating the various parameters ofthe oscillator block are

Figure 6 Block Diagram of the 10A Monolithic RegulatorL4970A

V2

V7

D93IN006

Vi=30V

Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Figure 7 Voltage Feeforward Waveform

APPLICATION NOTE

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

APPLICATION NOTE

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

APPLICATION NOTE

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

APPLICATION NOTE

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

2347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2547

Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

2547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

2947

8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

8192019 L4970A Design Considerations

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 9: L4970A Design Considerations

8192019 L4970A Design Considerations

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1) Oscillator charge current

ICHARGE = V i minus 9Vbe

Rosc(For 15V lt Vi lt 45V)

2) Oscillator discharge current

IDISCH = 20mA

3) Peakvoltage ramp

VthminusH = Vi minus 9Vbe

Rosc + 2Vbe

This formula is obtained in the following way indi-cating with Ve the voltageof theemitter of the NPNtransistor connected to Vcc and V- the voltage atthe invertedinput of the comparator onehas

(a) Ve = Vi

3 minus Vbe

(b) Vminus =

Ve minus 2Vbe

3R sdot R

+ 2Vbe

by substituting (a) into (b) one obtains

Vminus =( Vi

3 minus Vbe ) minus2Vbe

3 + 2Vbe =

Vi minus 9Vbe

9 + 2Vbe

4) Valley voltage ramp

Vth-L = 2Vbe

5) Switchingfrequency

fSW = 9

Rosc Cosc

It should be noted that formula (5) does not takeinto account the discharge time of Cosc whichcannot be neglected when one is working at fre-quencies equal or higher than 200KHz The dis-charge time is also tied to the value of Cosc itself

Analitycally one has

6) TDISCH = VthminusH minus VthminusL

20mA sdot Cosc

from which is obtained the more closely approxi-mate expressionof the oscillator frequency

7) fSW = 1

Rosc sdot Cosc

9 + TDISCH

During the discharge time of Cosc a clock pulse isgenerated internally that is made subsequentlyavailable on the Sync pin and that can be used to

synchronize other regulators (3 devices of thesame family maximum) The Syncpulse generatedhas a typical range of 45V and the current avail-ability is 45mA In general it is better that the Syncpulse is at least 300-400ns in order to be able tosynchronizea rangeof existing regulators to obtainthis result values of suggested capacitors in differ-ent test circuits have been selected The typicalduration of the synchronizing pulse with the sug-gestedvalues of Cosc are as follows

L497X Family (MULTIWATT PACKAGE)

Cosc (nf) - Rosc = 16KΩ Sync (ns)

068

11215223347

140

230270330450680

1100

L497X Family (POWERDIP PACKAGE)

Cosc (nf) - Rosc = 30KΩ Sync (ns)

1215223347

230280420600900

Vi

2R

1 3 2RR

Rosc

Cosc

PWM

COMP

Q1R

Q2

CLOCK

D93IN007

-

+

Figure 8 Oscillator Circuit

APPLICATION NOTE

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

APPLICATION NOTE

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

APPLICATION NOTE

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

APPLICATION NOTE

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

2547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 10: L4970A Design Considerations

8192019 L4970A Design Considerations

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Obviously synchronize pulses of eccessive dura-tion can greatly reduce the max duty-cycle andproduce distortions in the sawtooth of the syn-chronized regulator working as slave

PWM

Comparing the sawtooth signal generated by theoscillator and the output of the error amplifiergenerates the PWM signal which is sent to thedriver of the output power stage The PWM sig-nal in the path towards the output stage also en-counters a latch block to prevent other pulsesfrom being sent at same period to the outputpossibly damaging the power stage In the PWMblock a duty-cycle limiter has also been intro-duced Such a limiter is obtainedby taking advan-tage of the synchronizing pulse generated thepower output stage is inhibited Even if the error

amplifier gives a large signal to the peak of theramp the power stage will not be able to operatein DC but will be switched off at each clock pulse

The max obtainable duty-cycle is higher than

90 this however depends on the working fre-quency and the value of Cosc Using the formulas6) and 7) a precise calculation can be done

SOFT START

The Soft Start function is essential for a correctstartup of the device and for an output voltagethat at the switch on increases in a monotonousmode without dangerous output overvoltagesandwithout overstress for the power stage

Soft Start operates at the startup of the systemand after an intervention of the thermalprotectionFig 9 shows the simplified diagram of the startupfunctions The function is carried out by means ofan external capacitor connected to the Soft Startpin which is charged with a constant current ofabout 100microA to a value of around 7V During the

charging time the output of the error transcon-ductance amplifier becauseof Q1 is forced to in-crease at the same rising edge time of the exter-nal softstartcapacitor Css

CLAMPEDERROR AMPLIFIER

OUTPUTVc

OUTPUT

CURRENT

SOFT START TIME

t

D93IN011

t

Figure 10 Soft Start Waveforms

Figure 9 Soft Start Circuit

APPLICATION NOTE

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

APPLICATION NOTE

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

APPLICATION NOTE

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 2147

Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

2347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2547

Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

2547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

2947

8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

8192019 L4970A Design Considerations

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 11: L4970A Design Considerations

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The PWM signal begins to be generated as soonas the output voltage of the error amplifiercrosses the ramp at this point the output stagebegins to commutate slowly increasing its ONtime (see fig 10)

The charge of the Css capacitor as already men-tioned begins each time the device is suppliedwith power and after which an anomalous condi-tion is created as the intervention of thermal pro-tection or of the undervoltage lockout

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge time of the os-cillator capacitor Cosc is neglected This is anapprox valid for switching frequencies up to200KHz Let us indicate with Vr the output voltageof the error amplifier and with Vc the voltage of

the oscillator ramp

The PWM comparator block commutateswhen Vr= Vc Therefore

8) Vr = Vc = Vpp

T sdot t =

Vi minus 9Vbe

9 sdot T sdot t

from which is obtained

9) t = Vr sdot T sdot (Vi minus 9Vbe)

9

The time t obtained from this equation is equal tothe ON time of the power transistor The corre-sponding duty-cycle is given by

10)

D = ton

T =

Vr sdot T sdot (Vi minus 9Vbe)

9T =

Vr sdot (Vi minus 9Vbe)

9 =

VO

Vi

Consequently after leaving the discharged ca-pacitor of Soft Start the output of the regulatorwill reach its value when the voltage across the

Css capacitor charged with constant current hasreached the value Vr - 05V

The time necessary in order that the output risesfrom zero to the nominal value is given by

11) tstartminusup = Css sdot (Vr minus 05V)

Iss

in which Css is the Soft Start capacitor and Issthe Soft Start current Considering Soft Start timeas tss the required time for the Soft Start capaci-tor to change itself approx from (2Vbe - 05V) =(12V - 05V) to Vr - 05V is

12) tss = Css sdot (Vr minus 12V)

Iss

By taking Vr from (10)

13) Vr = Vo

Visdot 9Vi minus 9Vbe

and substituting it in (12) we obtain

14) tss = Css

Iss

Vo

Visdot 9

Vi minus 9Vbeminus 12V

UNDERVOLTAGE LOCKOUT

The device contains the protectionblock of under-voltage lockout which keeps the power stageturned-off as long as the supply voltage does not

reach at least 12V At this point the device startsup with Soft Start

The function of undervoltage is also provided withan hysteresis of 1V to make it better immune tothe ripple present on the supply voltage

ERROR AMPLIFIER

The error amplifier is a transconductance typeand deliver an output current proportional to thevoltage inbalance of the two inputs The simplifieddiagram is presented in fig 12The principal char-acteristics of this uncompensatedoperationalam-

plifier are the followingGm = 4mAV Ro = 25Mohm Avo = 80dBIsource-sink = 200uA Input Bias Current = 03uA

The frequency response of the op amp is givenin fig 13

Ignoring the high frequency response and hy-pothesizing that the second pole is below the 0dB axis in the all the conditions of loop compen-sation it is possible to make a first approximationwith the equivalentcircuit of fig 14

Figure 11 Soft Sart Time Waveform

APPLICATION NOTE

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

APPLICATION NOTE

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characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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8192019 L4970A Design Considerations

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

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Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

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8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 12: L4970A Design Considerations

8192019 L4970A Design Considerations

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In which

15) Av(s) = Gm sdot Ro

1 + sRo CowhereCo = 3pF

The error amplifier can be easily compensatedthanks to the high output impedance (see fig 14)

The resulting transfer function is as in the follow-ing

(16)

Av(s) = Gm sdot Ro sdot (1 + sRcCc)

s2 Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1

The Bode diagram is shown in fig16

The compensation circuit introduces a pole at lowfrequency and a zero that is generally calculatedto be put in the proximity of the resonance fre-quency of the output LC filter

The second pole at high frequency generally fallsin a zone of no interest (for the system stabilityone must consider the zero introduced by ESR

Figure 12 ErrorAmplifier Circuit

Figure 13 Openloop gain (error amplifier only)

Figure 14 Erroramplifier equivalent circuit

Figure 15 Compensationnetworkof the erroramplifier

Figure 16 Bode plot showing gain and phase ofcompensatederror amplifier

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 1347

characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

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8192019 L4970A Design Considerations

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2947

Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3347

CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3447

Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

8192019 L4970A Design Considerations

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 13: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 1347

characteristic of the output capacitor Not all thedesigners agreeon this solution)

If necessary however one can turn to more so-phisticated compensation circuitry An example isshown in fig 17

Such a circuit introduces a pole at low-frequencyand two zeros

17) Z1 = 1

2Π R1 C1 Z2 =

1

2Π R2 C2

It must be remembered however that because ofthe high output impedance of the erroramplifier asecond pole is also present

18) P2 = Gm

2Π C1

We normally suggest a high value for R1 to re-

duce the value of the capacitor C1 and allocatethe pole P2 at the highest possible frequencyThe essential limitation to the max value of R1 isthe offset introduced by the input bias current ofthe error amplifier In the case of output voltageregulated higher than 51V an external dividershould be introduced Itrsquos than possible to intro-duce a second zero using the following network

Two zerosand two poles are introduced

19) Z1 = 1

2Π Ro CcZ2 =

1

2Π R1 C1

P1 = 1

2Π Ro CcP2 =

1

2Π RxC1

Where Rx= R1 sdot R2

R1 + R2

APPLICATIONEXAMPLE

Consider the block diagram of fig 19 repre-senting the internal control loop section with theapplication valuesFswitch= 200KHzL = 100microH C = 1000microFPo = 50W Vo = 51V Io = 10A and Fo = 500HzGloop = PWM sdot Filter

The system requires that DC gain is maximum toachieve good accuracy and line rejection Beyondthis a bandwidth of some KHz is usually requiredfor a good load transient response The error am-plifier transfer function must guarantee the aboveconstrainst A compensation network that couldbe used is shown in fig 21

A(s) = (1 + sR1 C1) (1 + sR2 C2)

sR1 C1 (1 + s C1

Gm )

Figure 17 Onepole two zero compensationnetwork

Figure 18 Compensationnetwork for outputvoltages higher than 51V

Figure 19 Blockdiagram used in stabilitycalculation

Figure 20 Frequencybehaviourof the circuitoffig 19

APPLICATION NOTE

1347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 1447

The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 1547

In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 14: L4970A Design Considerations

8192019 L4970A Design Considerations

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The criterium is to define Z1 Z2 close to the reso-nant pole of the output LC filter The Gm2ΠC1pole must be placed at a frequencyat which openloop gain is below 0dB axis (fig 22)

CURRENT LIMITING

A complete regulation system will be equippedwith a good current limiter able to protect fromload breaking and operator error controllsThe current limiting function is totally integratedand does not require any external componentThe output current is sensed by an internal low-value resistor in series with the drain of theDMOS vertical power transistor

A precision current limitation of plusmn 10 relative atthe peak current is guaranted During overcurrentsituation the pulse by pulse current limitation pro-

duce an output stage switching frequency reduc-tion The block diagram of the current limiting isshown in fig 23

Figure 21 Compensationnetwork

ACSJ Gloop

PWM+FILTER

50Hz 500Hz 5Kz 50KHz

20

40

dB

D93IN012

Figure 22 Bodeplot of the regulation loop with the compensation network of fig 21

Figure 23 Currentprotectioncircuit

APPLICATION NOTE

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

1747

8192019 L4970A Design Considerations

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2047

8192019 L4970A Design Considerations

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2247

Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2347

Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

2347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2547

Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

2547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 15: L4970A Design Considerations

8192019 L4970A Design Considerations

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In overcurrent situation the comparator send asignal at the flip-flop set input an inhibit pulse isimmediatly generated from it and sended at theoutput stage switchingoff the power mos

A reset pulse input in generated from an 40KHzinternal oscillator

After the first reset pulse the control loop will startto regulate the system an the output current willincrease following the principal oscillator fre-quency If overcurrent condition is still present thecurrent limiting will be activate again

This type of current limiting ensure a constantoutput current in overload or short circuit condi-tion and allow a good reliability at high frequency(500KHz) reducing the problems relative at the in-ternalsignal delay through the protectionblocks

The inductor current in overload condition inshown in fig 24

The 40KHz internal oscillator is synchronizedwiththe principal one If the system work with a oscil-lator tracks the principal oscillator frequency Inthis way the switching frequency will not increasein overload situation

A particular care has to be taken in the inductorvalue in order to avoid problems during overloador short circuit conditions A critical situation ispresent with high switching frequency (more than

200KHz) where a small inductor value is usedand withhigh capacitiveload

In order to return in nominal condition after ashort circuit the inductor ripple at 40KHz with thenominal output voltage and current has to belower than the current limitation value

Example

Let us consider L4970A 10A (the same ap-proach can be used for all the family)

The inductor ripple current is given by the follow-ing formula

∆IL = (Vi minus Vo) sdot Vo

Vi sdot fsw sdot L

where fsw = 40KHzplusmn10

In order to get the maximum inductor ripple cur-rent the previous formula becomes

∆IL = (Vimax minus Vomax) sdot Vomax

Vimax sdot fsw min sdot L

The current limitation for L4970A will start to workat 13A

therefore

Ilim min gt Ionom + ∆IL

2

where Ionom = 10A for L4970A

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit thatmay be used to generate a power on power offreset signal for a microprocessorsystem The cir-cuit senses the input supply voltage and the out-put generated voltage and will generate the re-quired reset signal only when both the sensedvoltages have reached the required value for cor-

rect system operation The Reset signal is gener-ated after a delay time programmable by an ex-ternal capacitor on the delay pin Fig 25 showsthe circuit implementation of Reset circuit Thesupply voltage is sensed on an external pin forprogrammability of the threshold by a first com-parator The second comparator has the refer-ence threshold set at slightly less the ref voltagefor the regulation circuit and the other input con-nected internally at the feedback point on theregulated voltage When both the supply voltageand the regulated voltage are in the correctrange transistor Q1 turns off and allows the cur-rent generator to charge the delay capacitor dis-charges completely before initialization of a new

Reset cycle The output gate assures immediatetake of reset signal without waiting for completedischarge of delay capacitor Reset output is anopen collector transistor capable of sinking 20mAat 200mV voltage Fig 26 shows reset waveforms

Figure 24 Overloadinductancecurrent

APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 2247

Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 2347

Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 2447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2547

Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 16: L4970A Design Considerations

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 17: L4970A Design Considerations

8192019 L4970A Design Considerations

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POWER STAGE

The simplified diagram of the output stage isshown in the fig 27

The power stage and the circuit connected with itare by far the most important and critical compo-nents when one wants to obtain good perform-ance at highswitching frequency

The power transistor must have excellent charac-teristics from the point of view of both the switch-ing speed and the robustness

The transistor DMOS with its intrinsic charac-teristics of elevated speed no second breakdownphenomenom and easy driving proves to be par-ticularly suitable for this type of application thatnormally works at high frequency

For a properly driving of the DMOS gate it is nec-essary to use an external bootstrap capacitor

When the voltage Vs is low the Cboot capacitor ischarged through the internal diode D1 at thevalue of voltage equal to that of Vstart which isabout 12V the next step oversees that Q3 isturned off Q2 is driven in gate by Q1 so that Q1can go in saturation and its source can go up risetowardsVi

Cboot maintains its charge and guaranteesa volt-age equal Vi+12V at the gate of Q7 so that canenter into region of low resistance

At this point the diode D1 turns on to be inverselypolarized disconnectingthe 12V section from thatof the driving power stage

When Q2 is ON the driven current of the powerstage requires from the bootstrap capacitor a typi-cal current of 400uA

When Q2 is Off a current of 25mA is required tomantain Q2 in that state This current however isnot delivered from the bootstrap capacitor butrather from the internal regulator of 12V while the

output current flowing in the freewheeling diode

The circuit described is capableof obtainingcom-mutation rise and fall time a typical value of50ns

In principle it would have been feasible to reducefurthermore the commutation time whithout anyreliability problems

This was not believed to be advantageoussince itwould not have been of any benefit if one thinksof the trr time of the catch diode (with trise of50ns also the Schottky diodes begin to show limi-tations) and of the conseguent increase of differ-ent disturbances caused bt too higly elevateddIdt

Ther following table shows the main features ofthe DMOS transistor

Figure 27 Power stagecircuit

Figure 28 Gate-charge curve for the power

APPLICATION NOTE

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2547

Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2947

Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

2947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3047

Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3447

Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

8192019 L4970A Design Considerations

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 18: L4970A Design Considerations

8192019 L4970A Design Considerations

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THERMAL SHUTDOWN

The thermal protection intervenes when the junc-tion temperature reaches 150o

C it intervenes di-rectly on the output stage turning it off quikly andin the meantime discharging the soft start capaci-tor

The reference voltage and the oscillator will con-

tinue to work regularly

The thermal shutdown has a hysteresis after itsintervention it is necessary to wait for the junctiontemperature to lower around 30oC before the de-vice will begin to work properly again

The device restart to work by using the soft startfunction

Table 1

BVDSS gt 60V at ID = 1mA VGS = 0V

RDS(ON) = 100mΩ at ID = 10A T j = 25degC VGS = 10V

RDS(ON) = 150mΩ at ID = 10A T j = 150degC VGS = 10V

VTH = 3V at ID = 1mA

Table 2 HighCurrent Switching Regulator ICs

Parameter

L497X FAMILY

L4970A L4977A L4975A L4974A L4972A L4972AD

Surf Mount

Max Input OperatingVoltage

50V 50V 50V 50V 50V 50V

Output Voltage Range 51V (plusmn2) to 40V

Max Output Current 10A 7A 5A 35A 2A 2A

Power SwitchRDSON at 25degC 013Ω typ

Switching ModeControl System

Continuous Mode Direct Duty Cycle Control with Voltage Feed-Forward

Max Switching Freq 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz

EfficiencyVINPUT = 35VVOUT = 51V

10A80

at 200KHz

7A80

at 200KHz

5A85

at 200KHz

35A85

at 100KHz

2A85

at 100KHz

2A85

at 100KHz

Current Limiting Constant Current

Soft Start Yes

Reset and Power Fail Yes

Synch Yes

Crowbar No

PackageMax Rth j-case (pin)

Rth j-amb

Multiwatt151degCW35degCW

Multiwatt151degCW35degCW

Multiwatt151degCW

35degCW

Powerdip 16+2+2

12degCW60degCW

Powerdip 16+2+2

12degCW60degCW

SO20L6degCW

80degCW

APPLICATION NOTE

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APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 19: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 1947

APPLICATIONS

Even though the regulators of the L4970A familyhas been designed to work only in step downconfiguration we will see next how these regula-

tors can be use in large range of applicationsIn same cases the L4970A device will be used asan example for the entire family assembled inMultiwatt package and the L4974A will be usedfor the types in powerdip package

Anyway the suggested applications can be ex-tended to any other device of the family by adjust-ing if necessary the external components usingthe given equation for the calculation

Typical Application

The Fig 29 shows the electrical diagram of thetypical application complete with all the auxiliary

functions The same application suggested in thedata sheetas test circuit and is the same used forthe final dynamic test All our devices are 100tested both in static anddynamic conditions

Included in the dynamic test are obviously the ex-ternal components the coil catch diode and out-put capacitor which have been defined for allregulators

Shown below are the electrical diagrams of 5 de-vices that compose the family of this regulatorcomplete with the value of the external compo-nentsand with the relative pcb layout

Output voltages higher than 51V are possible us-ing an output resistive divider For Vo gt 24V forsafety reasons it must be avoided the zero loadcondition In the application with high currentconnected to the output divider are added twoother resistances that permit the separation ofsensing and forcing in such way as to compen-sate the fall of voltage on the connecting cablesbetween the outputand the load

Connecting directly the output to the feedback pin

a 51V plusmn2 is obtained The following table canbe help for a rapid calculation of a resistor dividerto obtain some of the most standard output volt-age

Figure 29 L4970ATypical Application Circuit

APPLICATION NOTE

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Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2247

Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

2247

8192019 L4970A Design Considerations

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

2347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2447

8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

2547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3347

CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3447

Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 20: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2047

Figure 30 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 10A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 10A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2047

8192019 L4970A Design Considerations

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

2147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2247

Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

2547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

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httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3347

CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

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Figure 31 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

Figure 32 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 30 (11 scale)

APPLICATION NOTE

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Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 22: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2247

Figure 33 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 2A fsw = 100KHz)

Vo RIPPLE = 30mV (at 1A)

Line regulation= 12mV (Vi = 15 to 50V)

Load regulation= 7mV (Io = 05 to 2A)

for componentvalues Refer to the fig 32 (Part list)

PART LISTR1 = 30KΩ

R2 = 10KΩ

R3 = 15KΩ

R4 = 30KΩ

R5 = 22Ω

R6 = 47KΩ

R7 = seetable A

R8 = OPTION

C1 = C2 = 1000microF 63V EYF (ROE)

C3 = C4 = C5 = C6 = 22microF 50V

C7 = 390pF Film

C8 = 22nF MKT 1837 (ERO)

C9 = 27nF KP 1830 (ERO)C10 = 033microF Film

C11 = 1nF

C12 = C13 = C14 = 100microF 40V EKR (ROE)

C15 = 1microF Film

D1 = SB 560 (OR EQUIVALENT)

L1 = 150microHcore 58310 MAGNETICS45 TURNS 091mm (AWG 19)COGEMA 949181

2 capacitors in parallel to increase input RMS current capability 3 capacitors in parallel to reduce total output ESR

Table BSUGGESTEDBOOSTRAPCAPACITORS

Operating Frequency Boostrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

NoteIn the Test and Application Circuit for L4972D are not mounted C2C14 and R8

APPLICATION NOTE

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 23: L4970A Design Considerations

8192019 L4970A Design Considerations

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Figure 34 ComponentLayout of fig 33 (11 scale) Evaluation Board

Figure 35 PCBoard and Component Layoutof the ciruit of fig 33 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2547

Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

2947

8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 24: L4970A Design Considerations

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3347

CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 25: L4970A Design Considerations

8192019 L4970A Design Considerations

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Figure 37 ComponentLayout of fig 36 (11 scale) Evaluation Board

Figure 38 PCBoard and Component Layoutof the ciruit of fig 36 (1 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

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The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 26: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2647

Figure 39 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 5A fSW = 200KHz)

Vo RIPPLE = 30mV(at 10A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 5A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 760CT (or 75A60V or equivalent)

L1 = 80microH core 58930 MAGNETICS47 TURNS Oslash 113mm (AWG 76)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2847

Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

2847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 2947

Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

2947

8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

3047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3547

POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3647

Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 27: L4970A Design Considerations

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

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In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 28: L4970A Design Considerations

8192019 L4970A Design Considerations

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Figure 42 Test and Evaluation Board Circuit

TYPICALPERFORMANCES (using evaluationboard)

n = 83 (Vi = 35V Vo = VREF Io = 7A fSW = 200KHz)

Vo RIPPLE = 30mV(at 7A) with output filter capacitor ESR le 60mΩ

Line regulation= 5mV (Vi = 15 to 50V)

Load regulation= 15mV (Io = 2 to 7A)

For componentvalues refer to test circuit part list

PARTS LIST

R1 = 30KΩ C1 C2 = 3300microF 63VL EYF (ROE

R2 = 10KΩ C3 C4 C5 C6 = 22microF

R3 = 15KΩ C7 = 390pF Film

R4 = 16KΩ C8 = 22nF MKT 1817 (ERO)

R5 = 22Ω 05W

R6 = 4K7 C9 = 22nF KP1830

R7 = 10Ω C10 = 220nF MKT

R8 = see tab A C11 = 22nF MP1830

R9 = OPTION C12 C13 C14 = 220microF 40VL EKR

R10 = 4K7 C15 = 1microF Film

R11 = 10Ω

D1 = MBR 1560CT (or 16A60V or equivalent)

L1 = 40microH core 58071 MAGNETICS27 TURNS Oslash 13mm (AWG 16)COGEMA 949178

2 capacitors in parallel to increase inputRMS current capability 3 capacitors in parallel to reduce total output ESR

Table B

SUGGESTEDBOOTSTRAPCAPACITORS

Operating Frequency Bootstrap Capc10

f = 20KHz ge680nF

f = 50KHz ge470nF

f = 100KHz ge330nF

f = 200KHz ge220nF

f = 500KHz ge100nF

Table A

V0 R10 R8

12V15V18V24V

47KΩ47KΩ47KΩ47KΩ

62KΩ91KΩ12KΩ18KΩ

APPLICATION NOTE

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

8192019 L4970A Design Considerations

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3447

Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

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8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Figure 43 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

Figure 44 PC Board (Back side) and ComponentsLayout of the Circuit of Fig 42 (11 scale)

APPLICATION NOTE

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

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httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

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when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 30: L4970A Design Considerations

8192019 L4970A Design Considerations

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Resistors value for standard output voltages

Vo(V)

Rx(kΩ)

Ry(kΩ)

12151824

47474747

62911218

Rx correspondsto R9 for L4974A and L4972A

Ry corresponds to R10 for L4970A L4977A andL4975A

Rx correspondsto R7 for L4974A and L4972A

Ry corresponds to R8 for L4970A L4977A andL4975A

The suggested switching frequency and used inthe dynamic tests is 200KHz for the Multiwatt

983214

package (MW) and 100KHz for the powerdipplastic package (PDIP) The maximum switchingfrequency allowed is 500KHz

For the types in plastic package (Powerdip) thelower switching frequency suggested is only de-pended by the minor dissipating power of a plas-tic package versus a rdquopower packagerdquo because itis well known that switching losses are directlyproportional to the commutationf requency

Higher switching frequencies are possible if lim-ited output current is required and the operating

ambient temperature are lower than 70oC Infactthe oscillator of the devices assembled in dual inline is completely equivalent to Multiwatt983214 pack-age

The most important external components whichneed a little more attention (because a properlydimensioning affects on the performance of theapplication) are the input and output capacitorsthe freewheelingdiodeand the coil

INPUT OUTPUT CAPACITORS

The output voltage ripple ∆Vo essentially de-pends on the current ripple in the coil and theESR of the output capacitor at the switching fre-quency

The capacitor that present a low ESR are capableof supporting higher current ripples

Today the majority of the constructors of elec-trolithic capacitors offer in their data book also awide range of rdquolow ESRrdquo types generally sug-gested for switching power supply application

In our case EKR and EKE series (ROE) has beenpreferred

Figure 45 Oscillatorwaveform and sync pulsefor Vi = 35V

Figure 46 Oscillatorwaveform and sync pulsefor Vi = 15V

Figure 47 Oscilloscopephotograph showing theshort circuit output voltage andcurrent waveforms

10microsD

10WDiv

5ADiv

1microsDiv

1VDiv

1microsDiv

1VDiv

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3647

Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 31: L4970A Design Considerations

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(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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httpslidepdfcomreaderfulll4970a-design-considerations 3647

Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

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8192019 L4970A Design Considerations

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Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 32: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3247

(EKE)

Rated cap

(microF)

Rated volt

(V)

DimensionsD x L (mm)

(nominaldimensions)

Dissipationfactor tan δ

(100Hz20degC) LimValues

ImpedanceZ (Ω)

(100KHz20degC)(Lim values)

ImpedanceZ (Ω)

(100KHz- 10degC)(Lim values)

ImpedanceZ (Ω)

(10KHz- 40degC)(Lim values)

Admissibleripple curr

(mA)100Hz105degC

223347100220330330470

1010101010101010

5 x 115 x 115 x 115 x 11

63 x 118 x 115

85 x 1258 x 115

019019019019019019019019

130130130130060033033033

390390390390180099099099

20202020

980580580580

1541541541 54260400400400

100220220330470

1616161616

63 x 118 x 115

85 x 1258 x 115

10 x 125

016016016016016

060033033033025

180099099099075

980580580580320

260400400400510

100220330470

25252525

63 x 118 x 115

10 x 12510 x 16

014014014014

060033025019

180099075057

980580320220

260400510635

100100220330470

3535353535

8 x 11585 x 12510 x 12510 x 1610 x 20

012012012012012

033033025019014

099099075057042

580580320220150

400400510635860

Table 2 Admissible ripple currentAmbient Temp

δu in degCAdmissible of the

85degC valueSurface Temp

in degCAdmissible of the

105degC valueSurface Temp

in degC

le 40 220 55 230 55

45 210 59 220 60

50 200 63 210 64

55 190 67 200 68

60 180 70 190 72

65 170 74 180 76

70 155 77 170 80

75 140 81 160 8480 120 84 150 88

85 100 88 140 92

90 90 92 130 96

95 80 97 120 100

100 70 101 110 104

105 60 106 100 108

APPLICATION NOTE

3247

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CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

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Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

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Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

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POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

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the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

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LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

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8192019 L4970A Design Considerations

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But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

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Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 33: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3347

CATCH DIODE

Because of quickly rise and fall time of the cur-rent (about 40-50ns) the use Schottky diode isreccomanded Ultra-fast diodes with 30-50ns of

trr (reverse recovery time) are not considered suf-ficiently fast for this family of converters sincethey would give too elevated peaks of current atthe turn on of the internal power transistor sohigh thatcould affect the reliability of the completesystem as well as drastically reduce the effi-ciency The oscilloscope photographs show theOutput Voltage and Output Current waveformsobtained with diode having different trr value

In the test circuits used for this family of convert-ers Schottky diodes from 60V (breakdown re-verse voltage) are suggested since the devicecan support a max input power voltage of 55V(for specific applications Schottky diodes with areverse breakdown voltage higher or equal to themaximum supply voltage should be used) withcurrent rating and packaging to satisfyall the con-ditions of duty cycle and therefore also of powerdissipation

COIL

Concerning the coil a molypermalloy toroidalcores has been suggested so that it would beeasy for everybody to obtain samples wrap them

with a right number of turns in order to evaluateand correlate the measurements and perform-ance of the devices

In addition since the devices are dynamicallytested 100 in production with a rdquojigrdquo of testingwhich uses the same coil suggested in the appli-cations in the case of contests for example on aguaranteed parameter like the efficiency shouldbe easier to solve the objections in this caseshould be remembered that changing the mag-netic material the dimension the wire and thenumber of the winding also change the losses inthe coil reducing the total efficiencyof the applica-tion

This can be easily verify using for example toroi-dal cores in iron powered rather that those sug-gested in molypermalloy

Moreover it is important to dimension properlythe coil in order to avoid its saturation a goodchoice is to dimension that its saturation currentis not equal to the maximum nominal current ca-pable to deliver to the load but rather higher byabout 20 then the maximum guaranted currentof the device in short circuit condition

Only in this way it is possible to guarantee thatthe coil never saturate in all the possible workingconditions ie in presence of a load transient inshort circuit in output and in the case of elevated

temperatureof the magnetic partAt last it should be remembered that the sug-gested inductors values are referred to the induc-tors values that the coil must have at the maxi-mum output current of the applicationOscilloscope Photographs showing the deviceoutput voltage and current waveforms obtainedwith different inductor

Figure 48 SchottkyDiode

Figure 49 Ultra Fast Diode (trr lt 100ns)

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 50 Waveformsfor L = 50microH

10VDiv

1ADiv

1microsDiv

APPLICATION NOTE

3347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3447

Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

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httpslidepdfcomreaderfulll4970a-design-considerations 3547

POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3647

Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

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8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 34: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3447

Anyway some general rules should be observedin order to avoid any rdquopoor functioningrdquo Theserules include

a) the catch diode that further to be the sug-

gested type in the test circuit it has to be as-sembled on the printed circuit very close tothe output of the regulator in order to mini-mize the leakage inductance and avoid overvoltage due to the long connection

b) The inductor avoiding the saturation at themaximum current guaranted by the currentlimitation of the device

If oscillations on the output voltage at low ambienttemperature (ie below 0oC) are originated anoutput low ESR capacitorhas to be used

Oscillations on the output al low frequency indi-cate instability of the control loop in this case achanging of the network compensation is sug-

gested (see Error Amplifier section)

LOW COST APPLICATION

The fig 53 shows the low cost application of apower supply of 10A and 51V

In comparison of the complete application (andthis is valid for all the devices of the family) theexternal components relative to the reset andpower fail functions can be missed

When a lower output voltage ripple is not requiredit is possible to eliminate the capacitors con-nected at the reference voltage pin of 51V (iepin 14 for Multiwatt package pin 13 for plastic

package)The reset input pin is suggested to connect it togroundThe soft start capacitor value can be reduced to100nF for 5v output voltage

Figure 51 Waveforms for L = 230microH

Figure 52 Waveforms in case of core saturation

10VDiv

1ADiv

1microsDiv

10VDiv

1ADiv

1microsDiv

Figure 53 Low Cost ApplicationCircuit

APPLICATION NOTE

3447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3547

POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3647

Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 35: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3547

POWER SUPPLY COMPLETE WITH MAINSTRANSFORMER

The fig 54 shown a power supply with mains110220Vac transformer diode bridge and filter

capacitor with output voltage adjustable between51V and 24V

Output capacitors have to be chosen with lowESR in order to reduce the output rippleParticularcare has to be taken for input filter capacitors infact they have to support high current spikes atmains frequency and at the same time currentpeak bigger than the output current at the switch-ing frequency

Therefore they must be chosen with low ESR andable to substain high current ripple in order toguarantee a good reliability to all the system

The trasformer can be chosen with a singlewindingand 4 diodesor a center tap with only2 diodeswith

higher reverse voltageA cost reduction of the trasformercan be reachedusing an active power factor corrector

It work at low voltage and the external compo-nents are relatively cheap more details can beobtained looking on the power factor corrector ap-plication note

POWER SUPPLY WITH MAINS HIGH FRE-QUENCY PREREGULATOR

When it is necessary to eliminate the mains tras-

former at 5060Hz for reasons like weight dimen-sions or cost a high frequency preregulator canbe used

A ferrite trasformer reduces the rectifier and fil-tered mains voltage in a convenient voltage tosupply directly the device providing for the isola-tion requirements

Using a free running solution or one of the volt-agecurrent mode controller available it is possi-ble to compensate the input variation while theoutput voltage variations due to the load are usu-ally very low Some examples regarding how touse this regulator in off-line power supply are nowshowed

Flyback Topology

Using a flyback topology with single or doubletransistors is possible to fix a single output volt-

age of 35-40V it can be a bit increased if using abackup battery of 48 nominal VoltsFrom this preregulator (plusmn10) tolerancevoltageis possible to get one or more indipendent out-puts with its own current limitation and thermalprotection

Moreover a possibility to syncronize more de-vices together is available remembering to fix themaster frequency at least 5 higher than the oth-ers device (working as slave) oneIn case of necessity is possible to synronize de-vices on the trasformer secondary with the swith-cing frequency of the controller (See Fig 55)

Figure 54 Typical power supply showing the mains transformer

APPLICATION NOTE

3547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3647

Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 36: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3647

Forward Topology

Further is showed an smps forward circuit wherethe dc-dc converter is used as post-regulator foran auxiliary output (35V) while the main one(51V or 33V) is controlled directly with the feed-back (See Fig 56)

Using a PFC preregulation

When an optimized power factor is required it ispossible to use the following two pricinple dia-

gram that make use of an active power factor cor-rector

1) usingthe standard boost topology (Fig 57)

2) usinga flybacktopology (Fig 58)

The idea is that to generate a stabilized voltagearound 30V - 35V already isolated avoiding to

use an isolation after the PFC section

Figure 55

Figure 56

APPLICATION NOTE

3647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 37: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3747

POWER SUPPLY WITH 0 TO 25V ADJUST-ABLE OUTPUT VOLTAGE

a) It is a classical solution with high performancethat make use of a negative reference voltageequal to the value of the internal voltage of thedevice (51V)

To generate this negative reference voltage it isuseful to equip the mains trnsformer with anothersecondary winding at a low voltage of around

8Vac and capable of delivering a few dozen ofmA

During the phase of starting up and stopping ofthe mains it is important to avoid generating os-cillations around the value of the output voltage including the zero voltage

For this reason a network consisting of two NPNsignal transistors TR1 and TR2 and some resis-tors has been introduced

The transistor TR2 remains is saturation whenTR1 is off untill the output voltage of the negativeregulator reaches 43V

At this point TR1 goes in saturation sending off

TR2 In this way the soft start is blocked and thedevicebegins to work starting in soft start

Switching off the mains voltage the regulatorgenerating the negative volatge is still in regula-tion when the input voltage of the switching con-verter has already dropped below the turn onthreshold

Carefull attention must be given therefore to cal-culate the input capacitor of the two sections inorder to avoid possible malfunctioning during theturning on and turning off

b) a solution that presents a cheaper costs andtha doesnrsquot use a negative reference voltage isthe following

Setting the cursor rdquoPrdquo to the adjustable resistanceat 0V using R1 and R2 the maximum output volt-age can be fixed

In this case we set R1 = 24Kohm and R2 =4K7ohm

In R1 the maximum flowing current will be limitedat 1mA with 1mA flowing in R1 Vo = 30V

Now by reducing the current in R1 the output volt-age Vo canbe adjustedtill to 0V

Figure 58

Figure 57

APPLICATION NOTE

3747

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 38: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3847

The current flowing in backward to have 0V itwill be

I1 = Vref

R1 =

51V

24K = 021mA

∆VR2 = R2 sdot 021= 47k sdot 021 = 1V

Therefore when the cursor rdquoPrdquo reaches Vref + 1Vthe output voltage goes to zero

At this point we are able to define as well the val-ues of P1 and R3

When the rdquoPrdquo cursor is completely moved to highthere should be 6V of dropping to rdquoPrdquo and in thisway 06mA will flow

The current flowing in R3 considering that thevoltage at pin 15 has a typical value of 12V it willbe of 08mA

In this case the R3 value will be 7K5ohm

33V 10A DC-DC CONVERTER

When an output voltage lower to the referencevoltage of 51V must be stabilized with a good re-sult from stability and regulationpoint of view and

Figure 59 10ASwitchingRegulatorAdjustable from 0V to 25V

Figure 60

APPLICATION NOTE

3847

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 39: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 3947

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 40: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4047

Efficiency vs Input Voltage

Vi (V) Io = 10A η Io = 7A η Io = 4A η

12 709 762 82

15 721 767 82

20 729 773 812

25 729 772 806

30 719 764 796

35 683 759 785

Output voltage ripplevs inductorvalueCo = 1000microF10V - EKRESR = 10mΩ

L L = 30microH L = 50microH L = 60microH L = 100microH

∆VOmax 80mV 60mV 40mV 25mV

CURRENT GENERATOR

Often it is required to generate constant current fixed or adjustable for various applications suchas chemical process lamp powering batterycharger for lead acids ni-cd and ni-me-hyd bat-

teries

Figure 63 LoadTransient Response

Figure 64 Load TransientResponse

Id

8

6

4

2

t (ms)

∆Vo

(mV)

+200

0

-200

Io

6

4

2

∆Vo

(mV)

+100

0

-100

t = 1msDiv

L4972A

11

1 5 K

2 2

micro F

78

R2 24K

STPS64030K

13

20

330Ω

1K

220nF

1

9

150microH

470microF

Vo=12V1A

2200microF

Vile40V

D93IN003A

2 2 n F

18

17

2 7 n F

3 0 K

3 9 0 p F

5

10K

01microF

Q2 Q1

R1 50Ω Rsense 100mΩ

Rx

100K

Figure 65 ConstantCurrent Generatorand battery chargers

R2 = 24kΩR1 = 50ΩRsense = 100mΩRx = 100kΩ

APPLICATION NOTE

4047

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 41: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4147

In this paragraph some suggestionswill be givenfor how to abtain generators of constant currentmore or less sophisticated according to the need

The examples given are time by time applicableto the different devices of this family of regulatorswith the necessary adjustement according to thecurrent requiredby the application

The diagram of fig 66 propose a simple solutionthat makes use of two esternal small signal-tran-sistor best if matched in Vbe and some otherpassive components For a cost reductionQ1 canbe substitute by a simple diode 1N4148

The divider composed by R2 and R1 fixes a volt-age at the whished voltage value (for example 50-100mV) on the Q2 emitter

Q2 will be reversed bias untill the emitter voltageof Q1 will raech the same value as itself

At this point Q2 will be direct bias and will beginto absorb current from its collector in the momentin which Q2 will enter into conduction a variation Vsc at the current sense resistor will give a vari-ation of the Q2 currentequal to

∆ICQ2 = ∆VSC

R1

When the current absorbed by Q2 will reach themaximum current delivered by the error amplifieroutput (or by the current of the soft-start if this pinis prefered to use) the error amplifier will fall outof regulation and its output voltage will begin todecrease reducing conseguentely the duty cy-cle then the regulator will begin in this way to be-have as a generator of current instead of voltageThe emitter voltage of Q2 is fixed by the following

formula

VEQ2 = VREF

R1 + R2 R1 = 51V

R1

R1 + R2

A general criterium is that of fixing the dividerrdquoR1R2rdquo in such way as to make a current flowthat is greater than the necessary lowering the

output voltage of the error amplifierThe maximum current delivered by the output ofthe transconduttanceerror amplifier is 200microA thecurrent that has to flow in the divider R1R2 shouldbe around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more softinterventions

By varying the value of R2 the point of interven-tion of the current limitation will be moved

The resistor Rx contributes to introducing a moreor less accentuate foldback effect on the outputcurrent

In the following table suggest a few values of

Rsense according to the nax output current

Rsense (mΩ) Io (A) Device

10153050100

1075

352

L4970AL4977AL4975AL4974AL4972A

The criterium used to defined the value of thesense resistor is essentially tied to the max powerdissipated by the resistance as well as to themarket availability

If the mains objective is to maximize the efficiency

OUTPUT

STAGEPWM

E A

+

-

51

2 1 10 15 14 8

L4972A74A

6

11

9

LM358+-

100nF

100

47K100

Rs

V+

Iomax=V+

RsV+=

51 100

100+47K~100mV

D93IN004

Figure 66

APPLICATION NOTE

4147

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 42: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4247

when (delivering for example 10A) it is conven-ient to use two current transformers instead of adissipative resistor one in series to the source ofthe internal DMOS and one in series to the catchdiode

Using such solution a quite simple and fine regu-lation of the current is possible to implement

Figure 66 shows a current generator solution withhigh precision on the current using an opampin-stead of two small signal transistors

Higher input voltage

Since the maximum operating input voltage of thisfamily is 50V when one of these devices must besupplied with more elevated voltages it is neces-sary to introduce a preregulator

Fixing the output voltage of the preregulator of

45V the power dissipationof the preregulator isPd = Ii sdot VCE sdot = Ii sdot (Vi - 45)

In the buck converter the average input currentis

Ii = Io sdot Ton

T = Io sdot

Vo

Vi

DESIGN EXAMPLE FOR L4974A

(a) (b)

Vo = 51V Io = 35APo = 1785W

Vo = 12V Io = 35APo = 42W

Ii = 0388A Ii = 0933A

With an operating input voltage of 60V the preregula-tor will dissipate

Pd = 582W Pd =134W

The overall efficiency will be

n = 68 n = 70

Up Down Converter

In some applications it is required to stabilize avoltage starting from an input voltage which canbe lower or higher then the output regulated volt-

ageIn this case a well known buck-boost topology issuggested

The fig 68 which shows the electrical diagram ofthe up-down converter makes use of the L4974Ato generatean output voltage of 12Vat 3A

For output current lower or higher than 3A otherdevices of this family can be used For input volt-age less than 20V the zener diode can beavoided

Such circuit can also be used as a simple step-up In this case there is a structure of the rdquoasym-metrical two transistor converterrdquo type that in the

case of a short circuit is automatically protectedsince the internal transistor turn-off disconnectingthe power supply

This doesnrsquot happen in the classical step-up con-verter topology in which during the short circuitonly the power transistor is protectedbut the cur-rent in the coil and the freewheeling diode is notlimited

Negative Output Voltage

Often it becomes necessary in the multioutputpower supplies to generate negative voltageswith current higher than 1A maintaining an ele-vatedefficiency of the system

Such outputs must have a good precision andstability and must be protected from short circuit-ing

With the application circuit suggested below onethe aime is to satisfy the performance listedabove and to contributing to the simplification of

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18 5

15K

2 2 n F

20

SB560

220nF

1

150microH

3 x100microFEKR

2200

microF

Vi=50 to 70V

D93IN005

BDW23C

3K

10microF 4 7 V

3 3 0 0 micro F

5 0 V 7

390pF

Vo=5V

9

Figure 67 DesignExample for L4974A

APPLICATION NOTE

4247

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 43: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4347

the power trasformer both at 50Hz and at highfrequency

Itrsquos important to remember not to exceed the ab-solute maximum voltage ratings of the device Inthis case the differentialvoltage applied to the de-vice is the sum of the maximum input voltage(positive) and of that controlled output negative

Linear low drop post regulation

In some application it becomes necessary to gen-

erate stable precise fixed or adjustable outputvoltages at high efficiency and with a truly negli-gible output ripple Summarizing a regulator thatoffers the quality of a linear type of control withthe efficiency of a switching regulator The fig 70shows the diagram of a swithcing preregulator athigh efficiency followed by one or more seriesregulators of the type very rdquolow droprdquo or in thecase of elevated current by a discret low drop so-lution

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 18

561516

15K

2 2 n F

20

SB560

220nF

1 100microH

470microF

1000microF

12VltVile35V

D93IN009

7

3 9 0 p F

9

62K

47K

-12V

Figure 69 Circuit for negative output voltage

2 7 n F

L4974A

11

3 0 K

2 2

micro F

178 1856

1516

15K

2 2 n F

20

S B 5 6 0

220nF

1 150microH

3 x

100microFEKR

1000microF

12VltVile50V

D93IN008A

7

3 9 0 p F

Vo=18V3A

9

1 K 56nF

12K

47K

SB560

Dz

20V

Figure 68

APPLICATION NOTE

4347

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 44: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4447

LAYOUT CONSIDERATIONS

Both for linear and switching power supplieswhen the current exceeds 1A a careful layout be-comes important to achieve a good regulationThe problem becomes more evident when de-signing switching regulators in which pulsed cur-rents are over imposed on dc currents In drawingthe layout therefore special care has to be takento separate ground paths for signal currents andground paths for load currents which generallyshow a muchhigher value

When operating at high frequencies the pathlenght becomes extremely important The pathsintroduce distributed inductances producing ring-ing phenomena and radiating noise into the sur-rounding space

The recirculation diode must be connected closeto output pin to avoid giving rise to dangerousex-tra negative voltages due to the distributed induc-tance

HEATSINK DIMENSIONING

The heatsink dissipates the heat produced by thedevice to prevent the internal temperature fromreaching values which could be dangerousfor de-vice operationand reliability

Integrated circuits in plastic package must never

exceed 150degC even in the worst conditions Thislimit has been set because the encapsulating

resin has problems of vitrification if subjected totemperaturesof more than 150degC for long periodsor of more than 170degC for short periods In anycase the temperature accelerates the ageingprocess and thereforeinfluences the device life Awell designed heatsink should keep the junctiontemperature between 90degC and 110degC Fig 71shows the structure of a power device As dem-onstrated in thermo-dynamics a thermal circuitcan be considered to be an electrical circuitwhere R1 R2 represent the thermal resistance ofthe elements (expressed in degCW) (see fig 72)

C1 C2 are the thermal capacitance (expressed indegCW)

I is the dissipated power

V is the temperature difference with respect tothe reference (ground)

This circuit can be simplified as shown in fig 74where

CC is the thermal capacitance of the die plusthat of the tab

Ch is the thermal capacitance of the heatsink

R jc is the junction case thermal resistance

Rth is the heatsink thermal resistance

HIGH POWERPREREGULATOR

L1 L2

C2

L7805

L7812

L4805

5V1A

12V1A

5V04A

D93IN010A

L2 and C2 are necessary to reduce the switching frequency spikes

Figure 70

APPLICATION NOTE

4447

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 45: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4547

But since the aim of this section is not that ofstuding the transistors the circuit can be furtherreduced as shown in figure 74

If we now consider the ground potential as ambi-ent temperaturewe have

T j = Ta + (R jc + Rth) Pd a)

Rth = T j minus Ta minus R jc Pd

Pdb)

TC = Ta + Rth Pd c)

Thermal contact resistance depends on variousfactors such as the mounting contact area andplanarity of the heatsink With no material be-tween the device and heatsink the thermal resis-tance is around 05degCW with silicone greaseroughly 03degCW and with silicone grease plus amica insulator about 04degCW See fig 75 In ap-plication where one external transistor is used to-gether the dissipated power must be calculatedfor each component The various junction tem-perature can be calculated by solving the circuitshown in fig 75 This applies if the dissipating

elements are fairly close with respect to the dissi-pator dimensions otherwise the dissipator can nolonger be considered as a concentrated constantand the calculation becomes difficult This con-cept is better explained by the graph in fig77which shows the case (and therefore junction)temperature variation as a function of the dis-tance between two dissipating elements with thesame type of heatsink and the same dissipatedpower The graph in fig 77 refers to specific caseof two elements dissipating the samepower fixedon a rectangular aluminium plate with a ratio of 3between the two sides The temperature jump willdepend on the total dissipated power and on thedevices geometrical positions We want to show

that there exists an optimal position between thetwo devices

d = 1

2 sdot side of the plate

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

APPLICATION NOTE

4547

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 46: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4647

Fig 78 shows the trend of the temperature as afunction of the distance between two dissipatingelements whose dissipated power is fairly differ-ent (ratio 1 to 4) This graph may be useful in ap-plications with two devices in MTW package aresynchronized

REFERENCES

1) AN244 rdquoDesigning with the L296 monolithic power switching regulatorrdquo (Ref Designerrsquo Guide to Power ProductsApplication Manual)

2) Table1 (see page 31-3246) ndash EKR amp EKE Roederstein Low Voltage Electrolytic Capaci- tors

Figure 77

Figure 78

APPLICATION NOTE

4647

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE

Page 47: L4970A Design Considerations

8192019 L4970A Design Considerations

httpslidepdfcomreaderfulll4970a-design-considerations 4747

Information furnished is believed to be accurate and reliable However SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use Nolicense is granted by implicationor otherwise under any patent or patent rights of SGS-THOMSON Microelectronics Specification mentionedin this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectronics

983209 1997 SGS-THOMSON Microelectronicsndash Printed in Italy ndash All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - USA

APPLICATION NOTE