L4: Sequential Building Blocks (Flip-flops, Latches and ...web.mit.edu/6.111/www/s2009/LECTURES/l4.pdf · Use negative clock phase to latch inputs into first latch Use positive clock

L4: 6.111 Spring 2009 1Introductory Digital Systems Laboratory

L4: Sequential Building Blocks

(Flip-flops, Latches and Registers)

Acknowledgements:

Lecture material adapted from R. Katz, G. Borriello, “Contemporary Logic Design” (second edition), Prentice-Hall/Pearson Education, 2005.

Lecture material adapted from J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective” Copyright 2003 Prentice Hall/Pearson.

Lecture notes prepared by Professor Anantha Chandrakasan


Combinational Logic Review

Combinational logic circuits are memorylessNo feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settledOutputs can have multiple logical transitions before settling to the correct value

CombinationalCircuit

in0

in1

inN-1

in0

in1

inM-1


A Sequential System

Sequential circuits have memory (i.e., remember the past)The current state is “held” in memory and the next state is computed based the current state and the current inputsIn a synchronous systems, the clock signal orchestrates the sequence of events

Memory element


A Simple Example

in0

in1

in2 inN-1

Adding N inputs (N-1 Adders)

inD Q

reset

clk

Current_Sum

Using a sequential (serial) approach


Implementing State: Bi-stability

Vi1

A

C

B

Vo2

Vi1 = Vo2

Vo1 Vi2

Vi2 = Vo1

Vo1 = Vi2

Vo2 = Vi1

Point C is Metastable

Vi2

=V

o

Vi1 = V o2

A

δ

Vi2

=V

o1

Vi1 = Vo2

C

δ

1

Points A andB are stable(represent 0 & 1)

B


NOR-based Set-Reset (SR) Flipflop

Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) – this circuit is not clocked and outputs change “asynchronously” with the inputs

Forbidden State

S

S

R

Q

Q

Q QRS Q

Q00 Q

101 0

010 1011 0

R Q

Reset Hold Set SetReset

R

S

Q

Q ??


Making a Clocked Memory Element:Positive D-Latch

CLK

D Q

D Q

clk

A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i.e., ignores input D)A Latch is level-sensitive: invert clock for a negative latch

S

R

clock

R and S

sample hold sample holdhold

G


Multiplexer Based Positive & Negative Latch

1

0in0

in1

out

SEL

Out = sel * in1 + sel * in0

2:1 multiplexer

1

0

DQ

CLK

Positive Latch

0

1

DQ

CLK

Negative Latch

"remember"

"load""data" "stored value"

clkclk


74HC75 (Positive Latch)


Building an Edge-Triggered Register

Master-Slave RegisterUse negative clock phase to latch inputs into first latchUse positive clock to change outputs with second latch

View pair as one basic unitmaster-slave flip-flop twice as much logic

D

G

Q D

G

Q

Clk

DNegative latch Positive latch

QD

Clk

Q QDQM


Latches vs. Edge-Triggered Register

Edge triggered device sample inputs on the event edge

Transparent latches sample inputs as long as the clock is asserted

Timing Diagram:

Behavior the same unless input changes while the clock is high

7474

7475

Bubble herefor negative

edge triggeredregister

Positive edge-triggered register

Level-sensitive latch

D Q

D Q

C

Clk

Clk

D

Clk

Q

Q

7474

7475


Important Timing Parameters

Setup Time (Tsu)

Clock: Periodic Event, causes state of memoryelement to change

memory element can be updated on the: rising edge, falling edge, high level, low level

There is a timing "window" around the

clocking event during which the

input must remain stable and

unchanged in order to be recognized

Minimum time before the clocking event by which the input must be stable

Hold Time (Th)Minimum time after the clocking event during which the input must remain stable

Input

Clock

T su T h

Propagation Delay (Tcq for an edge-triggered register and Tdq for a latch)

Delay overhead of the memory element


74HC74 (Positive Edge-Triggered Register)

74HC74(courtesy TI)

D-FF with preset and clear


The J-K Flip-Flop

S

R

Q

Q

J

K

Eliminate the forbidden state of the SR Flip-flopUse output feedback to guarantee that R and S are never both one

J K Q+ Q+

0 0 Q Q

0 1 0 1

1 0 1 0

1 1 Q Q


J-K Master-Slave Register

S

R

Q

Q

J

K

S

R

Q

Q

CLK

Sample inputs while clock high Sample inputs while clock low

Correct ToggleOperation

P

P

Is there a problem with this circuit?


Pulse Based Edge-Triggered J-K Register


Pulse-Triggered Registers

Master-Slave Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Based Register

L1 L2 Latch

Ways to design an edge-triggered sequential cell:

Pulse registers are widely used in high-performance microprocessor chips (Sun Microsystems, AMD, Intel, etc.)The can have a negative setup time!

Short pulse around clock edge


D Flip-Flop vs. Toggle Flip-Flop

T

Clk

QT (Toggle)

Flip-Flop

0 1

1

1

0T QN

0 Q N-1

1 QN-1

0

D

Clk

QD Flip-Flop

0 1

0

1

0

D QN

0 01 1

1


Realizing Different Types of Memory Elements

Characteristic Equations

D:

J-K:

T:

Q+ = D

Q+ = J Q + K Q

Q+ = T Q + T Q

E.g., J=K=0, then Q+ = QJ=1, K=0, then Q+ = 1J=0, K=1, then Q+ = 0J=1, K=1, then Q+ = Q

Implementing One FF in Terms of Another

D implemented with J-K J-K implemented with D


Design Procedure

Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?

Implementing D FF with a J-K FF:1) Start with K-map of Q+ = ƒ(D, Q)

2) Create K-maps for J and K with same inputs (D, Q)

3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map

E.g., D = Q= 0, Q+ = 0then J = 0, K = X

D 0 1 0 1

T 0 1 1 0

Q +

0 1 0 1

Q 0 0 1 1

K X X 1 0

J 0 1 X X


Design Procedure (cont.)

Implementing J-K FF with a D FF:1) K-Map of Q+ = F(J, K, Q)

2,3) Revised K-map using D's excitation tableits the same! that is why design procedure with D FF is simple!

Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identicalto the characteristic equation for a J-K FF.


System Timing Parameters

D

Clk

QIn CombinationalLogic

D

Clk

Q

Register Timing Parameters

Tcq : worst case rising edge clock to q delay

Tcq, cd: contamination or minimum delay from clock to q

Tsu: setup timeTh: hold time

Logic Timing Parameters

Tlogic : worst case delay through the combinational logic network

Tlogic,cd: contamination or minimum delay through logic network


System Timing (I): Minimum Period

D

Clk


D

Clk

Q

CLK

Tsu

Th

Tsu

Th

Tcq

Tcq,cd

Tcq

Tcq,cd

FF1

IN

CLout

CLout

Tl,cdTsu2

Tlogic

T > Tcq + Tlogic + Tsu


System Timing (II): Minimum Delay

D

Clk


D

Clk

Q

CLK

Tsu

Th Th

Tcq,cd

FF1

IN

CLout

Tl,cd

Tcq,cd + Tlogic,cd > Thold

CLout


Shift-Register

all measurements are made from the clocking event that is,

the rising edge of the clock

Typical parameters for Positive edge-triggered D Register

Th5ns

Tw 25ns

Tplh25ns13ns

Tphl40ns25ns

Tsu20ns

D

CLK

Q

Tsu20ns

Th5ns

IN

Q0

Q1

CLK

100

CLK

INQ0 Q1

DQ DQ OUT

Shift-register

Documents

L4: Sequential Building Blocks (Flip-flops, Latches and ...web.mit.edu/6.111/www/s2009/LECTURES/l4.pdf · Use negative clock phase to latch inputs into first latch Use positive clock