SungKyunKwan Univ.

1VADA Lab.

L35: Lower Power Voltage Scaling

1999. 8.

성균관대학교 조 준 동 http://vada.skku.ac.kr

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2VADA Lab.

Voltage Scaling

• Merely changing a processor clock frequency is not an effective technique for reducing energy consumption. Reducing the clock frequency will reduce the power consumed by a processor, however, it does not reduce the energy required to perform a given task.

• Lowering the voltage along with the clock actually alters the energy-per-operation of the microprocessor, reducing the energy required to perform a fixed amount of work.

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3VADA Lab.

Dynamic Voltage Scaling(DVS)

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4VADA Lab.

Processor Usage Model

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5VADA Lab.

OS: Voltage Scaling

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6VADA Lab.

Scale Supply Voltage with fCLK

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7VADA Lab.

Adaptive Power Supply Voltages

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8VADA Lab.

Variable Supply Voltage Block Diagram

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9VADA Lab.

Typical MPEG IDCT Histogram

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10VADA Lab.

Voltage scheduling under timing constraints

– Energy consumption of a processor:• 10nJ/cycle at 2.5V

• 25nJ/cycle at 4 V

• 40nJ/cycle at 5V

– maximum clock frequencies:• 50MHz at 5V, 40MHz at 4V, 25MHz at 2.5V

– Given that an application needs 1000M cycles to finish and the timing constaint is 25sec.

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11VADA Lab.

Different Voltage Schedules

0 5 10 15 20 25 Time(sec)

5.021000Mcycles50MHz

40J

(A)

0 5 10 15 20 25 Time(sec)

5.02750Mcycles50MHz

32.5J

(B)

0 5 10 15 20 25Time(sec)

5.02

1000Mcycles40MHz

25J (C)

Timing constraint

2.52

250Mcycles25MHz

4.02

En

ergy

con

sum

pti

on (

Vd

d2 )

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12VADA Lab.

Example of Variable Supply

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13VADA Lab.

DVS Implementation

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14VADA Lab.

Variable Supply Voltage Block Diagram

• Computational work varies with time. An approach to reduce the energy consumption of such systems beyond shut down involves the dynamic adjustment of supply voltage based on computational workload.

• The basic idea is to lower power supply when the a fixed supply for some fraction of time.

• The supply voltage and clock rate are increased during high workload period.

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15VADA Lab.

Data Driven Signal Processing

The basic idea of averaging two samples are buffered and their work loads are averaged.

The averaged workload is then used as the effective workload to drive the power supply.

Using a pingpong buffering scheme, data samples In +2, In +3

are being buffered while In, In +1

are being processed.

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16VADA Lab.

Example of Buffering

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17VADA Lab.

Graphical Interpretation

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18VADA Lab.

Buffering Example: MPEG Decoder

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19VADA Lab.

DVS

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20VADA Lab.

DVS Scheduling Frameworkµ

Pro

c. S

peed

Time

Start Deadline Start Deadline

Idle time represents

wasted energy

Lower speed,Lower voltage, Lower energy

Energy ~ Work • Speed

WorkWork

• Use real-time framework toconstrain task voltage scheduling

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21VADA Lab.

DVS SimulationS

peed

Time

S1 S2 S3 D1 D3 D2 Task Variance

Weather

Interrupts

User Input

Cache Behavior

Scheduling Overhead

IntercomIntercom

RealityTheory ImplementationSimulate run-time scheduler to

fully understand voltage-scaling behavior

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22VADA Lab.

Simulation InfrastructureGUI

Run-timeScheduler

VoltageScheduler

Applicationsupport libraries

MPEG Priority 80GUI Priority 23

MPEG Priority 80GUI Priority 23

Speed Priority

{ Frame_Start(deadline); Decode_MPEG_Frame(); Frame_Finish();}

{ Frame_Start(deadline); Decode_MPEG_Frame(); Frame_Finish();}Windowing

Cryptography

I/O Support

lpARM

MPEG

Develop support environment tomodel complete software system

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23VADA Lab.

Run-Time Voltage Scaling

73%

58%

25%16%

65%

46%

15%20%

0%

20%

40%

60%

80%

100%

Audio GUI MPEG Audio &MPEG

To

tal

Sy

ste

m E

ne

rgy

DVS SimulationPost-Trace Optimal

Normalized to 3.3V

fixed-voltage processor

Combination of independent

benchmarks

• Dynamic Voltage Scalingsignificantly reduces energy dissipation!

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24VADA Lab.

Run-Time Performance AnalysisFrame Computation Histogram

0%

20%

40%

60%

80%

100%

Fixed-V Frame Execution Time

AudioGUIMPEG

DVS System Energy

0%

20%

40%

60%

80%

100%

To

tal S

ys

tem

En

erg

y

Basic AlgorithmAdjusted AlgorithmPost-Trace Optimal

Audio MPEG GUI

Software can automatically recognize and adjust for

bi-modal GUI distribution

0 2x deadline

Normalized to deadline at max processor speed

• Application characteristics strongly affectvoltage scaling performance

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25VADA Lab.

Compute ASAP+ System Shutdown

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26VADA Lab.

Another Approach: Reduce Clock Frequency

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27VADA Lab.

Voltage Scheduling II

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28VADA Lab.

Evaluation: Algorithms

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29VADA Lab.

AVG<weight>

• Computes an exponentially moving average of the previous intervals. At each interval the run-percent from the previous interval is combined with the previous running average, forming a long-term prediction of system behavior. <weight> is the relative weighting of past intervals relative of the current interval (larger value means a great weight on the past) using the equation (weight X old + new)/(weight+1). 3 can be used.

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30VADA Lab.

OS: Voltage Scheduling

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31VADA Lab.

Run-Time Scheduling Dynamicsµ

Pro

c. S

peed

Time

Thread accomplishing more than expected,

reduce speedDeadline exceeded,

increase speedHigher-priority

task

Run faster to make up lost time

Initial speed estimate

Optimal scheduleE(work)

Workload calculated to be average of previous frames

• Periodically re-evaluate schedule toadjust for unforeseen events

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32VADA Lab.

Vertical Layering

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33VADA Lab.

Optimal Scheduling• For a region spanned by a given task

specification, each point in time will either be scheduled at the minimum speed spanned by that task or else the task will not be scheduled to run at that point.

Algorithm• n tasks to schedule• O(n) speed settings to consider for each task• O(n) linked tasks requiring adjustment for

each setting: Total complexity: O(n 3 ) time.

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34VADA Lab.

Scheduling step0

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35VADA Lab.

Scheduling step1

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36VADA Lab.

Scheduling step2

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37VADA Lab.

Scheduling step3

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38VADA Lab.

Scheduling step4

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39VADA Lab.

Scheduling step5

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40VADA Lab.

References• [Lin97] Lin et al., "Scheduling Techniques for Variable Voltage Low Power Designs," ACM Transaction

s on Design Automation of Electronic Systems, vol. 2, no. 2, pp. 81-97, 1997.

• [Govil95] - Extended simulation with practical algorithms on traces of UNIX workstations• [Kuroda98] - Implementation of DVS processor to mitigate effects of process variation• [Ishihara98] - Dynamic voltage scaling with non- constant capacitances• S. Gary, et. al., "The PowerPC 603 Microprocessor: A Low-Power Design for Portable Applications," Pr

oceedings of the Thirty-Ninth IEEE Computer Society International Conference, Mar. 1994, pp. 307-15.

• A. Chandrakasan, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995.

• C. Nagendra, et.al., "A Comparison of the Power-Delay Characteristics of CMOS Adders,” Proceedings of the International Workshop on Low Power Design, Apr. 1994, pp. 231-6.

• T. Callaway and E. Swartzlander, "Optimizing Arithmetic Elements for Signal Processing," VLSI Signal Processing, Vol. 5, New York: IEEE Special Publications, 1992, pp. 91-100.

• T. Biggs, et. al., "A 1 Watt 68040-Compatible Microprocessor," Proceedings of the IEEE Symposium on Low Power Electronics, Oct. 1994, pp. 8-11.

• J. Lorch, A Complete Picture of the Energy Consumption of a Portable Computer, M.S. Thesis, University of California, Berkeley, 1995

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41VADA Lab.

References• S. Kunii, "Means of Realizing Long Battery Life in Portable PCs," Proceedings of the I

EEE Symposium on Low Power Electronics, Oct. 1995, pp. 12-3.

• M. Culbert, "Low Power Hardware for a High Performance PDA," Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, Mar. 1994, pp. 144-7.

• T. Ikeda, "ThinkPad Low-Power Evolution," Proceedings of the IEEE Symposium on Low Power Electronics, Oct. 1995, pp. 6-7.

• A. Chandrakasan, A. Burstein, and R.W. Brodersen, "A Low Power Chipset for Portable Multimedia Applications," IEEE Journal of Solid State Circuits, Vol. 29, Dec. 1994, pp. 1415-28.

• M. Horowitz, T. Indermaur, and R. Gonzalez, "Low-Power Digital Design," Proceedings of the IEEE Symposium on Low Power Electronics, Oct. 1994, pp. 8-11.

• D. Lidsky and J. Rabaey, "Early Power Exploration - A World Wide Web Application," Proceedings of the Thirty-Third Design Automation Conference, June 1996.

• T. Burd, Low-Power CMOS Cell Library Design Methodology, M.S. Thesis, University of California, Berkeley, UCB/ERL M94/89, 1994.

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42VADA Lab.

• A. Chandrakasan, S. Sheng, and R.W. Brodersen, "Low-Power CMOS Digital Design," IEEE Journal of Solid State Circuits, Apr. 1992, pp. 473-84.

• Advanced RISC Machines, Ltd., ARM710 Data Sheet, Technical Document, Dec. 1994.

• Integrated Device Technology, Inc., Enhanced Orion 64-Bit RISC Microprocessor, Data Sheet, Sep. 1995.

• Intel Corp., Embedded Ultra-Low Power Intel486TM GX Processor, SmartDieTM Product Specification, Dec. 1995.

• A. Stratakos, S. Sanders, and R.W. Brodersen, "A Low-voltage CMOS DC-DC Converter for Portable Battery-operated Systems," Proceedings of the Twenty-Fifth IEEE Power Electronics Specialist Conference, June 1994, pp. 619-26.

• J. Bunda, et. al., "16-Bit vs. 32-Bit Instructions for Pipelined Architectures," Proceedings of the 20th International Symposium on Computer Architecture, May 1993, pp. 237-46.

• Advanced RISC Machines, Ltd., Introduction to Thumb, Developer Technical Document, Mar. 1995.

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43VADA Lab.

• J. Bunda, W.C. Athas, and D. Fussell, "Evaluating Power Implications of CMOS Microprocessor Design Decisions," Proceedings of the International Workshop on Low Power Design, Apr. 1994, pp. 147-52.

• P. Freet, "The SH Microprocessor: 16-Bit Fixed Length Instruction Set Provides Better Power and Die Size," Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, Mar. 1994, pp. 486-8.

• T. Burd, B. Peters, A Power Analysis of a Microprocessor: A Study of an Implementation of the MIPS R3000 Architecture, ERL Technical Report, University of California, Berkeley, 1994.

• J. Montanaro, et. al., "A 160MHz 32b 0.5W CMOS RISC Microprocessor," Proceedings of the Thirty-Ninth IEEE International Solid-State Circuits Conference - Slide Supplement, Feb. 1996, pp. 170-1.

• J. Bunda, Instruction-Processing Optimization Techniques for VLSI Microprocessors, Ph.D. Thesis, The University of Texas at Austin, 1993.

• R. Gonzalez and M. Horowitz, "Energy Dissipation in General Purpose Processors," Proceedings of the IEEE Symposium on Low Power Electronics, Oct. 1995, pp. 12-3.