Key Lecture Concepts for CoE225/EE 271 (Mostly Digital ...hychang/ece271_files/Lesson 4... · Web viewCircuits for DC Bias Analysis (without The Analog Signal Generator Connected)

ECE 271 Electronics Lecture Notes Lesson Four

Key Lecture Concepts for CoE225EE 271 (Mostly Digital Electronics) by RHCornely Sept 27 2005 All Copyrights Reserved

LESSON FOUR The MOS Field-Effect Transistor (MOSFET) MOSFET Circuit Analysis Examples Logic Circuit Concepts Voltage Transfer Characteristics Noise Margins and Digital Gain Introduction to the Dynamic Response of Logic Gates Appendices Characteristics of other FET Devices Introduction to the Properties of Semiconductor Materials the MOS Transistor (MOSFET) Review of the Historical Development of Computer Hardware and the Need for Three-Terminal Devices

Lesson Overview A major goal of this course is to develop an understanding of how computers work from a hardware point of view Digital signals lose amplitude and their rise and fall times become worse as they propagate from the inputs to the outputs of a digital system on the conductors between devices that perform logic and memory operations Therefore it is necessary to regenerate the signals by providing digital signal amplification or digital gain It is also necessary to prevent signals intended to propagate towards an output of a digital system from propagating back and influencing other signals introducing errors A three-terminal device is necessary to provide this isolation of input and output signals or directionality of signal propagation The MOS transistor has proven to be an outstanding device for providing these two requirements of digital logic circuits digital gain and signal directionality Of great significance is that the millions of MOS transistors required for computer logic and memory can be mass-fabricated on the surface of low cost silicon material

A major learning objective of the lesson presented in section A is to be able to understand the IV characteristics of the MOS field-effect transistor MOSFET) The MOSFET is a three-terminal device consisting of a control gate terminal whose voltage controls the flow of current between the two other terminals the source and the drain Two current-voltage (IV) characteristics are necessary to describe the operation of the FET One is the dependence of the output current as a function of the voltage difference between the input gate and the source The second is the dependence of the output current on the voltage between the two terminals that the output current flows between (the drain and the source) The junction field-effect transistor is a device with similar IV characteristics of the MOSFET It is described in Appendix 41 To further understand the objective of the lesson the first paragraph of the Summary in Section G should be read

The lesson objective of section B is to introduce basic MOSFET circuits with a resistor as the load for either p or n-channel MOSFET For digital circuits the MOSFET serves as a switch and for analog circuits it amplifies small ac signals between the gate input and the source The load serves to isolate the output terminal from the power supply used for the source drain voltage drop necessary to obtain current Actual MOSFET circuits used MOSFET loads the resistor load in this lesson is used for tutorial purposes only A mathematical as well as a graphical or ldquoload linerdquo approach for finding the Q points of these basic circuits will be shown Then the important logic circuit concepts of the voltage transfer characteristic (output circuit voltage versus input voltage) digital gain (the change in output voltage for a change in input voltage) fan-out and fan-in capability

propagation and pair signal delay times and the power-delay time product will be introduced

The lesson concludes with a concise description of noise ie undesirable coupling of voltages and currents from one wire to another nearby wire The electromagnetic phenomena causing the signal coupling will be described by sketches that show that the complex electromagnetic ldquopickuprdquo of noise signals onto wires and device terminals can be accounted for by capacitance and inductance that provide a simple model for the electromagnetic phenomena The lesson explains how the effects of the unwanted noise can be minimized by designing a digital circuit so that the output versus input voltage transfer characteristic will have a ldquonoise marginrdquo that protects against the noise signal causing an error eg the output becoming a one when it should be a zero Some discussion of the minimization of noise by optimizing the layout of wires connecting the devices is given

There are three appendices at the end of the lesson that would be nice to study in ECE 271 except that study time for many students is limited Appendix 41 presents the terminal currentvoltage characteristics for other types of FET devices such as the JFET and MESFET They are practically the same as those for the MOSFET You will need the JFET equations for other courses Appendix 42 offers a review of the basic properties of semiconductors as background to understand how the MOSFET characteristics depend on material properties and FET structure and dimensions However it is possible to learn how to design and analyze digital circuits starting with the FET characteristics without learning the device physics material science and manufacturing techniques on which the characteristics depend Therefore it is optional during this course to learn the basic subjects presented in appendix 42 You are encouraged to read appendix 42 at least once to get a feeling for the subject and to study the concepts in A-42 in the near future The knowledge of semiconductor devices will enable you to follow and anticipate the exciting developments of the components and systems that will be the heart of future generations of not only computers but also many other important solid state products such as sensors displays miniature robots laser beam switches and novel every-day products as watches vehicle components and medicines whose low-cost production is based on solid state technology

Appendix 43 expands on the first paragraph of this overview by presenting a brief review of the history of computer hardware This historical overview outlines how electronics technology evolved over the last 6 decades It should be read as a news article and not studied because of your limited time The section aims to give you an appreciation of the microelectronic devices and circuits that will be studied in the upcoming lessons and those that will be part of technology in the coming decades

A) Basic Concepts for the Metal-Oxide-Semiconductor Transistor (MOST)

There are four basic types of MOS transistors N-type EMOS P-type EMOS N-type DMOS and P-type DMOS Column one of fig41 lists the four transistor types Also in this column are the key parameters for each device the threshold voltage VT the gain factor K and the width to length ratio WL Typical values for 2005 for each parameter also are given under each name These parameters completely determine the device IV characteristic just as IS and nVT did for the diode Unlike the diode which has a single IV curve the three-

terminal MOST is described by two IV characteristics The transfer characteristic which is sketched in column 3 and the drain characteristic sketched in column 4 Before discussing in more detail these important characteristics we will review basic concepts for electrical conduction using fig42 and then look at the structure of a transistor as presented in fig43 and discuss briefly the physical operation of the device

The basic concepts for conduction in semiconductors are presented in fig42 As listed in the bottom half of the page there are 4 types of charges in semiconductors The mobile negative charge (electrons) and the mobile positive charge (holes) provide the carriers for current due to applied voltage The two other charges are fixed ie immobile They are the doping atoms that provide the mobile carriers Donor doping atoms provide (or donate) mobile electrons Acceptor doping atoms provide the mobile plus-charge holes The symbols for the four charges are used in eg fig44 to explain the structure and operation of MOSFETs Appendix 42 presents in more detail the generation and conduction processes in semiconductors A brief summary is the following and does not have to be learned until the other concepts of this lesson are mastered Holes actually are due to electrons that jump between vacancies in the electronic bonding structure of the acceptor atoms An electron will jump from a position in the bond structure towards the right into a vacancy in the bonding structure if an electric field points to the left When the electron jumps to the right it leaves behind a vacancy on the left Thus the motion of the electron to the right opposite the electric field results in the vacancy moving to the left This vacancy motion to the left is equivalent to positive charge moving to the left Thus the motion of the electrons appears as a positive charge moving in the direction of the electric field (Actually doping atoms (dopants) at very high temperatures eg1000 degrees centigrade do move from a high concentration to a lower concentration of dopants this high temperature diffusion motion is necessary to put them into the silicon material However for understanding the operation of transistors at normal it is convenient to consider the dopants to be immobile)

Silicon that has mainly donor atoms added to pure silicon material is called N-type silicon Silicon that mainly has acceptor atoms added to the host silicon atoms is called P-type silicon P refers to the resultant mobile positive charge and N to the resultant mobile negative charge Equation one in fig42 presented also below gives the dependence of the resistance (R) of a sample of semiconductor material on its resistivity and dimensions width W thickness t and length L Fig42 also shows the current and electric field directions in response to a voltage V across the material and the motion of any holes or electrons in the material The equations that relate the mobility of carriers and their concentration in either N or P type semiconductor material to the conductivity of the material are next to equation Note that and q is the electron charge 16 bull 10 ndash19 [coul]

1) R = [ohm-cm]L[cm] divide W [cm] t [cm] = q N n = 1 P = q P p = 1P

Table 41 after fig42 is provided to give the reader a feeling for the resistivity values for commonly used metals semiconductors and insulators Equation 1 applies to all materials of course This amazing wide range of resistivity 1023 is very helpful in the design of devices and circuits for the microelectronics powerenergy microwave etc industries

Besides N and P type semiconductor material there is intrinsic material which has basically only the host atoms eg silicon and is relatively non-conductive It has a large resistivity of about 1000 ohm-cm at room temperature (2930K)

Table 42 lists the types of charges typical doping concentration ranges and corresponding resistivity and conductivity values for the 3 types of silicon material The typical concentration values for doping atoms are much smaller than the concentration of the host atoms in silicon 5 times 1022 [cm ndash3] Also given are values for the mobility of electrons and holes and P The units for mobility by dimensional analysis are cm2 per volt-sec

Fig43 shows the major features of the structure of an N-MOST transistor As shown in fig43a a MOSFET is composed of a MOS ldquocapacitor-like sandwichrdquo which has a highly conducting metal gate (G) serving as the top plate This metal plate is typically 1000 to 10000 Angstroms (A) thick Under the top plate is a very thin insulating oxide layer (from 20 to 500A thick) The relatively thick semiconductor silicon substrate (typically about 200 to 500 m) serves as the bottom plate [Recall that 3 to 4 A is the distance between atoms that one micron is 10000 A and that a human hair is 50 to 100 microns thick It is suggested that colored pens be used to color the metal regions eg blue and the more conducting semiconductor source and drain regions in the semiconductor red so that they stand out] Looking at the cross-section note that charge or current can not go from the gate terminal to the semiconductor because the gate metallization is separated from the silicon substrate by the highly insulating non-conducting oxide The two conducting regions the metal gate and the semiconductor substrate serve as the ldquoplatesrdquo of a capacitor with the highly insulating region between the plates usually an oxide grown by heating a silicon substrate in oxygen at eg 1000 C

A ldquochannelrdquo of negative charge can be formed at the oxide interface by applying positive voltage to the gate as shown in fig43b The channel then serves as the lower plate that can be contacted by voltage applied to the highly conducting source and drain regions shown crosshatched below the oxide These are the regions that are contacted from the S and D metal connections at the top by the metallization that continues through the openings made in the oxide The region on the left is labeled arbitrarily S (D) and the region on the right labeled D(S) Each region can serve as the source and the other the drain depending on the polarity of the voltage applied between these terminals and thus the direction of current flow through the channel They have a depth ld that is relatively shallow

Voltage between the plates of a capacitor controls the equal and opposite charge on the plates For example positive voltage and charge on the upper plate (the gate) will induce negative charge in the bottom plate This charge can be in the form of mobile electrons or as fixed ionized acceptors without the holes they created present The crosshatched regions with depth ld can serve as the source of mobile electrons that can flow in the channel from the source to the drain when positive voltage is applied to the drain with respect to the source Current for this n-channel device with electrons in the channel will flow from the drain to the source since current flows opposite to the flow of electrons

The sketches in Fig44 explain in more detail the nature of the charge induced in the semiconductor for both positive and negative voltage applied to the gate When positive voltage is applied negative charge is induced in the channel as in fig44a For small values of voltage this induced charge is in the form of immobile negatively-charged ionized atoms the holes originally with the ionized atoms are driven away by an electric field so that region can provide the negative charge to balance the positive charge on the gate However when the voltage between the gate and the source exceeds the threshold voltage mobile electrons are induced in the channel as shown in fig44b The channel consists of a so-called electron inversion layer because the p-type semiconductor has been inverted from a region containing mainly holes to one containing mainly electrons The inversion layer is only several atoms thick however there is enough mobile charge in the channel to provide the current that must flow between the drain and source regions when voltage is applied between the drain and source As the gate voltage increases further the mobile electron charge in the channel increases as shown in fig44c and the current therefore also increases Basically the MOST structure allows an input voltage applied at the gate terminal to cause an output current flowing between the source and the drain terminals and also through the external circuitry connected to the device This is the basic function of all transistors provide a change in output current which can pass through a load and produce an output voltage change with a change in input voltage The change in output current with a change in input voltage is the key performance parameter of a transistor It is called the transconductance Refer again to figs43b for the location of these regions and typical dimensions)

If VGS is less than the threshold value VT and is also negative positively charged mobile holes would be induced in the channel as shown in fig43d The source and drain n-type regions have a large number of electrons and these regions are now separated by positive mobile holes Thus there are essentially two ldquoback to backrdquo diodes One between the source and the channel and the other between the channel and the drain For any polarity of voltage between the source and drain one of these diodes would be reversed biased preventing current flow between the drain and the source Current flow would occur if one of the diodes had Zener breakdown but the MOSFET is designed so that this does not occur under normal operating conditions Only when the carriers in the channel are of the same type as the free carriers in the source and drain diffusion wells is conduction between the source and drain contacts possible

Summarizing the n-type transistor operation is based on the motion of the induced channel electrons (or holes) that flow from the source to the drain The electrons are actually provided by the electron-rich source (S) region Electrons flow to the drain (D) terminal and out to the external circuit because of a voltage applied externally to the MOST (To visualize these concepts think of the kitchen faucet being the source of water particles [either holes or electrons] and the drain as the collector of the carriers) The motion of the electrons is in the opposite direction to the current for the n-type MOST but in the same direction as the holes for the p-type MOST The electron concentration (and therefore the current flowing in the channel region from the D to the S) can be

changed by a voltage applied between the third terminal the gate and the source terminal The voltage between the gate and the source VGS has to be more positive than the threshold voltage to induce electrons in the channel If it is not no current between the S and the D no matter what the potential difference VDS is between the D and S terminals This is because without electrons in the region the conductivity is zero

Return to fig41 and study the E-MOST device with a threshold voltage VT of 10 [v]) Because the threshold voltage VT has a positive value this N-MOST is called an enhancement mode MOST or E-MOST If an n channel MOST has a negative threshold voltage it is called a depletion-mode MOSFET as the third MOST device in fig41 For the transfer curve in column three VDS is greater than VGS ndash VT the transfer curves are always given for the MOST in its saturation region Note that there is a current even when VGS is zero Current can flow even when VGS is zero because VGS is more positive than VT Note again that for the transfer curve for device 1 the drain current is zero when VGS is zero The gate to source voltage VGS must exceed VT = 1 [v] for the transistor to conduct

Let us compare the structures for the four types of transistors as presented in column 2 Notice that the two n-type transistors are both made with p-type substrates and have N source and drain diffusion wells The plus sign means that the region has a high concentration of electrons eg about one out of 100 Silicon atoms is replaced by a column 5 donor atom (eg Arsenic Phosphorus or Antimony) and provides a free electronThe difference between the devices is that the D-MOST device has an inversion region with no voltages applied To understand the reason for this requires a background in device physics However a simple explanation is that MOSTs can be made with fixed positive charge appears at the interface between the oxide and the channel The positive charge induces conducting electrons in the channel even without voltages appliedThe device symbols with the broken line for the E-MOST and the solid line for the D-MOST device emphasize that the E-MOST source and drain are disconnected when VGS is zero Note again that the D and S terminals are interchangeable depending on the direction of current flowing through the transistor Also note again that the distance between the diffusion wells is L and that the width of the device [into the paper] is W WL is the parameter that engineers use when designing FET circuits

P-channel devices are identical to n-channel MOSTs except that their substrate is made of N-type material and holes flow between source and drain when VGS becomes more negative than VT The mobile carriers that conduct current ID are holes rather than electrons Note that the source and drain wells are made of heavily doped p-type material which is symbolized by the + sign on the P symbol in the source and drain regions Compare the transfer characteristics for the two p-channel transistors with the two n-channel transistors Note that the only difference is that the curves sweep up to the left for the p-channel devices as VGS becomes more negative and sweep up to the right for the n-channel transistors Note that for P-MOSTs holes and current flows from source to drain This causes a voltage drop such that the drain voltage will be negative with respect to the source Thus VSD will be positive In contrast current flows from drain to source in the n-channel devices which results in VDS being positive Since VDS is positive it is used in the plots of the drain characteristic plots

for N-MOSTs For P-MOSTs we use VSD (not VDS) because it is positive and it is convenient to have essentially the same drain characteristics for both the p and n channel devices

Now compare the transfer characteristics for the depletion mode and enhancement mode p-channel transistors The E-MOST does not conduct when VGS is more positive than the threshold voltage VT = 1 On the other hand the D-MOST conducts since VT is positive for D-MOSTs For the p-channel D-MOST a thin P region is made where the conducting channel is The p-channel D-MOST is not used in commercially popular circuits

The equations for finding the drain current in the devices will now be introduced by considering the n-channel E-MOST with VT equal to +1[v] and K = 2 mAV2 Notice the constant current behavior in the saturation (sat) region of the drain characteristic in column 4 ID does not vary as VDS increases Also note that the value of VDS at which the current curves become flat is given by VGS VT This important parameter is defined as VDS [VGS VT equiv VDS] It is the particular value of VDS separating the linear region (or ohmic [resistor-like] region) on the drain characteristic from the saturation (or constant current region) It is of course different for curves with different values of VGS The equation below describes the dependence of ID on both VDS and VGS in the linear region Note that if the value for VDS is much less than the key parameter VGS VT the transistor behaves as a resistor whose resistance is controlled by the gate voltage and whose current is directly proportional to VDS Increasing the gate voltage decreases the value of this resistor The MOST can act as a voltage-controlled resistor

1) I D = K [(VGS VT)VDS (VDS )2 2] ID = K [VGS minus VT]VDS for relatively small values of VDS relative to VDS equiv VGS ndash VT

Note that the value of K and the resistor can be controlled by the WL ratio The term tox is not really a variable for circuit designers because it has already been maximized by the device processing engineers and researchers The tox values have increased by a factor of 10 in the last 10 years to 250 and 100 AV2 for n-type and p-type MOSTs respectively in 2005

The equation for the saturation region (the constant current region) is given by

2) ID = K2 [VGS - VT]2 = K2 [VDS]2 VGS - VT equiv VDS

Equation 2 can be obtained by setting VDS equal to VGS - VT in equation one The point on the MOST characteristic common to both regions at the intersection of the two curves can be found from either equation 1 or 2

Exercise 41 Sketch the transfer and drain characteristics of the transistors in fig41 for one or two values of VGS Do not refer to the figure This is a highly recommended exercise as you will be given K and VT values on exams and asked to sketch the drain and transfer characteristics Hint First find VDS and then the saturation current Also find a current value for one convenient value of VDS in the linear region [A convenient value to use for VDS is one half of VDS The current at VDS2 will be frac34 of the saturation value]

Exercise 42 Find the values of VDS and VGS for the transistors in fig45and identify the region of operation for the transistor in each of the circuits First read the problem at the top and then study the suggested step-by-step approach at the bottom of the figure A word of caution Most errors in solving these types of problems occur because of errors in the use or understanding of potential difference and Ohms Law As with the diode problems put voltage drop signs on the circuit BEFORE proceeding

Exercise 43 Make a sketch to explain how when an electric field is applied hole motion (due to the motion of electrons ldquojumpingrdquo between the broken valence bonds of acceptor atoms) acts as a positive charge Review the top complete paragraph of the third page of this lesson

B) Analysis of Basic MOSFET Circuits

A simple circuit with a MOSFET transistor attached to a resistor load is shown in fig46a The device parameters VTN and Kn are specified and written next to the device Since WL is given to be 11 the K value is 250 AV2 The circuit will be analyzed by finding the Q-point of the device ie the dependent variables ID VDS and VGS The four steps to solve the circuit are listed under fig46 a so that you can look at the circuit while you read the steps The additional comments below on the four steps should be read while you have both this text and the figure in front of you1) Since the gate and source voltages are given the difference in potential between the gate and the source VGS is easily found to be 3 [v] 2) It is good practice to assume that the transistor is in the saturation region because the current equation involves only two dependent variables and not VDS Therefore in step 2 we substitute VGS = 3[v] into the saturation equation and calculate ID = 05 mA 3) Add the correct plusminus sign across the resistor along with the calculated 5 [v] voltage drop4) The last value for the Q point VDS is found by subtracting the resistor drop from 10 [v] since the total voltage around the loop must be 10 [v] and the source is at ground5) The final step is to check the assumption that the MOST is in the saturation region We must use the fact that the drain to source voltage for the border between the saturation region and linear regions VGS VT is 3 1 or 2[v] This value is less than the calculated value of 5 [v] for VDS Thus the transistor is in the saturation region as was assumed

The same circuit is analyzed by graphical analysis using steps 1 2 and 3 in fig46b First the characteristic of the N-channel MOST with VTN = 1[v K = 250 Av2 and VGS = 3 [v] is plotted in fig46b1 [The calculated values for the saturation current and boundary region voltage VDS are used to make the plot] Second the circuit characteristic is added to the plot as in fig46b2 The circuit characteristic depends only on the total voltage applied and the value of the resistor and is not related at all to the device characteristic The voltage across the device must equal the total voltage applied minus the voltage across the resistor Therefore the resistor iv characteristic is plotted ldquobackwardsrdquo from the total voltage of 10 [v] In step 3 the Q-point is found at the intersection of the device and resistor characteristics

The circuit in fig47 uses the same transistor as in fig46a but has a resistor connected from the MOST source terminal to the minus 5 [v] supply The resistor connected to the source terminal makes the analysis more difficult than for the circuit of fig46a Three equations must be written to find the 3 unknowns the dependent variables ID VDS and VGS Equation one written below is the MOSFET equation for the saturation region The two other equations are

those for the two loops the gate-source loop and the drain-source loop Note that VG is 05[v] by voltage division of the 5 [v] applied to the gate biasing circuit Also note that the total voltage for the gate loop from the gate to ndash 5 is 55 [v] and that voltage must equal VGS plus the drop across the resistor The total voltage dropped across the loop from the 5 [v] drain supply to the minus 5 volt supply is 10 [v] It is dropped across the two resistors (50K + 50K = 100K) and across the transistor (drain to source voltage drop) The equation for this loop is 3

1) ID = K2 [VGS ndash VT]2 2) 55 = VGS + I D50K 3) 10 = ID (100K) + VDS

The three equations can be solved for the three parameters that determine the Q point VGS VDS and ID Equations 1 and 2 can be combined and the resulted quadratic equation solved An alternative method is by guessing the value for VGS and finding ID using equation 2 Then one has to check if this pair of VGS and ID values satisfies equation one If they do not a revised guess for VGS must be made similarly as done for the trial and error procedure presented in lesson 2 To save time let us make a wild guess of 3 [v] for VGS This results in ID

being 50 A according to equation 2 Letting VGS equal 3 [v] in equation one yields 50 A so the guess of VGS = 3[v] was a very lucky one (smile) From equation 3 VDS is found to be 5[v] The graphical approach shown in fig47b gives the same result and also clearly shows that the MOST is in the saturation region as assumed Of course the device curve had to be sketched by guessing that VGS was 3 [v] [It is easier to make a lucky guess if you design the problem as the author did Note that the procedure that the author followed would be the one that would be used if the desired Q point values were known and the biasing circuit to obtain the Q point was to be designed]

The circuit in fig47 could be modified so that voltage from an ac analog signal generator could be either amplified or applied to loads for the purpose of making the resistance of the generator appear to be much less Such an amplifier is shown in fig47d A capacitor connects the output of the generator to the gate terminal of MOSFET circuit The capacitor serves the purpose of coupling the ac voltage to the gate while blocking any DC current to the signal generator circuit due to DC voltage on the gate The generator circuit would be in parallel with the 9 M resistor and would cause a change in the DC gate voltage if the capacitor was not used The capacitor couples the ac voltage to the gate input by behaving as an effective short circuit for the ac current as long as it is large enough to have low impedance for the frequency of the ac input signal Such analog circuits are studied EE 372 [This type of circuit could amplify a 1 mV signal voltage for example to a level of volts As mentioned the capacitor is an open circuit for DC current and thus allows the ac signal to reach the gate but isolates the DC bias circuitry from the signal source Because of the particular choice of 5 K resistors for both the drain and source circuits the voltage gain of the circuit (time varying output voltage divided by the time varying input voltage provided by the signal generator) is actually less than one However this ldquoamplifierrdquo has other useful properties as taught in electronics 2]

Example Problems with Solutions Given Study the following problems to develop your analysis skills for MOSFET circuits PROBLEM ONE Select the value for VDD for the circuit in fig48 that sets the Q-point 4 [v] greater than the value of VDS at the intersection of the linear and saturation regions In other

words the value of VDS should be four volts greater than the value of VDS that defines the boundary of the linear and saturation regions

Solution for Problem One a) By voltage division of the 10 [v] with the 40K and 60K VG = 4 [v] b) VGS is found to be 4 [v] because the source is grounded c) The MOST saturation equation is used to find ID = 4 mA Confirm that this is so (Note that the wording of the problem tells you that the FET should be in the saturation region) The value of VDS that separates the saturation and linear regions is found by subtracting the threshold voltage from VGS (Confirm that it is 2 [v]) d) The actual value for VDS of 6 [v] is obtained by adding four volts to the value of VDS = 2[v] found in step d so that the Q-point is 4 [v] into the saturation region as requirede) Adding the drop across the resistor for ID = 4 [mA] 4 [v] to VDS = 6[v] gives the value of VDD that should be selected ie10 [v] This value of VDD enables the Q-point of the FET to be at VDS = 6v] and ID = 4 [mA] as required in this design problem

PROBLEM TWO Find the Q-point for the circuit in fig49 Note that the circuit and device are the same as for problem 1 except that the 1K resistor has been increased to 10 K Solution for Problem Two If we assume that the transistor is saturated the current would be 4 [mA] This current would cause a drop across the 10 K of 40 [v] This is impossible since only 10 [v] is applied to the drainsource loop Therefore the assumption that the MOST is in the saturation region is incorrect The equation for the linear region must be used to find ID

Since there are 2 unknowns in the equation for the linear region a second equation must be used This equation is Ohms Law for the resistor It relates the current in the resistor to the unknown voltage VDS and VDD = 10 [v] as written below equation 1 in the figure The two equations can be equated to obtain equation 3 since the current in the resistor and MOST are the same VGS = 4 [v] obtained as in problem 1 was substituted into equation 1

1) I D = 2 10 -3 [(VGS VT)VDS (VDS)2 2 ] 2) IR = (10 VDS ) 10K = ID

Equation 1 and 2 can be combined and then reduced to the quadratic equation

3) (VDS)2 41VDS +1 = 0

Solving the equation using the quadratic formula leads to finding VDS is either 02605 or 384 [v] The larger value is rejected because it is greater than 2 [v] and therefore the MOST would be in the saturation region which is impossible It was already determined that the MOST must be in the linear region The drain current can be found easily from equation 2 to be 0974 [mA] using the value of 026 for VDS Please check these results by inserting the values for VDS and VGS into the linear region equation for current

PROBLEM THREE Find the Q-point for the circuit in Fig410 This problem is similar to the previous one but there is less required math

Step by Step Solution for Problem Three 1) First we find VGS is 4 [v] by voltage division 2) Assuming that the MOST is in the saturation region we can easily calculate the current to be 4 [mA] However the drop across the 43K resistor would be greater than 5 [v] and that is impossible since only 5 [v] is applied to the drain loop 3) Therefore the linear equation is written for the MOST 4) The device current is set equal to the current in the resistor as done in the previous problem and as shown in fig410 for convenience Practice doing this The resultant equation for VDS is

1) (VDS)2 194VDS + 154 = 0

Let us have some fun by solving this problem by trial and error starting with a guess of 1 [v] What a guess It solves the equation and 1 [v] is a value less than 2 [v] so that the device is in the linear region as it must be since linear device equation was used The current is easily found to be 3 [mA] by applying Ohms law to the resistor

PROBLEM FOUR Find the value of the resistor in fig411 so that VDS = 1 [v] and ID = 3 [mA] This problem should look familiar

Solution for Problem Four We note that the required value of VDS compared with 2 [v] tells us that the MOST is in the linear region Since we are given all the Q-point values a device equation is not needed The voltage across the resistor is 5 1 = 4 [v] and the current is 3 [mA] Therefore by Ohmrsquos Law the resistor value is 43 K

PROBLEM FIVE Given the circuit in fig412 Find the Q-point for the transistor Note that the MOST is a P-type transistor (by the small circle on the gate of the transistor) Also note that the magnitude of the values for the voltages and currents in the circuit and the power supply voltages and threshold voltage are the same as for problem 3 the circuit in fig410 but the signs are different

Solution to Problem Five As a first step to finding the Q-point for the circuit in fig412 we note that the current flows from ground to the minus five volt supply Therefore since the MOST is p-type the source terminal is again at ground potential The direction of current flow from ground to the minus five volt supply and the voltage drops VSD and VGS are shown to the right of the figure It is good practice to show the current flow direction and add the drops to the circuit in fig412 [You could also sketch the circuit on a separate sheet of paper As a first step to solving the problem add current flow and voltage drops with polarities] As a second step the value of the voltage VGS can be easily found by voltage division on the gate circuit (VG = VGS = 4 [v]) Then the current can be calculated assuming that the device is saturated This current value (4 mA) times the 43K resistor will produce a voltage drop greater than the applied voltage Thus we know that the equation for the linear region should be used See equation 1 under the figure As a fourth step the Ohmrsquos Law equation for the resistor is written as equation 2 also in the figure Equations 1 and 2 can be solved simultaneously by the quadratic equation or by trial and error to find VSD = 1[v] and ID = 3 [mA] The next section presents a general approach to solving the ldquofind the Q-pointrdquo problems Section C does not have to be studied for the Electronics One course if you are

comfortable doing the previous examples It is written so that you have an organized approach at hand if you need to solve such problems in other courses or work

C) General Guideline for Analysis to Find the Dependent Variables ID VDS and VGS in a MOSFET Circuit

a) Find the gate voltage VG by voltage division Since the MOST has no DC gate current this is a very simple task

b) Write an equation for the gate-source loop that includes the key parameter VGS which controls the drain current [Determine first which terminal is the source by observing the direction of the drain current and using the fact that the carriers electrons for N-MOST and holes for P-MOST leave from the source and travel to the drain] If the source is connected to ground VGS is given by equation 4 If the source is connected to a supply voltage VSS through a resistor RS equation 5 must be used

4) VGS = VG - VS = VG

5) VGS = VG minus IDRS minus VSS

c) Write one of the two MOST device equations Unless it is obvious that the device is in the linear region choose the saturation region equation since it has only two unknown parameters ID and VGS

d) Write an equation for the drain source loop equating the total voltage applied to the loop equal to VDS plus the IDR drops across the resistors in the source leg and in the drain leg

e) Use the three equations obtained in steps b c and d to solve for ID and VGS and then VDS This step will involve the use of either the quadratic equation or the trial and error method f) Compare the values for VDS with VGS - VT to see if the assumption of using the saturation equation for the FET was correct If it is not use the linear equation for the device and redo the steps starting with c to find the actual values for ID VGS and VDS

D) REVIEW OF THE LOAD LINE CONCEPT

It is important to visualize the analysis of these problems from a load line point of view Review again the graphical solutions for the circuits in figs46 and 47 Note that when there is a resistor connected between the source and ground as in fig47 the load line is determined by the sum of RS and the resistor connected to the drain RD [This resistor has often the symbol RL because its function is to act as a load across which the small signal analog output voltage due to the current develops for use of a load device for example a sixteen ohm audio speaker] The load line for the MOST depends only on the total voltage applied to the drain source loop and the total resistance in the loop Equation 6 can be used to plot the load line by asking ldquoifrdquo questions as were done with the diode circuits for example a) If ID were

zero what would VDS be b) If VDS were zero what would ID be c) If VDS were two what would ID be These values of VDS and ID will lie on a straight line the load line

6) VDS = (VDD + VSS) - ID(RD + RS)

E) VOLTAGE TRANSFER CHARACTERISTICS OF LOGIC CIRCUITS and NOISE MARGINS

The transfer characteristic of a logic gate is the plot of its output voltage versus its input voltage An example basic logic gate is shown in fig413a The N-channel MOST acts as a switch while the resistor acts as a load dropping voltage so that the output is not always 5[v] When the input voltage is 5 [v] (as the boxed value at the gate) the output voltage is 025 [v] This is because the switch conducts current when the input voltage is greater than VT The current causes a 475 [v] drop across the load resistor The value of the voltage drop is set by the resistor and current values so that the output is the desired ldquo0rdquo logic value of 025 [v] When the input voltage is less than the threshold voltage eg025 [v] the switch is open The output rises to the logic ldquo1rdquo value of 5 [v] because no current flows and there is no voltage drop across the load resistor

The transfer characteristic or transfer curve for the gate is shown in fig413bThe transfer curve gives a value for the gate output v0 for every possible input voltage vI For this gate the normal inputs are 5 [v] for a ldquo1rdquo and 025 [v] for a ldquo0rdquo Observe that the corresponding outputs as plotted on the transfer curve are 025 and 5 [v] These pairs of values locate the normal operating points of the gate on the transfer curve

The input voltage to the logic gate can not change instantaneously from 5 to 025 [v] during the transition from a ldquo1rdquo to a ldquo0rdquo During this input transition time the output voltage switches from 025 to 5 [v] The time for the input and output to change is referred to as the switching time Similarly as the input changes from 025 to 5 [v] the output decreases from 5 to 025 [v] Fig414a shows typical input and output waveform changes when clock pulses are applied The rise and fall times of the input and output usually are different The signals are ldquocleanrdquo because the circuit is assumed to be in a noiseless environment Fig414b shows that in a normal environment there is noise ldquopickuprdquo on the waveforms caused by fast rise and fall times of the input and output voltage The waveforms sketched in fig414b illustrate that actual voltage signals are not ldquocleanrdquo but modified by the noise pickup Even during the time when the input is suppose to be at a steady value eg 5 [v] it may fluctuate due to ldquopickuprdquo from nearby gates

What causes the ldquopickuprdquo or noise that results in waveforms not being clean The major cause of noise is that the wires or conductors in the circuit act as tiny antennae receiving electromagnetic radiation from nearby wires due to rapid changes in the currents and voltages in the surrounding conducting connections and gates including power supply lines See fig415 and study the comments presented under the sketch for your convenience The comments point out that the wires connecting the devices and circuits in a logic system can effectively be modeled as capacitors resistors and inductors The inductors can represent coupling between two different wires or mutual inductance or the voltage drop in a single wire due to the rate of change of current through the wire self-inductance The

very rapid rise and fall times of the voltage and current signals (big dvdt and didt) in modern high-speed computers enhance these undesired effects

One purpose of the transfer curve is to reveal how much protection a logic circuit has against having its output being switched by noise from logic 1 to 0 or from 0 to 1 without the input changing The noise margin in volts indicates the protection against unwanted noise pickup Notice that when the input waveform in fig414b dropped below the VIH level due to a large noise pickup during the time that the input was suppose to be high the output changed from a ldquo0rdquo to a ldquo1rdquo Thus a computer error was generated When the noise diminished and the input went above the VIH level the output returned to its correct value of ldquo0rdquo Similarly near the end of the waveform when the input in the low state rose above the VIL for a short time the output dropped to a low level creating a second error Thus VIL is the maximum low level that the input can increase to without causing the output to switch erroneously from a ldquo1rdquo signal to a ldquo0rdquo signal Similarly VIH is the minimum high level that the input can fall to without causing the output to switch erroneously from a ldquo0rdquo signal to a ldquo1rdquo signal These levels in fig414b can be found on transfer curves such as the one in fig418 However first we will discuss some basic concepts using figs416and 417

Fig416 shows the voltage transfer characteristic for an inverter logic circuit There are two normal operating points An operating point is a pair of input and output values that are associated with the normal ldquo1rdquo and ldquo0rdquo levels The curve is ideal because the output does not change with input except for the transition region where the output changes rapidly from a high level to a low level with increasing input voltage Ideally the digital gain defined as the change in output divided by change in input is infinite as in the case of the vertical drop versus the finite slope of a realistic transition region Looking along the vertical scale the normal high-level output voltage that must serve as a high level input can be seen to be VOH = 5[v] and the normal low level output voltage that must serve as an input is VOL = 1 [v] Note that when the input voltage is at 5 [v] (the high level signal VOH) the output is at the low signal level VOL= 1 Also when the input is at a normal now level VOL the output is VOH You should observe this by following the arrowpath beginning at the input VOH (the a arrow) Then follow the b arrowpath beginning at the input VOL to see the output is the high level VOH

The reason that the normal outputs VOH and VOL must be used as inputs is that the inverters must drive identical inverters as shown by a typical logic gate array in fig417 The circled normal output voltages correspond to signals levels observed during one clock period The squared voltages correspond to a different clock period The load inverters in turn drive identical inverter gates or perhaps NAND OR etc gates which also must operate with the same voltage levels for the 0 and 1 signals For the array of gates to function without error there must be this ldquoinputoutput compatibilityrdquo The high-level output signal level VOH must serve as the high-level input signal VOH the low-level output signal level VOL must serve as the low-level input level signal VOL

A more realistic transfer curve is shown in fig418a Note that between the two signal inputs where the slope of the curve is minus one the output changes more rapidly than the input That is the slope of the curve is greater than one For a particular input change eg 01volt the output will change by more than 01volt This region is said to have digital gain ie the output

changes more than the input Increasing the digital gain is necessary to reduce the time for the input and output to switch between high and low voltage levels The more vertical the transition region of the logic gate transfer curve the higher the switching speed of the gate

The symbols for the particular input signal values for the points on the curve where the slope is minus one are VIH and VIL The noise margin of the gate depends on having the lowest possible value for VIH and the highest possible value for VIL See fig418b which shows an error in the output of inverter 2 created by the drop below the VIH level in the output voltage in inverter 1 that drives inverter 2 Once the input falls below the value at which the slope of the transfer curve is minus one it enters a region of digital gain where the output changes are large and serve as large input change to gate 2 and produce wrong output for gate two as shown in the waveforms in fig418b If the reduction of the input signal were not enough to bring the input to VIH errors would not occur in the following gates Thus the voltage difference between VOH and VIH represents a safety factor or high level input noise margin NMH Similarly the voltage difference between VIL and the input VOL NML represents protection against the input signal increasing from the normal signal input level VOL to beyond the value VIL where there is gain This voltage difference represents the low-level input noise margin

Ideally the transition region where there is digital gain is located in the center of the transfer characteristics and has zero width so that the noise margins have the maximum possible values The noise margins also would be the same This is preferred since the quality of the noise protection is only as good as the smallest noise margin

As stated immunity against noise is only as good as the smallest noise margin A large signal swing VOH VOL tends to produce larger rate of change of voltage with time and therefore more electromagnetic pickup by the gates in a logic array and therefore more errors Therefore a noise immunity figure of merit equal to the noise margin divided by the signal swing has been used as an industrial standard to compare different logic gate circuit families eg ECL TTL CMOS and DMOS

F) DEFINITIONS OF PROPAGATION AND PAIR DELAYS FAN-IN AND FAN-OUT AND THE POWER-DELAY PRODUCT LOGIC CIRCUIT REQUIREMENTS

Example switching waveforms for an inverter gate are shown in fig419 The logic decision speed of gates is compared using values for the propagation and pair delays The propagation delay on the high to low output transition PHL is shown in fig419 as the delay between the 50 points of the rising input waveform versus the falling output waveform Similarly the propagation delay on the low to high output transition PLH is shown as the delay between the 50 points of the falling input versus the rising output The two times will not necessarily be the same The average propagation delay P which is the sum of the two propagation delay times divided by two is often used when comparing logic circuits

The propagation times will depend on the number of gates driven by the output or the fan-out [A major reason for this is that the capacitor loading changes with the number of MOSFET gates] One type of logic gate might appear to be very fast for low fan-out but will slow up much more than another type of gate when required to drive many other identical gates The normal

speed performance parameter is pair delay the time for the input to reach the same 50 value on the rising input waveform after passing through two identical gates

Logic gates can be operated with shorter propagation delays by increasing the supply voltages The cost is that the standby power and switching power dissipation will increase Therefore to compare fairly circuit families and designs a figure of merit (FOM) equal to the product of the average propagation delay time (eg in nanosec) and the average power supplied to a gate (eg microwatt) is used The unit for the FOM of logic gates manufactured in 2005 is femto-joules You will see that it is possible to decrease switching speed if the power consumed by the gate is increased Therefore for a given logic gate technology the FOM tends to be constant Ask your instructor to provide you with the latest energy versus time (in years) for the various logic technologies Sources for information are the January issues of the IEEE Spectrum magazine

The number of identical gates that a logic gate can drive effectively is defined as the fan-out capability Fan-out capability is sometimes just called fan-out [However this could be confused with the total number of gates attached to a gate which might be less than what it is capable of] In general the fan-out capability will be different for high and low outputs Similarly the fan-in capability is the number of inputs that can drive a single gate at a specified clock rate without errors being produced Fan-out and fan-in depend on clock rate

G) BRIEF SUMMARY OF LESSON FOUR The major learning objective of section A is to be able to sketch the transfer and drain curves of a MOSFET if the K and VT values are specified Section A also focuses on explaining why the MOSFET structure results in these characteristics However it was pointed out that the design of circuits can be done with knowledge of the characteristics in fig41 only On the other hand knowing the device physics and material science behind the characteristics is valuable knowledge for following developments in the many high technology areas based on semiconductor technology Section A provides this basic knowledge Additional material science information is given in Appendix 42

The analysis of the basic circuits in figs46 through 413 was used to exercise and develop your knowledge of the FET device characteristics and equations The examples also exercise your basic knowledge of circuit analysis principles as voltage division potential difference multi-loop equation analysis and load line However the only new concept in these exercises was the brief introduction to the MOSFET circuit as an amplifier of analog signals The subject of MOSFET and Op-amp analog circuits is covered extensively in EE372 and EE 373

Another key learning objective of lesson 4 is to know the important applications of the logic gate transfer curve The concept of noise causing unwanted changes in output voltages summarized in fig418 The physical cause of noise and how the transfer curve provides some protection against noise and the propagation of errors (as indicated by the noise margins) are summarized in figs415-417 Other figures are presented only to help you understand the information in those four figures The bold statements in Section F and fig419 summarize the important logic gate performance parameters of average propagation delay

pair delay power-delay product (which has the units of energy) and their dependence on fan-in and fan-outThe key information in this lesson will be used in almost all the following lessons so you will be ldquoreviewing by usingrdquo throughout the rest of the course

Appendix 41 Basic Concepts for the Junction Field Effect Transistor (JFET)

The structure and physical operation of the junction field effect transistor is entirely different than for a MOST and will not be discussed in detail However the IV transfer and drain characteristics are nearly the same The JFET parameters that are given by manufacturers of the transistor are IDSS the saturation current for VGS is zero and the pinchoff voltage VP which corresponds to the threshold voltage for the MOSFET For an n-channel JFET the pinchoff voltage is the value of VGS that reduces the current to zero (or pinches off the channel) For the saturation region equation 1 is used The equation is equivalent to the MOSFET saturation equation if K is set equal to 2IDSS [VP

]2 The linear equation for the MOSFET can be used for the JFET also The transfer curve for the JFET is identical to the DMOST except that it cannot be used in the region where VGS is positive [This is because current then flows from the gate into the channel region and the gate is no longer isolated from the source and drain as it should be for a FET] The transfer curve is shown in the margin The equation for the linear characteristic is equation 2

1) ID = IDSS [1 ndash VGS VP ]2 from ID = K 2 [VGS minusVP ]2 where K = 2IDSS [VP]2 and VDS geVDS

2) ID = K [(VGS - VT ) minusVDS 2] VDS ID = (2IDSS [VP]2) [VGS - VP]VDS for ldquosmallrdquo values of VDS Also ID = (2IDSS [VP]2) [(VGS - VT ) - VDS 2] VDS for values of VDS that are large enough to make the subtractive term in the brackets significant

Appendix 4-2 Review of Conduction Properties of Silicon and Other Semiconductors

This appendix presents in more detail the mobile charge generation and conduction processes introduced briefly in the first paragraph in section AThere are three types of silicon material intrinsic n-type and p-type Intrinsic or pure silicon with no deliberately added impurities is relatively non-conductive It has a large resistivity of about 1000 ohm-cm at room temperature (2930K) Equation one describes the dependence of the resistance (R) of a sample of semiconductor material of width W thickness t and length L with voltage (V) applied across L The material parameter that controls R is the resistivity The resistance is also dependent on W L and t that make up the geometry factor Fig41 described the geometry factors (L W and t) and showed the current and electric field directions in response to a voltage V across the material

1) R = [ohm-cm]L[cm] W [cm] t [cm]

Bond and band energy models are useful for visualizing the complex phenomena that occur at the atomic level in conductors insulators and semiconductors These simple

models enable engineers to effectively design and even invent electronic devices without having to think in detail about the complex phenomena at the atomic level FigA-1 shows the simple bond model (the chemistrsquos view) which describes some of the electronic properties of intrinsic material Surrounding each host silicon atom are 4 valence electrons These electrons are shared between neighboring atoms and are the co-valence bonding which holds the array of atoms called a lattice together Notice that each atom such as the central one in the sketch shares eight electrons with the surrounding atoms

The atoms can be thought of a connected by springs that represent the various forces that the atoms exert on each other Thus thermal energy of the atom array can be expected to trigger coordinated motion or vibration wavelike motion The ldquoparticlesrdquo that carry the energy of these vibrations are called phonons just as photons are the particles carrying the energy of electromagnetic radiation or light [For a very simple idea of the wave motion of the phonons visualize the coordinated standing up and sitting of fans at sports events called the WAVE] Because of the energy of the moving atoms about 1010 elcm3 of the electrons in the co-valence bonding will be ldquoshookrdquo free from their ldquomotherrdquo atoms at about 68 degrees Fahrenheit They generate not only free electrons ni but also an equal number of holes pi in the covalent bonding Only a small percentage of the bonds are broken at room temperature (ni = pi =1010 elcm3) This number is much less than the number of host atoms 5bull1022 atomscm3

A hole acts as a positive charge and moves in the opposite direction of an electron when under the influence of an electric field FigA-1a shows a broken bond first created at the lower left (step a) by thermal energy The broken bond or hole can move upwards by eg an electron at the upper left randomly moving down from its valence bond position to fill the broken bond at the bottom (step b) Thus the broken bond or hole has moved up as indicated by c Again this creation of the electron and hole pair occurs at random due to thermal energy breaking the valence bonding

FigA-1b shows the energy band model (the physicist view) The potential energy for an electron in electron-volt units is plotted in the vertical direction When an electron receives energy eg from heat (the atomic vibrations) or from sunlight it moves up from the valence band representing its location in the bonding structure to the conduction band representing its ability to move through the material free of the bonding forces [Note that an eV unit of energy is 16 times 10 ndash19 joules These small energy units are convenient for measuring the potential and kinetic energies of electrons with their very small mass and small energies for separating them from their ldquomotherrdquo atoms] The model shows a band of electron energy levels that hold electrons involved in the co-valence bonding This lower group of energies is named the valence band as shown in the figure Above the valence band there is a range of energy in which there are no energy levels and therefore no electrons can be in this energy range called the forbidden gap

The conduction band contains the generated electrons that are free to move in random directions The free electrons in the bond model occupy the lowest levels in the conduction band as shown in the figA-1b [The horizontal axis has no significance in figA-1b however in other energy-band figures it is used to show how the conduction band energy and potential

energy barriers for electron flow vary with distance along a direction through the device structure] The band model shows clearly the amount of thermal energy required to break the bond generating the free electron and hole This energy is 111 eV for Silicon and 143 eV for Gallium Arsenide The difference in energy required to break bonds is significant and the density of ni in GaAs is only 2bull106 pairscm3 because it has a wider bandgap than Silicon

If an electric field is applied the free electrons although moving in all directions will have a net component that moves opposite the direction of the electric field (ie provide electrical current) When no voltage is applied to the silicon material the holes and free electrons are moving around in all directions so that there is no net charge motion and therefore no current flow However when voltage is applied the electrons jumping around in all directions tend to move slightly more in the direction opposite the direction of the electric field due to the voltage and thus the holes move in the direction of the electric field and thus act as positive charge Again hole motion is actually due to electrons that jump into the broken bond from neighboring bonds creating a hole in their former location as shown in figA-1a It appears that the hole moves in the opposite direction to the jumping electrons and therefore a hole acts as a positive charge when an electric field is applied The field enhances the motion of electrons in a direction opposite the field direction Thus it enhances the motion of electrons jumping in the band structure to fill vacancies and thus enhances current due to holes When no voltage is applied to the silicon material the holes and free electrons are moving around in all directions so that there is no net charge motion and therefore no current flow

N-type or electron-rich material is made by adding column 5 impurity atoms (such as phosphorus antimony and arsenic) to intrinsic silicon to dope the material FigA-2a shows that the extra electron is not involved in the bonding process and is thus relatively weakly attached to the impurity atom Almost all the impurity atoms lose their fifth electron at room temperature and thus are ionized Thus doping by the impurity atoms increases the free electron concentration due to the concentration level of the doping impurities called donor atoms without generating any holes The number of electrons generated can be between 1015 to 1020 elcm3 compared with the number of host silicon atoms about 5bull1022

atomscm3 The band model in figA-2b shows the electrons thermally excited into the conduction band by the addition of the donor atoms along with the relatively small number of thermally generated electrons across the relatively large energy of the gap To show the small amount of ionization energy required energy levels representing the donor atoms are shown as shallow energy states located eg 01 eV below the conduction band edge

The addition of a large number of electrons greatly reduces the hole concentration because the extra free electrons from the donor atoms fill in most of the broken bonds From the band model point of view the negatively charged electrons in the conduction band attracted to the positively charged holes lose the extra energy that they have in the conduction band by recombining with the holes in the valence band [The recombination occurs directly across the gap in ldquodirect gaprdquo materials eg the 3-5 compound GaAs The recombination time is short about a nanosecond and the loss of electron energy is converted into the emission of a light particle or photon Silicon is an ldquoindirect gaprdquo semiconductor and the holes and electrons recombine in a much slower process that involves a small number of

impurities eg 1013 cm3 that are located in the forbidden gap and serve as recombination centers The recombination centers are energy levels in the forbidden gap that can capture eg a hole so it canrsquot move and but can still can attract and recombine with a free electron] The result is that the number of holes in n-type material pn is reduced to the number of holeselectrons pairs squared in intrinsic material ni

2 divided by the electron concentration in the n-type material nn A doping concentration of 1015 cm 3 reduces the hole concentration from 1010 to only 105 holescm3 as shown in figA-2b The holes become what are called the ldquominorityrdquo carriers Nevertheless the small minority carrier concentration plays an important role in diodes eg being responsible for the reverse saturation current in a p-n junction diode

Besides increasing the number of free mobile electrons donor doping introduces immobile ions that are positively charged after they donate an electron to the conduction band These positive charges cause electric fields (and forces on charges) Electric fields due to impurity atoms play an important role in the complex physical behavior at the junction of N-type and p-type material and thus influence the IV characteristics of diodes

Intrinsic silicon can be made p-type by adding column three dopant atoms creating broken covalent bonds without adding electrons see figsA-3a and A-3b Note that the original acceptor is neutral but will probably have its broken bond filled by electrons from the more numerous silicon host atoms that surround it Thus the acceptor atom becomes a negatively charged fixed ion The broken bond (hole) will randomly move around the crystal unless an electric field is applied and then the broken bonds will behave as positive charge and add to the current due to the applied E-field Current that flows in n-type or p-type material because of free charges electrons or holes which move under the influence of electric fields is called drift current The electric field could be due to applied voltage to the material or due to the electric field generated by positive and negative impurity atoms at the junction between P and N-type material There is another cause for free charge motion in semiconductors and that is diffusion due to carrier concentration gradients eg due to added impurity distributions that are not constant in space At the boundary between P and N type material the sum of the diffusion current due to electrons and holes moving across the boundary is cancelled out by the drift current due to the electric field due to the ionized donors and acceptors

The conductivity of n-type material depends on the number of free electrons n and a very important semiconductor property the electron mobility n Electron mobility indicates the velocity response of an electron due to an electric field The value of mobility is about 1500 [cm2volt sec] for silicon material doped at 1015 atcm3 [The mobility decreases as the doping level is increased to obtain more free electrons to eg it is about 500 for added impurities at the 1019 atcm3 level The motion of electrons due to an electric field the drift velocity increases as the mobility times the electric field However at electric fields corresponding to 10 [v] applied across a 1 micron distance the drift velocity in silicon saturates at about 105 cmsec and may decrease further with increasing electric field which corresponds to the interesting property of negative resistance ie decreasing current with increasing voltage]

Mobility is the most important property of semiconductor material and is the major limitation on the speed of computers Thus new materials are often proposed to replace silicon for high-speed computers [These materials are usually in the 3-5 material systems such as the tri-constituent compounds InGaAs and InGaP Although some of these materials have electron mobilities that are of the order of 100 times those for silicon the mobility for the high fields that are needed for short channel MOSFETs is much less even being less than for Silicon There are significant research efforts to synthesize high mobility semiconductors The efforts include looking at non-crystalline materials as well as using dimensions as small as several atoms in order to change the band-structure of the semiconductor]

The time for holes to recombine with excess electrons (added to p-type material eg by optical excitation or by injection of electrons due to forward bias in a p-n junction) is defined as the minority carrier lifetime The 3-5 compounds differ from silicon in that this time is of the order of a nanosecond in the 3-5 compounds versus a microsecond or more in silicon The minority carrier lifetime in semiconductors or recombination time is the other important property of semiconductors Mobility and lifetime are the two properties that control the performance of electronic devices

The conductivity of p-type material is proportional to the hole concentration p and the hole mobility p The hole mobility is about 40 of the electron mobility in silicon Equations for the conductivity and resistance of semiconductor material are summarized below Note that resistivity is the reciprocal of conductivity and that L is the length W the width and t the thickness of a rectangular region of material in cm

1) N [-cm] = q n n 2) P [cmq p p 3) R = LWt 4)

To fabricate electronic devices and circuits materials with a wide-range of resistivities are desirable Mother Nature has provided electronic engineers with an amazing range from 10minus6 to 1018 ohm-cm as shown in Table 41 Table 42 showed calculated values using the above equations for the conductivity and resistivity for the three types of semiconductors Reasonable values for the acceptor and donor impurity concentrations and corresponding values for mobility were assumed Note that for intrinsic material the conductivity due to electrons and holes must be added together to find the total conductivity

There is another cause for current due to free mobile charges besides their drift velocity due to an electric field Current can be due to diffusion which results whenever there is carrier concentration gradient Carrier concentration gradients occur when there is a spatial change in impurity concentration levels as in a p-n junction Diffusion current is important in the operation of mainly semiconductor devices eg forward biased diodes photo-diodes and solar cells Diffusion current can occur even without applied voltage

Exercise A41 Calculate the resistance of a bar of intrinsic silicon ( = 1000 ohm cm) that is ten m by ten m and 01 m thick [Note that the distance between atoms is about 3 A and that 10000 A is equal to one micron Recall also that 10000 m is equal to one cm]

Exercise A42 Confirm the calculated value of 416 [ohm-cm for the resistivity for n-type silicon with ND = 1015 [atcm3] in Table 42

Appendix 4-3 Review of the Development of Computer Hardware

The three-terminal devices that were used in the first manufactured computers (circa 1950) were vacuum tubes The tubes were structures enclosed in glass cylinders about one inch in diameter and two inches long that had the air within them largely pumped out to form a vacuum The structures provided the essential requirements of a three-terminal electronic device that could be used as a digital gate One requirement of the device was to have electrons flow from a source terminal (called the cathode in the case of the vacuum tube) to an output terminal (the anode) in response to voltage applied across these terminals A second requirement was to have a third terminal between the two terminals that could control (or increase and decrease) the current flow between the first two terminals

For a digital inverter circuit a more negative or ldquo0rdquo signal input to a third terminal the control terminal must be able to either cut off the current flow completely or reduce it enough so that the voltage on the output terminal can rise to the level of a lsquo1rsquosignal voltage In addition a ldquo1rdquo signal voltage applied to the control or input terminal should allow enough current to flow to cause the voltage drop across a resistor load to be large enough that the voltage at the output node is below a minimum value Since the output node voltage serves as an input to identical load inverters to be driven by inverter the minimum value must be small enough to shut off the current flow of these load inverters [The vacuum was necessary so that a tiny coil of metal wire a filament could be heated by passing current through it without oxidizing The hot filament caused electrons to boil out of a nearby metallic cathode These electrons were attracted to a metallic anode (about an inch or so away) by a voltage (typically 50 to 100 [v]) applied between the anode and the cathode

The anodecathode structure essentially formed a diode The vacuum diode was converted into a three-terminal triode by putting a metallic plate with lots of holes for electrons to pass through in the path between the cathode and the anode This grid-like structure was connected to the control terminal When the voltage between the grid and the cathode was small the structure could repel the electrons trying to flow to the anode from the cathode The structure named a grid therefore served as a valve to produce the desired effect of increasing and decreasing the flow of current between the cathode and the anode]

Several computer logic inverter components were held on printed circuit boards which were about ten inches by 5 inches The boards had a socket that plugged into a rack of equipment that was about ten feet high and two feet wide On one side of the printed circuit board were components such as the vacuum tubes held in sockets and discrete resistors about 18th inch diameter and frac12 inch long On the other side were electroplated conductors that were connected through holes to the components Electro-mechanical relays about the size of the vacuum tubes (making loud clicking noises) were added to the components to perform logic switching operations that did not require digital gain About ten racks of this hot noisy equipment and a few magnetic memory drums and tape

machines about the size and weight of the largest athletes made up the computer which typically occupied a room about the size of NJITrsquos theatre

The first computers could keep track of about 10000 airline and railroad reservations if the computer maintenance people were able to keep up with the many failures that often occurred in this non-microelectronic equipment [If you have a chance look at the relatively few journals of the IREIEEE in the early 1950s to see some photographs of the early ldquolarge-scalerdquo computers Experienced field service engineers often could tell from changes in the clicking sounds of the relays when the computer was making errors and rushed in to make repairs which sometimes could take hours Unlike the computers of today these computers were real machines that you could see hear smell and even feel the heat emanating from the large number of vacuum tubes The computers served the useful purpose of providing warmth in a cold room in the winter]

The first practical MOS transistors were made in the early sixties and prototype integrated circuits began to be made around 1970 It took several decades of engineering work by competing companies to make the present inexpensive computers with millions of silent reliable MOS logic gates and memories on the surface of a piece of silicon about the size of a quarter The tubes were replaced at first by the semiconductor bipolar junction transistor BJT Computers were made mainly with mass fabricated BJT integrated circuits in the 60s and 70s However in the 80s MOS digital circuits became increasingly preferred for large logic and memory arrays because of their lower standby power consumption This advantage is due to the nearly infinite input resistance of the control-gate input terminal which controls the flow of electrons between the source and drain output terminals just as the grid controlled the flow of electrons in the vacuum tube

The MOS transistor device and the digital logic and memory circuits that can be made from it are an outstanding technology achievement attributed to many engineers and material scientists with backgrounds similar to the students in this class Therefore it is a good idea to pay respect to their work by making a special effort to master the basic principles that went into their inventions that gave us the computer technology of today The many future applications that engineers will work on in the 21st century including the integrated engineering systems within a silicon chip (called MEMS for micro-electromechanical systems) could eventually exceed the impact of the computer They are built on the foundation of the computer engineers of the last five decades The micron-sized electromechanical structures are evolving so that they can be designed for functions involving eg optical signals fluid flow and biological and chemical systems Examples are the high speed testing of drugs (Orchard Inc) the reproduction and testing of DNA molecules and the manufacture of robots the size of dust mites These robots are able to travel within the body taking photographs and fly through caves with video and sound recording devices A pre-requisite for this course is to be a member of the IEEE so that you can keep up with these exciting developments

Table 41 Resistivity of Microelectronics Materials

Microelectronic Materials Resistivity [Ω-cm]Copper 17 10-6 Gold 23 10-6

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Tungsten Silicide [WSi2] 12 lt ρ lt 55 10-6

Polysilicon (used as a conductor) ~500 10-6

Platinum Silicide (PtSi) 30 10-6 Silicon (value depends on the concentration of the dopant) 10-4 lt ρ lt 10+5

Intrinsic GaAs 4 108 Intrinsic CdTe 1010 SiC 1010 SiO2 (55 Relative Humidity) 1017 ΩSiO2 (80 Relative Humidity) 1016 ΩHigh Resitivity Glass (60 Relative Humanity) ~1018 Ω

Note that the range of resistivity available to the microelectronic engineers is from 10-6 to ~10+8Ω-cm a 1024 range

Table 42 Summary of the Properties of Intrinsic N-type and P-type Silicon

Type Charges Concentration σ [Ωcm] -1 ρ [Ωcm]

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

positive fixed ionized donors

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

negative fixed ionized donors

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

Fig 42 Basic Concepts for Current in Semiconductor Material

[ohm cm] = n [cm 3] q [coul ] N [cm2 volt-sec] + pqP = 1 = conductivity resistivity in inverse ohm cmP = hole mobility [cm2 volt-sec] N = electron mobility [cm2 volt-sec]p= hole concentration in number of holes per cubic centimetern= electron concentration in number of electrons per cubic centimeter

Four Types of Charges in Semiconductor Devices

----- mobile free electrons (negatively charged)

----- mobile free holes (positively charged) Essentially a hole is a vacancy in the normal co-valence bonding between adjacent atoms

----- Immobile positively charged donor atoms that have ionized and donated a free electron to the surrounding semiconductor region Ionized atoms are immobile ie they do not move under the influence of an electric field unless the temperature is extremely high

----- Immobile negatively charged acceptor atoms that have ldquoacceptedrdquo an electron from their surroundings Taking the electron effectively creates a positive mobile hole that has some mobility or will move under the influence of an electric field A voltage applied across a region with negatively charged acceptors and free holes will result in current due to the motion of the mobile holes

Fig 43 Structure of the MOS Transistor

electrons

holest

Iε [Vcm]

Fig 43a The MOS Sandwich (Cross-section of the E-MOST)

Fig 43b Structure of the E-MOST (Enhancement Mode MOSFET)

1000 lt lm lt 10000Aring

01 lt ld lt 1 μm

50 lt tox lt 1000Aring

200 lt LD lt 300 μm

P- Substrate

SD SDG

channel

Low resistivity metaleg aluminum ρ = 27 [μΩcm]

Oxidized Silicone = SiO21010 lt ρox lt 1012

Heavily doped N+-typeSilicone eg n = 1019 [cm-3]

P- Substrateeg NA = 10-15 [cm-3]

Metal plate

Semiconductor plate

ohmic contact to lower plate

Fig 44 Models Outlining the Physical Behavior of the MOS Capacitor for Different Gate Voltages

Fig 44a

Fig 44b

Fig 44c

Fig 44d VG -1 -2 etc

P-type MOS Capacitor

Depletion Region(depleted of

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

Oxide 11 [V] gt VT = +1 [V]

Source or Drain Well

Mobile electrons that can move between the source and drain terminals

Induced electron charge in channel Channel thickness is only several atomic layers

VG + 2 [V]

2 [V] gt VT = +1 [V]

The increase in the number of electrons increases the conductivity of the channel More current flows from the drain to the source for the same value of drain to source voltage VDS

= mobile holes

= mobile electrons

= fixed ionized acceptors

Fig 45 Exercises to Develop Understanding of the MOST Regions of Operation

Given VDS = VGS ndash VT and ID = 1 [mA] Find the values for VDS and VGS for the MOST circuits Please identify the regions of operation ie S L and CO and the reason for why the transistor is eg in the saturation region

A step-by-step approach to do the exercise is suggesteda) Draw the direction of current flow and add the plusminus sign for the

voltage drops across the resistors and show the values of the dropsb) Write a small S and D at the source and drain terminals taking into

account the current directions for the P and N transistorsc) Find the voltage at the source and drain terminals from the applied voltage

and the drops across the resistors

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

d) Find VDS and VGS from the potential differences between the gate source and drain terminals Use the equation that separates the Linear and Saturation regions of the MOST to find the regions of operation

Fig 46 Analysis of a Simple MOSFET Circuit

a) The Circuit and Equations (Mathematical Steps) to Find the Q Point

1) VGS = VG VS = 3 2) Assume Saturation Region (VDS VDS ) ID = K2 [VGS VT ]2

ID = 250 AV2 2 (11) [3 1]2 = 500 A = 05 mA [Note K= KnWL]3) Find VR from VR = ID R = 5 [mA] 10K = 5 [v]4) Find VDS VD = 10 IR = 10 5 = 5 [v] Therefore the Q point is VGS = 3 [v] VDS = 5[v] and ID = 500 A

Check Is VDS VDS = VGS VT = 3 1 = 2 Yes as assumed

b) Circuit Analyzed by the Load Line Approach1) Sketch the Device Characteristic Using VDS and ID(sat) as shown in Fig b12) 2)Superimpose the Load Line as Done in Lesson 2 for Diode Circuits [See fig b2]3) The Q point is at the intersection of the two curves Note that the result is the

same as for graphical analysis

Figure 47 MOSFET Amplifier Circuit with DC Bias Circuitry and an Analog Signal Source (vs and Rs)

b) Circuits Showing the Voltage Drops Found from DC Analysis

a) Circuits for DC Bias Analysis (without The Analog Signal Generator Connected)

d) Graphical Analysis of the Circuitc) Circuit with the Analog Signal Source Connected to the Input

VDS = 5 [v]IDS = 500 [uA]

Figure 48 Circuit and Solution for PROBLEM ONE [Find the Q pt for the Circuit]

[Find the value of VDD so that VDS is four volts greater than the drain to source voltage at which the transistor enters the saturation region]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

rarr By voltage division

Figure 49 Circuit and Solution for PROBLEM TWO [Find the Q pt for the Circuit]

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

Since 20 [v] gt 10 [v] assumption is wrong and MOSFET is in the linear region

Wrong since 374 gt VDS2 = 2

and MOST assumed to be in linear region

Figure 55 Circuit and Solution for PROBLEM THREE [Find the Q pt for the Circuit]

a) VG = 4 [v] rarr VGS = 4 [v] rarr ID = 4 [mA] (if the transistor is in the saturation region)

However 4 [mA] 43 K = 5333 [v] the voltage drop across the resistor VR = 5333 [v]

would be greater than the voltage of 5 [v] applied drain source loop of the circuit

Therefore the MOST is not in the saturation region

b) Setting the current in the linear region equal to the current in the resistor equation 1

and 1a are obtained

22[1020

DSDSDSD

We can solve this equation by Trial and Error

Try VDS = 1 [v]YES VDS = 1 [v] is a solution for the equation And since 1 is less than VDS = 2 [v] it is the acceptable solution

If you solve the equation by the quadratic equation the VDS values will be 1 and 375 [v] Although mathematically VDS = 375 [v] is a solution 375gt VDS = 2[v] and this is unrealistic and unacceptable of the MOSFET is in the linear region

Figure 411 Circuit and Solution for PROBLEM FOUR Find the value of RL so that VDS = 1 [volt] and ID = 3 [mA]

Figure 412 Circuit and Solution for PROBLEM FIVE [Find the Q pt]

2)]2(4[102]

SDTSGDVVVVVVKI

The magnitude of the first term of the bracketed expression is always greater than the magnitude of the second term in the MOSFET linear equation)

VI SDDS

Solving equations 1) and 2) by either Trial and Error or the quadratic Quadratic equation yields ID and VSD DO this and check the results

VGS = -4VSG = +4

Figure 413 Basic Inverter Switch and Its Transfer Curve

a) Circuit

b) Transfer Curve

Fig 59 Typical Computer Voltage Signals

a) Signals in an Ideal Noiseless Environment

b) Signals in a Realistic Environment with Noise Due to High-Speed Circuitry

Comments on fig415 1) Conductors have a small amount of self-inductance proportional to their length and inversely proportional to their cross-section This is true even if they are flat and not in the form of coils Wires are made into coils when big inductance is required eg when micro-henries are needed When current flows through an inductor a voltage is induced across the conductor proportional to didt egv1 = L1di1dt Conductors also are not perfectly conducting but have some resistance even if very small These resistances in the conductors contribute to RC and LR time constants and signal propagation delays in computer circuits2) There is electromagnetic (EampM) coupling between wires ie currents flowing in a conductor send out EampM force fields which move adjacent charges in other conductors This is modeled by mutual inductance between eg wires 1 and 2 iev2 = M12 di1dt and v1 = M12 di2dt3) Electron charges on a wire induce equal and opposite charges (repelling electrons) on adjacent wires This is modeled by a capacitor between the wires Capacitance thus causes current flow eg i2 = C dv1dt Current is induced in wire 2 due to changing voltage in wire 1If the voltage pulses have fast rise and fall-times there will be more electromagnetic coupling between the wires and larger induced currents The induced currents will also be larger the closer the wires are to each other and if the wires run parallel to each other To minimize the induced current the wires should be kept apart and perpendicular to each other The voltages created by these currents depend on the impedance levels of the wires and loads that the currents flow through4) Generally the coupling of EampM energy between wires acting as transmitters and as receivers causes unwanted effects in closely spaced conductors in high-speed computers The phenomena are similar to the desired pickup of EampM coupling from distant high power transmitters to radioTV antennas To partially suppress pickup the area of the ldquolooprdquo of conducting paths should be minimized5) You might notice that capacitance and mutual inductance might vary along the length of the wires Circuit layout and models are often too complex to analyze However there are eg transmission line models and other approaches NJIT students will learn more about these in the Transmission Line course for CoE students and the Fields courses for EE students Two practical guidelines for circuit

Fig 415 Sources of Noise in Computer

layout are a) minimize the area of loops of wires and b) minimize the distance that nearby wires run parallel to each other Fig 416 Transfer Characteristic of an Inverter Logic Circuit

Fig 417 Logic Array Showing the Need for InputOutput Compatibility

Figure 418 Realistic Transfer Curve Showing VIL and VIH

Fig 418a Realistic Transfer Curve Showing VIL and VIH Note that when the input signal is VIL or VIH the slope of the Transfer Curve is minus one VIL or VIH are used to find the Noise Margin which is the protection against noise for the inverter Noise can shift the input signal away from a normal operating point of the inverter

Figure 418b Example of an Error on a Load Inverter Created by Noise on the Output Signal of the Inverter Driving the Load Inverter

Figure 419 Definition of Propagation Delay Using Inverter Input Output Waveform

PHL = 3 ndash 1 [nsec]

PLH = 18 ndash 14 [nsec]

P equiv average propagation delay equiv (PHL + PLH ) 2

PAIR equiv (PHL + PLH ) Pair Delay equiv 2 (PHL + PLH ) delay through two identical inverters

Power Delay Product Figure of Merit of Logic Gates equiv Product of the average propagation delay times the average power dissipated in a gates

Another Definition for the Figure of Merit Product of the pair delay times the average power dissipated in the two gates

Fig 4A-1 Models for Intrinsic Semiconductors

Fig 4A-1a Bond Model for Intrinsic Semiconductors

Fig 4A-1b Band Model for Intrinsic Semiconductors

(b) (c) holemoves here

Broken bond (hole)

Conduction Band Mainly empty levels in the conduction band hold free electrons

bandgap 111 [eV] for Silicon 143 [eV] for GaAs

Valence Band whose energy levels are mainly filled with electrons

Energy [eV]1010 [cm-3] electrons ni

1010 [cm-3] holes pi

Silicon Host Atoms

electrons

Fig 4A-2 Models for N-type Extrinsic Semiconductors

Fig 4A-2a Bond Model for N-type Extrinsic Semiconductors

Fig 4A-2b Band Model for N-type Extrinsic Semiconductors

In this n-type semiconductor ni ndash ND = 1015 [cm-3] and pi = 105 [cm-3]Current flow is controlled by electrons σ = q μo n + q μp p - q μn n

V Ionized Acceptor Impurity atoms from column V of the periodic table

Loosely bond electron easily removed by thermal energy

Free electrons fill broken bond

Electrons recombines with a hole and thus p = pi = 1010 cm-3 is reduced to a much smaller value of (1010)21015 = 105 cm-3

E [eV]

nn = ND = 1015 [cm-3]

Donor level (ND donors)

(positively charge ionized donors)

pn = 105=(1010)21015

Fig 4A-3 Models for P-type Extrinsic Semiconductors

Fig 4A-3a Bond Model for P-type Extrinsic Semiconductors

Fig 4A-3b Band Model for P-type Extrinsic SemiconductorsIn this P-type material the majority carriers are holes pp and the minority carriers are electrons np

IIIIonized Acceptor Impurity atoms from column III of the periodic table

Initial broken bond due to the column III impurity with only three valence electrons versus the four valence electrons for Silicon

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

Recombining Most of these electrons thermally generated across the bandgap recombine with holes leaving only ~100 electrons [cm-3]

A hole is generate3d by ionizing the acceptors Excite an electron from the valence and edge up to the acceptor impurity level witch accepts the electron

pp ~ 1018 [cm-3]

Ionized acceptor eg 1018 [cm-3]

Example Problems with Solutions Given

propagation and pair signal delay times and the power-delay time product will be introduced

The lesson concludes with a concise description of noise ie undesirable coupling of voltages and currents from one wire to another nearby wire The electromagnetic phenomena causing the signal coupling will be described by sketches that show that the complex electromagnetic ldquopickuprdquo of noise signals onto wires and device terminals can be accounted for by capacitance and inductance that provide a simple model for the electromagnetic phenomena The lesson explains how the effects of the unwanted noise can be minimized by designing a digital circuit so that the output versus input voltage transfer characteristic will have a ldquonoise marginrdquo that protects against the noise signal causing an error eg the output becoming a one when it should be a zero Some discussion of the minimization of noise by optimizing the layout of wires connecting the devices is given

There are three appendices at the end of the lesson that would be nice to study in ECE 271 except that study time for many students is limited Appendix 41 presents the terminal currentvoltage characteristics for other types of FET devices such as the JFET and MESFET They are practically the same as those for the MOSFET You will need the JFET equations for other courses Appendix 42 offers a review of the basic properties of semiconductors as background to understand how the MOSFET characteristics depend on material properties and FET structure and dimensions However it is possible to learn how to design and analyze digital circuits starting with the FET characteristics without learning the device physics material science and manufacturing techniques on which the characteristics depend Therefore it is optional during this course to learn the basic subjects presented in appendix 42 You are encouraged to read appendix 42 at least once to get a feeling for the subject and to study the concepts in A-42 in the near future The knowledge of semiconductor devices will enable you to follow and anticipate the exciting developments of the components and systems that will be the heart of future generations of not only computers but also many other important solid state products such as sensors displays miniature robots laser beam switches and novel every-day products as watches vehicle components and medicines whose low-cost production is based on solid state technology

Appendix 43 expands on the first paragraph of this overview by presenting a brief review of the history of computer hardware This historical overview outlines how electronics technology evolved over the last 6 decades It should be read as a news article and not studied because of your limited time The section aims to give you an appreciation of the microelectronic devices and circuits that will be studied in the upcoming lessons and those that will be part of technology in the coming decades

A) Basic Concepts for the Metal-Oxide-Semiconductor Transistor (MOST)

There are four basic types of MOS transistors N-type EMOS P-type EMOS N-type DMOS and P-type DMOS Column one of fig41 lists the four transistor types Also in this column are the key parameters for each device the threshold voltage VT the gain factor K and the width to length ratio WL Typical values for 2005 for each parameter also are given under each name These parameters completely determine the device IV characteristic just as IS and nVT did for the diode Unlike the diode which has a single IV curve the three-

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

3) (VDS)2 41VDS +1 = 0

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

1) (VDS)2 194VDS + 154 = 0

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Aluminum 267 10-6

Tungsten 54 10-6

Tantulum 135 10-6

Intrinsic

mobile electrons ni

ni = 1010 24 10-6 (for μn = 1500 [cm2v-sec]) 0416 106

mobile holes pi

pi = 1010 24 10-6 (for μp = 500 [cm2v-sec]) 0125 106

n-type

1015 le ND le 1019

024(μn = 1500 [cm2v-sec] for ND = 1015) 416

160(μn = 100 [cm2v-sec] for ND = 1019) 625 10-3

p-type

1015 le NA le 1019

00768(μp = 480 [cm2v-sec] for NA = 1015) 13

80(μp = 50 [cm2v-sec] for NA = 1019) 00125

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

2 ]με

t ox =

μεt o

00 [μ

2 ]με

t ox =

μεt o

00 [μ

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

electrons

holest

Iε [Vcm]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

01 lt ld lt 1 μm

P- Substrate

SD SDG

channel

Metal plate

Semiconductor plate

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Fig 44a

Fig 44b

Fig 44c

mobile charge)

el elcurrrent

09 [V]lt VT = +1 [V]

P-type

VG + 09 [V]

VG + 11 [V]N+ N+

VG + 2 [V]

2 [V] gt VT = +1 [V]

= mobile holes

= mobile electrons

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

-2 1k 4k +8

VT = -3

1k 5k +10

VT = -3

-4 1k 6k +6

VT = -3

+10 6k 2k -2

VT = +2

+8 3k 1k +2

VT = -1

+8 3k 1k

VT = -1

-1 2k 5k +8

VT = +1

+8 2k 5k -1

VT = +1

ID 1 [mA]

VDS VSD

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

VDS = 5 [v]IDS = 500 [uA]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

][41004010 v

][404 vVVV SGGS

][4]24[2102][

32 mAVKI DSD

][6424 vVV DSDS

][104 vVV DSDD

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

)[(1022

3 DSDSTGSD

R IKVI

2[20102

DSDSDS

0104110 2 DSDS VV 01142 DSDS VV

384[v] ][260502

5793142

aacbbVDS

][974010

26010 mAK

Check ][9740])2

26050()26050(2[102 23 mAID

2 mA 10K = 20 [V]

Assuming Sat Region

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

and 1a are obtained

22[1020

DSDSDSD

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

2)]2(4[102]

SDTSGDVVVVVVKI

VI SDDS

VGS = -4VSG = +4

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

a) Circuit

b) Transfer Curve

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Broken bond (hole)

Silicon Host Atoms

electrons

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

E [eV]

nn = ND = 1015 [cm-3]

pn = 105=(1010)21015

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

E [eV]

np = (ni)2pp = (1010)21018 = 100 [cm-3]

pp ~ 1018 [cm-3]

Documents

Key Lecture Concepts for CoE225/EE 271 (Mostly Digital ...hychang/ece271_files/Lesson 4... · Web viewCircuits for DC Bias Analysis (without The Analog Signal Generator Connected)