Kameshwar K. Yadavalli, Alexei O. Orlov, Ravi K. Kummamuru, John Timler, Craig Lent, Gary Bernstein,

and Gregory Snider

Department of Electrical EngineeringUniversity of Notre Dame

Supported by DARPA, NSF, ONR, and W. Keck Foundation

Fanout in Quantum-dot Cellular

Automata

Outline

Quantum Cellular Automata paradigm Initial devicesClocked QCAPower Delay ProductMetal tunnel junction implementationQCA latchQCA shift registerFanout in QCASummary

Quantum-dot Cellular Automata

A cell with 4 dots2 extra electrons

and inter-dot tunneling

Polarization P = +1Bit value “1”

Polarization P = -1Bit value “0” Neighboring cells tend to align

byCoulombic coupling

Information encoded in charge configuration

Polarization P = 1Bit value “1”

QCA simulations are available at

www.nd.edu/~qcahome/

0 01 1

01 10A

B

C

Out

Binary wire

Inverter

Majority gate

MABC

Programmable 2-input AND or OR

gate.

Initial QCA devices

Ground state computationPossibility of metastable statesLack of power gain and signal level degradation

Benefits of Clocked QCA

Power Gain. Energy is supplied directly to cells by the clock, not by the signal inputs alone.

Pipelined Architectures. Clocked cells in locked state acts as a memory controlled by the clock. A large QCA array can be divided into sub-arrays using phase shifted clocks.

Fanout in QCA. A single latch can drive multiple latches to create a complex circuit.

Pbath

PCLK

PoutPin

Adiabatic clocking with reversible computation canbeat the limit of power dissipation per bit operation,kTln2.

Implementation of Clocking in Quantum-dot Cellular Automata

Lent et al., Physics and Computation Conference, Nov. 1994Likharev and Korotkov, Science 273, 763, 1996

Metallic or molecular dots: Clocking achieved by modulating the energy of a third dot

P= +1 P= –1 Null State

Semiconductor dots:Clocking achieved by modulating inter-dot barriers

Clock signals need not have to be sent to individual cells, but to sub-arrays of cells.

Clocking in QCA

0 1

0

en

erg

y

xClock

Clock Applied

but Information is preserved!

0

Keyes and Landauer, IBM Journal of Res. Dev. 14, 152, 1970

Initial StateWith clock applied

Null State

Differential Inputapplied

Clock barrier isslowly raised

Input removed

Switching Energy in QCA

Quasi-adiabatic operation of QCA devices leads to very low power dissipation.

QCA Latch: A Building Block

+VIN

+VIN

-VIN

~

A

Vg

SEM Micrograph of a QCA latch

MTJ

D3

D1

D2

+VIN

+VIN

-VIN

1m

Electrometer

MTJ=multiple tunnel junction

The third, middle dot acts as an adjustable barrier for tunneling

D1

D2

D3

SET

MTJ

MTJ

MTJ

Experiment: Single-Electron Latch in Action

Weak input signal sets the direction of switching Clock drives the switching

Memory Function demonstrated Inverter Function demonstrated

D1

D2

D3

E1

-VIN

+VIN

VCLK

Latch

SET electrometer

-6

-3

0

-0.5

0.0

0.5

VC

LK (

mV

)V

IN

+ (m

V)

0 2 4 6 8 10

-0.2

0.0

0.2

VD

1 (m

V)

Time (sec)

Switch to “1”

Hold “1”

Switch to “neutral”

Switch to “0”

Hold “0”

Switch to “neutral”

Input

Clock“High

”

T=100 mK

QCA Two-Stage Shift Register Two latches with two electrometers for readout Inter-latch coupling by means of inter-digited capacitors (CC)

A Two-phase Clock to control electron switching is used One latch serves as input for the other

1mVCLK1 VCLK2

+VIN

-VIN

CC

CC

D1

D2

D3

D4

D5

D6

CC

CC

SEM micrograph

Operation of QCA Shift Register

Small external input applied – SR remains in neutral state

CLK1 applied 1st latch switches. Input now can be

removed CLK2 applied 2nd latch switches Process is repeated for the

inverted input

-0.20.00.2

0.00 0.35 0.70 1.05 1.40 1.75 2.10 2.45

-0.20.00.2

VC

LK2 (mV

)V

D4(mV

)

Time (sec)

-6

0

VD

1 (mV

)

-6

0

VC

LK1 (mV

)

-0.50.00.5

VIN

+ (mV

)

VCLK1 VCLK2

+VIN

-VIN

Fanout in QCA

CLK2

CLK1

+Input

-

CLK1

NULL

NULL

Writing Information into first stage latch

Transfer information intosecond stage latches

Fanout in QCA• Fanout in QCA allows for

complex circuits to be designed and operated.

• A latch in the first stage (L1) is coupled to two latches (L2, L3) in the second stage.

• A two phase clock (VCLK1, VCLK2) controls information transfer between the two stages.

• Information is first written into L1, then clocked into L2, L3 on the application of VCLK2.

VCLK2VCLK1

+VIN/2

E3

E4

(E2)

E1

SET

SET

SET

SET

L1 L2

-VIN/2

e

e

e

L3

Operation of Fanout in QCA

• All the latches are initially in null state.

• A differential input is then applied to L1, to define the polarization state.

• On the application of VCLK1, electron switches in L1 and is locked after the input is removed.

• VCLK2 is then applied to L2, L3, with the locked state of L1 providing the input to L2, L3.

• Information from L1 is written to L2 and L3.

QCA with Fanout

• An implicit demonstration of power gain and the benefit of clocking.

• In the absence of clocking, there will be signal level degradation in a fanout gate.

• Also, the middle latch will see two kinks resulting in a higher energy state, stopping the computation.

• As the second stage latches are driven by a weak input, the power gain in the second stage latches is greater than unity.

Kinks

•Enables multi-tasking architecture.•Affords the creation of complex circuitry.

Summary Clocked QCA offers a working paradigm for

digital nanoelectronics in the quantum realm:orders of magnitude lesser power

dissipation than FETspower gain for signal level restorationpipelining

Latch and shift register elements for information processing

Fanout gate in QCA paradigm is demonstrated Future Work: Molecules? High resistive

junctions for QCA latches in place of MTJs, for higher charging energy

Future Work: High speed measurements on QCA

Fabrication of Metal-dot QCA cells

Dots = small metal (Al) islands separated by tunnel junctions (Al203)Junctions: area of about 100 x 100 nm2 ; thickness is 0.1-0.5 nm Charging energy is small, so that operation temperature is low (<1K)High yield and good reproducibility allows proof of concept demonstration

Simple 4-dot cell is shownNo clocking yet!