Journal of vlsi design tools & technology (vol4, issue2)

(JoVDTT)

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www.stmjournals.comSTM JOURNALSScientific Technical Medical

STM JOURNALSScientific Technical Medical

STM JOURNALSScientific Technical Medical

May - August 2014 ISSN: 2321-6492

ü A Cuckoo Search based Approach for Solving Standard Cell Placement Problem

ü Triangular Waveform Generation using Mixed Signal Modeling

ü A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit

ü A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits

ü Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers

ü A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture

ü Design of High-Speed TIQ Comparator for Flash-Type ADC for (WPMOS/LPMOS

ü Comparative Analysis of Low-Power Adiabatic Techniques

ü Performance Estimation of VLSI Design

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Journal of VLSI Design Tools & Technology

Journal of VLSI Design Tools & Technology

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I take the privilege to present the hard copy compilation for the [Volume 4 Issue (2)] of Journal of

VLSI Design Tools & Technology (JoVDTT). The intension of JoVDTT is to create an atmosphere

that stimulates creativeness, research and growth in the area of VLSI Design Tools & Technology.

The development and growth of the mankind is the consequence of brilliant Research done by

eminent Scientists and Engineers in every field. JoVDTT provides an outlet for Research findings

and reviews in areas of VLSI Design Tools & Technology found to be relevant for National and

International recent developments & research initiative.

The aim and scope of the Journal is to provide an academic medium and an important reference for

the advancement and dissemination of Research results that support high level learning, teaching and

research in the domain of VLSI Design Tools & Technology.

Finally, I express my sincere gratitude and thanks to our Editorial/ Reviewer board and Authors for

their continued support and invaluable contributions and suggestions in the form of authoring write-

ups/ reviewing and providing constructive comments for the advancement of the journals. With

regards to their due continuous support and co-operation, we have been able to publish quality

Research/Reviesw findings for our customers base.

I hope you will enjoy reading this issue and we welcome your feedback on any aspect of the Journal.

Dr. Archana Mehrotra

Director

STM Journals

Director's Desk

STM JOURNALS

1. A Cuckoo Search based Approach for Solving Standard Cell Placement Problem Amanpreet Singh, Maninder Kaur 1

2. Triangular Waveform Generation using Mixed Signal Modeling Amit Krishna Dwivedi, A. Islam 8

3. A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder CircuitAshish S. Shende 18

4. A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated CircuitsHarshvardhan Upadhyay 24

5. Design and Analysis of Energy-Efficient GDI Cell and Its Impact on MultipliersPreethi Rangaraj, Naveen Raman 32

6. A Novel Current-Mode Quaternary Multiplier with Indian Vedic ArchitectureAshish S. Shende, Deepak R. Dandekar 37

7. Design of High-Speed TIQ Comparator for Flash-Type ADC for (WPMOS/LPMOS) > 1Neerja Singh, Tania Gupta 47

8. Comparative Analysis of Low-Power Adiabatic TechniquesCharu Rana, Priyanka Ohja 53

9. Performance Estimation of VLSI DesignArindam Sadhu, Pritam Bhattacherjee, Sabnam Koley 59

ContentsJournal of VLSI Design Tools & Technology

JoVDTT (2014)© STM Journals 2014. All Rights Reserved

Journal of VLSI Design Tools & Technology ISSN: 2249-474X (online), ISSN: 2321-6492 (print)

Volume 4, Issue 2

www.stmjournals.com

A Cuckoo Search based Approach for Solving Standard

Cell Placement Problem

Amanpreet Singh*, Maninder Kaur

School of Mathematics and Computer Applications, Thapar University, India

Abstract The standard cell placement (SCP) is an NP complete problem in VLSI layout which

focuses on placing the cells at appropriate locations so as to minimize the resultant

wirelength. The standard cell placement is one of the significant phases in VLSI circuit design. Many heuristic approaches have been developed in literature to solve this

problem. The paper presents an efficient nature-inspired meta-heuristic algorithm for

solving the standard cell placement problem based on cuckoo’s behavior. The performance of the proposed algorithm is tested against set of MCNC benchmarks

circuits. The experimental results showed promising results of the proposed algorithm in comparison to the existing meta-genetic approach.

Keywords: Cuckoo search, standard cells, VLSI, meta-heuristics, evolutionary algorithms



Volume 4, Issue 2

www.stmjournals.com

Triangular Waveform Generation using Mixed

Signal Modeling

Amit Krishna Dwivedi*, A. Islam Electronics and Communication Engineering, Birla Institute of Technology,

Mesra, Ranchi, Jharkhand, India

Abstract The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of analogue and mixed signal circuits to be described with a more lucid way

as compared to the conventional circuit-level simulators. Mixed-signal simulators are

thus providing a new platform for more efficient modeling of mixed signal that contains both the analogue and discrete features which was not previously possible. The non-linear

characteristics of many circuits are still difficult to be exactly described by the

conventional simulators. Hence it is required to explore the simulation behavior of analogue and mixed-signal circuits in a more efficient manner which can be done using

mixed signal modeling languages. This paper presents an alternative approach to model the behavior of analogue and mixed-signal circuits based upon piecewise linear

waveforms. A triangular waveform generator is modeled using the mixed signal

modeling. The proposed model of triangular waveform generator can be used in the circuits for signal processing. The triangular-wave generator is often necessary in

laboratories for efficient generation of other types of fixed periodic functions. It is also

useful for performance testing of electrical network and servo-systems. The waveform generator modeled using mixed-signal modeling provides more accurate and highly

precise waveform which reflects its advantages.

Keywords: Triangular waveform generators, Mixed-signal modeling, piecewise

linear waveforms

JoVDTT (2014) © STM Journals 2014. All Rights Reserved


Volume 4, Issue 2

www.stmjournals.com

A Simple, Compact, and Power-Efficient Current-Mode

Decimal Adder Circuit

Ashish S. Shende* Bapurao Deshmukh College of Engineering, Sewagram, Maharashtra, India

Abstract A size and power efficient current-mode decimal adder is proposed in this paper. The

proposed adder does not use binary coded decimal (BCD) number system for

processing the decimal data like other decimal adders. Instead, it processes the

decimal data as the actual decimal inputs. The proposed adder can be used as a

decimal half adder as well as a decimal full adder. The adder is based on simple

decimal arithmetic that we use in our daily life. The proposed adder has been

simulated in 90 nm technology with a supply voltage of 0.4 V and unit current step of

0.3 µA. The proposed adder occupies an area of only 3 µm2 and consumes only

7.52 µW power. This adder is suitable for commercial and financial applications

which spend most of their time in decimal computations. For future applications,

parallel decimal arithmetic will be more attractive to achieve the output with fewer

computations compared to binary and BCD arithmetic.

Keywords: Multi-valued logic, current-mode circuits, decimal adder, arithmetic units



Volume 4, Issue 2

www.stmjournals.com

A Survey on Recent Approaches for Leakage Power

Reduction in MOS Integrated Circuits

Harshvardhan Upadhyay* RKDF Institute of Science and Technology, RGPV Bhopal-462023, MP, India

Abstract Today the integrated circuit’s functionalities are increasing day by day with increase in

the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in

the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to

major losses, both at static and dynamic phases of the circuits. Power consumption is based on the number of elements and its fabrication [1] with its orientation and

connections in an integrated circuit. It is the dominant factor in today’s scenario for any

VLSI circuit designer as reported by ITRS [2]. Different techniques such as stack [3, 4],

sleepy stack [5, 6], sleepy keeper [3], leakage feedback with stack [4], etc., were

developed to reduce leakage power consumption at the cost of delay and area penalty. Here the author makes a review of all the different approaches which have overcome the

critical parameters such as area and delay penalty with high performance and increased

density to greater extent.

Keywords: Stack, sleepy stack, leakage feedback, sleepy keeper



Volume 4, Issue 2

www.stmjournals.com

Design and Analysis of Energy-Efficient GDI Cell and Its

Impact on Multipliers

Preethi Rangaraj1*, Naveen Raman

2

1VLSI Design, Info Institute of Engineering, Kovilpalayam, India

2AP/ECE, Info Institute of Engineering, Kovilpalayam, India

Abstract VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this

paper, power is concerned more as compared to area and speed. GDI (gate diffusion

input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, this technique is

extensively used in many low-power applications. This paper presents three different

multipliers such as array multiplier, Wallace tree multiplier and Dadda multiplier based on GDI technique. The proposed designs were done using DSCH2 and were simulated

using 120 nm technology in Microwind EDA tool with a supply of 1.5 V.

Keywords: GDI, VLSI, CMOS, array multiplier, tree multiplier, power consumption



Volume 4, Issue 2

www.stmjournals.com

A Novel Current-Mode Quaternary Multiplier with

Indian Vedic Architecture

Ashish S. Shende*, Deepak R. Dandekar P.G. Department of Electronics Engineering, Bapurao Deshmukh College of Engineering,

Sewagram, Maharashtra, India

Abstract A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and

hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic

results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier

has been simulated using 0.18 µm technology with a power supply of 1 V and a unit

current step of 1 µA. The proposed multiplier works on simple quaternary arithmetic and has a very low transistor-count. The transient delay of the proposed multiplier also has

been improved compared to our previous multiplier. The proposed approach of employing multi-valued logic with Vedic architecture has made the application of multi-

valued logic simpler, which can make multi-valued circuits as generalized as binary

circuits.

Keywords: Multi-Valued Logic, Current-Mode Circuits, Vedic Multiplier, Urdhva

Tiryakbhyam Sutra, Digital Signal Processing



Volume 4, Issue 2

www.stmjournals.com

Design of High-Speed TIQ Comparator for Flash-Type

ADC for (WPMOS/LPMOS) > 1

Neerja Singh*, Tania Gupta

ABES Engineering College, Ghaziabad, U.P., India

Abstract Comparator is the circuit that compares an analog signal with the reference signal and

produces the binary output based on comparison. A Comparator is the main block in the

ADC design as it directly affects the conversion rate of an ADC. Depending on the type and architecture of the comparator, the comparator can have significant impact on the

performance of the target application. The speed and resolution of an ADC is directly

affected by the comparator input offset voltage, the delay and input signal range. This paper presents a high-speed TIQ comparator for flash type ADC with (Wpmos/Lpmos) > 1 to

achieve minimum propagation delay.

Keywords: Analog to digital converters (ADC), threshold inverters quantization

(TIQ), comparators, high speed, SoC



Volume 4, Issue 2

www.stmjournals.com

Comparative Analysis of Low-Power Adiabatic

Techniques

Charu Rana*, Priyanka Ohja Department of EECE, ITM University, Gurgaon, India

Abstract In today’s modern era, new revolutionary designs are replacing old traditional bulky

designs. Due to advancements in technology, low-power designs are in demand.

Advantages of adiabatic technique can be used for overcoming disadvantages of typical CMOS such as dissipated energy loss. Adiabatic techniques are extremely reliant on

parameter changes. In this paper, the merits of adiabatic techniques are depicted on the

basis of parameter variations. By the use of SPICE simulation, traditional CMOS inverter is compared with two adiabatic techniques, positive feedback adiabatic logic

(PFAL) inverter and efficient charge recovery logic (ECRL) inverter on 125 and 90 nm technology. The results show that adiabatic logic circuits are better energy-reducing

techniques than typical CMOS logic circuit.

Keywords: Clock power, adiabatic switching, energy dissipation, AC power supply,

ECRL logic circuit, PFAL logic circuit



Volume 4, Issue 2

www.stmjournals.com

Performance Estimation of VLSI Design

Arindam Sadhu, Pritam Bhattacherjee*, Sabnam Koley Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India

Abstract This paper explores performance estimation of VLSI design using simple RC delay model

based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.

Keyword: Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay,

Layout

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Journal of vlsi design tools & technology (vol4, issue2)