Jorge Guilherme Lisbon 20 April 2012 #1 High Dynamic Range Signal Conversion Jorge Guilherme INSTITUTO DE TELECOMUNICAÇÕES Basic Sciences and Enabling

Jorge Guilherme Lisbon 20 April 2012 # 1

High Dynamic Range Signal Conversion

Jorge Guilherme

INSTITUTO DE TELECOMUNICAÇÕESBasic Sciences and Enabling Technologies

Escola Superior de Tecnologia de Tomar Departamento de Engenharia Electrotécnica


Outline

Context

Pipeline Architecture

Design of a 15-bit 10 MS/s Pipeline ADC

Design of a 9-bit 10MS/s Logarithmic Pipeline ADC

Other Projects

DC-DC controller for Space Applications

Class D Audio Amplifier


ADSL

ModemMbits/s

kbits/s

To POTS Line card

POTS

Splitter

POTS

Splitter

ADSL

Modem Mbits/s

kbits/s

Twisted pair

Exchange End Customer End

ftoneskHz

Level

POTS

Upstream Downstream

1 7 29 38 2554 30 125 165 1104

ADSL modem structure

POTS and ADSL information channels

•255 subcarriers•14-bit QAM •Up to 8.8 Mbit/s

Context


28 30 32 34 36 38 40 42 44 4610

-20

10-15

10-10

10-5

100

SNR/bit (dB)

Ber

Digital QAM Modulation for M = 14 bits

Bit error rate probability as a function of SNR for 14 bit QAM Simulation with white noise

System considerations

For ADSL a ber of 10-8 requires an SNR of 42 dB for 14QAMADSL requires an 80-dB dynamic range ADC due to signal dynamics (80 dB = 42dB QAM + 3dB margin + 15dB crest factor + 10dB AGC + 10dB crosstalk)

Linear pipeline ADC with 13-bit resolutionLogarithmic 9-bit ADC converter with a max SNR of 44.3 dB and 80 dB

dynamic range

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 00

10

20

30

40

50

60

70

80SNR of Linear and Logarithmic A/D Converters Dynamic Range =80.8233 dB

Input Power (dBW)

Ou

tpu

t S

ign

al-

to-N

ois

e R

ati

o (

dB

)

11 bit

13 bit 9 bit log

2 solutions


Error

ADC Converter Types


Vin

ADC DAC

+

-

B bits

Vout

B bits B bits

Vin Stage 1 Stage 2 Stage M-1 Stage M

2Bn

n

nn

S/H

S/H

B1 B2 BM-1 BM

Digital delay line

Digital correction logic

bits word

N

M

bits output word

Pipeline ADC

2 2 22, 1 , 2 , ( 1), /

2 2 2 2 2 21 1 2 1 2 11

no Stage no Stage no Stage Mno S Hni

M

V V VVV

G G G G G G

Input Noise

2

2ln)1(

2 1

NFGBW

A

clk

N

OL Amplifier specifications


Pipeline ADC

MDAC


Matlab Pipeline ADC Model

0.8192 1.6384 2.4576 3.2768 4.096 4.9152 5.7344 6.5536

x 104

-2

-1

0

1

2

Code

DN

L [L

SB

]

Fs=03.00MHz Fin=0.749MHz , File=From Matlab Model

DNL= 1.60 / -1.00 LSB Offset= 0 LSB

0.8192 1.6384 2.4576 3.2768 4.096 4.9152 5.7344 6.5536

x 104

-2

-1

0

1

2

Code

INL

[LS

B]

INL= 2.28 / -2.19 LSB

0 0.5 1 1.5

-160

-140

-120

-100

-80

-60

-40

-20

0

Frequency [MHz]

Pow

er S

pect

ral D

ensi

ty [

dB]

Fs=03.00MHz Fin=0.749MHz , File=From Matlab Modelo 1= -0.10

o 2= -120.27

o 3= -124.22o 4= -121.46

o 5= -105.47

o 6= -114.73

o 7= -97.86

oWoSpur=-110.81

524288 point FFT

1 Avg FFT

H1= -0.10dBFS

HD2= -120.2dBc

HD3= -124.1dBc

WoSpur= -97.9dBc

SNR= 87.06dB

SNRFS= 87.16dBFS

THD= -96.95dB

SFDR= 97.76dB

SINAD= 86.64dB

SINADFS= 86.73dBFS

ENOBFS= 14.11bit

Offset= 0LSB

Phase= -0.07º


S/H

Flash DAC

Vinp

Backend 1.5b/stage

6b 10b

Output Register and Digital Error Correction Logic

R1

R2

C

1

2

1

Cal DACSAR

SAR

pipeline ADCVinn C

1

2

vbg Vrefp

Vrefn

Cal DAC

Vn

Vp

Backend Vref Generationcontrol

Vrefp

Vrefn

Vn

Vp

Offset Calibration

Architecture of the 15-bit 10MS/s self-calibrated pipeline ADC


Noise contribution of the Front-end Pipeline Blocks

Vin

Csh

Csh

2

2

1

1

1'

DACFlash

Input sampling capacitors

S/H amplifier

DAC

Resistors

Residue amplifier

MHzFoFn 702

RVod

FnIdTKVndac

3

16

fVdsatVdsat

Cc

TKVnamp 7

11

3

2

RFnTKVr 4

Kelvin 1998

The resistors and the DAC inject large noise!

The DAC noise current is proportional to gm


SNR system calculation

C = 10 pFCc = 10 pFIdac = 1mARstring = 1000 ohm

Noise Bandwidth of a 2 pole system = 0.7854 Fo helps reducing the noise from the DAC and resistors

Noise distribution by block

Quantization 26%KT/C 17%Resistors 20%DAC 16%Amplifiers 21%

Trade off between power, noise and resolution obtained by program

dBVnampVr

VndacVrVnampC

TKVref

Vref

SNR

N

79

32.2.2

.2.242

2.12

221

log10 22222

2

2

2


0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.080

10

20

30

40

50

60

70

80

90

100

Std. dev. Unity Current Source [%]

Yie

ld o

f th

e D

AC

IN

L [%

]

15-bit

14-bit

13-bit

22

β 2

min2

41

2

vt

ovd

AA

VWL

II

•Current steering DAC requirements: random errors•Current source sizing: std dev(I/I) = 0.027% for 13 bit linearity•Vod = 0.76V ==> total current source DAC transistor area = 0.817 mm2 , DAC area = 1.7 mm2

•Hierarchical symmetrical switching scheme used to compensate systematic errors

Current Steering DAC


DAC Layout

Area = 1.51x1.82 mm2

DAC Output

Current Steering DAC


Bias

vdd

gnd

Bias

Cc

VinP

OutP

I

M1

M3

M9

M2

M4

M5 M6

M7 M8

I

OutNCc

M10

M11 M12

M13M14 M15

VinN

Main schematic of the amplifiers used in the S/H and residue amplifiers

fVdsatVdsat

Cc

TKVnamp 7

11

3

2

CcCLCcCCLCCT ..1.1

222

23

22

.29.3.1.

.2.9.3.1..3

..29.3.2

1

)(

CTCgmgmgm

sCTC

Ccgmgms

CTCcgmCcCLgm

s

sCcCgmgmCTC

gm

sH

The amplifiers where designed based on the noise allowed to it dependent on Cc

A telescopic cascode compensation topology was chosen to minimize power

From Cc and GBW we obtained the gm and current of the input diferential pair

CC

gmGBW

2

Residue amplifier


0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.30

10

20

30

40

50

60

70

80

90

100Yield vs. relative accuracy (6 bit FLASH)

Std. dev. Comparator Offset [LSB]

Yie

ld f

or

INL

=0.

5 L

SB

[%

]

S/H

C

C

C

C

-Vref

+Vref

1

1

1

0

R

Vin

Yield of a 6 bit flash for INL=0.5LSB

2 22 2β2

4GS Tvt vt

i i i

AV VA AVos

WL WL WL

Yield Simulation of a flash


vdd

b0 b1

Control_Z

Control

b2 b3ROM

ROM

Resistor String

Capacitors

Area = 1.7 * 0.72 mm2

Com

para

tor

ROM Implementation


15-bit 10MS/s pipeline ADC Chip Layout

Resolution 15 bitConversion rate 10 Ms/sPower consumption 320 mWPower supply 2.7-3.3VInput range 1.1VSNDR 77.2 dBTHD 84.8 dBENB 12.5 bitDNL, fin = 9.5 kHz 1.5 LSB at 15-bitINL, fin = 9.5 kHz 3.3 LSB at 15-bitChip area 3.23 mm*4.75 mmCore area 2.8 mm * 4.3 mmProcess technology 0.35 m CMOS

single poly 5-metal

Summary

DACS/H

Backend 10 bitFlash

Calib

rationB

lock R

esidueam

plifier

Cloc

k

Flash Vref buffer

Local decoup

lingLocal decoup

ling


0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 105

-160

-140

-120

-100

-80

-60

-40

-20

0

Frequency [Hz]

Po

we

r S

pe

ctr

al

De

ns

ity

[d

B]

Fs= 1.00MHz Fin=0.010MHz Vdd=3.3V AD1510 Sample ad1510-d0012.BIN AvgFFT=5

Signal=-6.0dBN+HD=-77.2dB

N=-78.0dBTHD=78.8dBSNR=72.0dB

SINAD=71.2dBENOB=11.5bit

Extrapolated to Full Scale:THD=84.8dBSNR=78.0dB

SINAD=77.2dBENOB=12.5bit

( 1)(-6.00)

( 2)(-99.94)

( 3)(-85.42)

( 4)(-97.92)

( 5)(-96.92)

Evaluation of the linear pipeline ADC

Full Converter Experimental Results

THD=84.8 dBSNR=78 dBSINAD=77.2 dBENOB=12.5 bit


Evaluation of the linear pipeline ADC

Full Converter Experimental Results

0 0.4096 0.8192 1.2288 1.6384 2.048 2.4576 2.8672 3.2768

x 104

-4

-2

0

2

4

6

AD1510 INL Characteristic

CODE

INL

[L

SB

]

0.0001 0.4097 0.8193 1.2289 1.6385 2.0481 2.4577 2.8673

x 104

-1.5

-1

-0.5

0

0.5

1

1.5AD1510 DNL Characteristic

Output Digital Code

DN

L [

LS

B]

Vdd=3.3VFs=1MHzFin=9.5kHzVin=1.1V

16 million samples

Measured DNLMeasured INL


221 1ln1

3

2

3

2

RI

VnVVVbeV

R

OSTR

ROSR

ROUT

R1R2

R3Slopecompensation

Q2 Q1Ra Rb

Vout

VbgAo1

Ao2

R0

AVDD

M0

A1

Vbg

Ibias

Band-Gap

Bias current generation

Auxiliary Blocks

Ra Rb

Vcm

Vbg VrefpVbg

Vcm Vrefn

R1

R1

R2

R2

Reference VoltageVcm Voltage


Classical Linear Pipeline Converter

Subtraction/Addition Attenuation/Amplification

K

Multiplication by 2

xx

Linear Domain Logarithmic Domain

Square

22

The signal operations in the linear domain are replaced by their equivalent in the logarithmic domain

Vin

ADC DAC

+

-

B bits

Vout

B bits B bits

Vin Stage 1 Stage 2 Stage M-1 Stage M

2Bn

n

nn

S/H

S/H

B1 B2 BM-1 BM

Digital delay line

Digital correction logic

bits word

N

M

bits output word

Logarithmic transformation


Stage 1

SHAAnaloginput

Stage i Stage n

Registers

Digital Correction

Digital Output

k

Vref1

Vref2

Digital

Coder

Logarithmicattenuator/amplifier

Square

Gain

Vref4

Vref3

Vref5

Logarithmic pipeline ADC architecture

Replacing the signal operations in the linear pipeline we obtain a logarithmic pipeline ADC.

A k offset at the input extends the range down to zero due to the logarithmic characteristic.


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.2

0.4

0.6

0.8

1

1.2

1.4

Vin (V)

Re

sid

ue

vo

lta

ge

(V

)

Logarithmic A/D converter with digital error correction

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vin (V)

Ou

tpu

t D

igit

al

Co

de

Logarithmic A/D converter with digital error correction

Residue of first stageConverter characteristic

Converter characteristics for positive input signals.The squarer gives a parabolic characteristic to the residue

Logarithmic pipeline ADC

111

1log20

12

110N

KK

DRdB

k

SNRN

dB 11ln

23log10

2

10


-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Vin (V)

Ou

tpu

t N

orm

alis

e D

igit

al

Co

de

Symmetrical Logarithmic A/D converter with digital error correction

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

1.2

1.4

Vin (V)

Ou

tpu

t R

es

idu

e V

olt

ag

e (

V)

Symmetrical Logarithmic A/D converter with digital error correction

After first stage residue signal is always positive due to squarer.

Following stages only process positive input signals.The sign bit is extracted by the intersection of the input stage

characteristics.Second stage is split in two to allow the sign bit decision

Solution for bipolar characteristic

1.5 bitADC

PGA Square

Offsetcalibration

1.5 bitADC

PGA Square

Offsetcalibration

Positive

Negative

1.5 bitADC

PGASquare

1.5 bitADC

PGA

Offsetcalibration

1st Stage 2nd Stage

sign bit

vinp,vinn

+vref

-vref



vin+

vin-

vcm

out

Gain control

Gain control

6C

2C

C

Vin

1'

1

1

1

2

2a

2b

2c

2d

Digital

Coder

Vref1

Vref2

2a

2b

2c

2d

phases

1

2

T

2a,2b2c,2d

1.5-bit pipeline stage block diagram


Squarer


1.5 bitADC

PGA Square

Offsetcalibration

1.5 bitADC

PGA Square

Offsetcalibration

Positive

Negative

1.5 bitADC

PGASquare

1.5 bitADC

PGA

Offsetcalibration

1.5 bitADC

PGA Square

Offsetcalibration

2 bitADC

Last StageStage i1st Stage 2nd Stage

sign bit

Timing Generationclock

calibration

vinnp,vinnn

vinpp,vinpn

vref1

vref2

vref3

vref4

vref5

Digital Calibration and

avdd dvdd svdd

Bias Current Generation

ibias

Power_down

vcm

agnd dgnd

Power_off_calib

gain control

Digital errorCorrection

OutputRegister b<0:9>

clkout

bypass_digcorr

in<0:1> stage<0:2> testtest_outptest_outn

controlPcontrolN

Test Mode

Architecture of the 9-bit 10MS/s logarithmic pipeline ADC


Resolution 9 bitConversion rate 10 Ms/sPower consumption 478 mWPower supply 2.2-2.7VInput range 1VSNR 45.7 dBDynamic range 79.28 dBChip area 3.1 mm*2.6 mmProcess technology 0.25 m CMOS

single poly 5-metal

Summary

Pipeline stages

Calibration stages

9-bit 10MS/s logarithmic pipeline ADC Chip Layout

CL

K


Measured output of the pipeline converter by injecting a triangular waveform of 250 Hz at the input, for a clock frequency of 1.3 MHz

Evaluation of the logarithmic pipeline ADC


Other Projects


DC-DC Controller for Space Application

Radiation resistant isolated DC-DC converter using a forward topology


Controller Features

Current mode control, cycle by cycle current limit

Up to 2nF drive capability (to drive external power MOS)

Soft-Start

External shutdown/enable pin

Adjustable oscillator frequency (up to 2MHz) using a single resistor

PFM control mode for light loads to improve efficiency

Radiation hardening

Technology AMS 035 um CMOS


-

+

X8

-

+

AE

4Bit DAC

UVLOOSC

-

+

COMP

-

+

COMP

4

4Bit Counter

S

R Q

_

Q

+

LDOBandgapOscControl

UVLOSense

Soft Start Current Limit

Isense+

Isense-

Bandgap

VoltageSense

-

+

COMPIref

-

+

COMP

VoltageSense

Bandgap

Rc Cc

To all circuit

Shutdown

OUT

5V

Bandgap

Controller:

F

PWMPWM PFMPFMDRIVERDRIVER


Integrated Prototype:Area = 2.79 mm^2Technology: 0.35um CMOS C35B4C3 4M/2P/HR/5V IO


Class-D Audio Amplifier

MOSFETDrivers A

LoadLf

Cf

Lf

Cf

Vdd

Rfb

Rfb

MOSFETDrivers B

OscCarrier

C0

C0

Ri

Ri

Rs

Rs

In(t)

Rb1Rb3

Rb2Cb1

Rc1

Rc2

Cc1

Rb1Rb3

Rb2Cb1

Rc1

Rc2

Cc1

Results:

• THD below -92dB with 8ohm load at 680mW (~0.0025%)

• Over 26dB THD reduction when compared with open

loop results

• 3.6μVrms closed-loop base-band noise


Design Example – BTL Class-D

-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0-100

-90

-80

-70

-60

-50

-40

-30Total Harmonic Distortion

Amp (dB)

TH

D (

dB

)

Diff MAEF 2kHz 8ohm

Diff PWM 2kHz 8ohm

SE MAEF 2kHz 8ohm

SE PWM 2kHz 8ohm

26dBimprovement

26dBimprovement

THD simulation results for Class-D with and without filter feedback – Comparison between BTL and SE Amp.

Two very long sweeps were conducted, each with 120 long transient simulations.

The evolved filter improvement achieves over

26dB reduction for an 8 ohm load.

The BTL Class-D exhibits lower intrinsic HD and higher

open-loop diff gain, it has lower THD+N than the SE

case.


Test-Chip ArchitectureA Multi-mode Stereo Class-D Amplifier

Short-Circuit detectorInternal ControlReference

Generator

PowerH-Bridge(and replicas)

PowerDrivers

Vgsi4

4

4

4

LPF

Load

ExternalRC network

ExternalRC networkD

rive

cont

rol

QOscFFlvc

Leve

l Win

dow

con

trol

Tun

ning

and

con

trol

Dig PWM

PCM

4

DAC

PowerH-Bridge(and replicas)

PowerDrivers

Vgsi4

4

4

4

LPF

Load

ExternalRC network

ExternalRC network

Drive control

QOscFFlvc

Level Window

control

Tunning and control

Dig PWM

PCM

4

DAC

Designed – both schematic and layout

Ongoing design – schematic phase

Starting development

TC phase


Test-Chip LayoutFully differential BLT Class-D Amplifier – Single Channel (UMC 018 um)

Note: MPW area constrains TC to single channel (1 reticule, 1.52x1.52 mm^2)


Summary

A 15-bit 10MS/s pipeline ADC was presented Linearity determined by matching accuracy of a current steering DAC. A calibration scheme adjust the reference voltage of the backend

pipeline, instead of calibrating the gain of the front-end stage.

A 9-bit 10MS/s true logarithmic pipeline ADC derived from their linear counterparts.

Symmetrical characteristic with dynamic range independent of SNR

SNR of 44.3 dB for a dynamic range of 80 dB.

Other Projects DC-DC controller for Space Applications Class D Audio Amplifier

Documents

Jorge Guilherme Lisbon 20 April 2012 #1 High Dynamic Range Signal Conversion Jorge Guilherme INSTITUTO DE TELECOMUNICAÇÕES Basic Sciences and Enabling