John Brown Art Kay Tim Green Tina-TI

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High Current V-I Circuits. The Four Musketeers of HPL. Recognize. Analyze. Synthesize. Tina-ize. John Brown Art Kay Tim Green Tina-TI. Potential Applications, End Equipment, Markets Circuit Topologies Circuit Stability Issues - PowerPoint PPT Presentation

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  • John Brown Art Kay Tim Green Tina-TISynthesizeTina-izeThe Four Musketeers of HPLAnalyzeRecognizeHigh Current V-I Circuits

  • V-I Circuit Recognize ObjectivesPotential Applications, End Equipment, MarketsCircuit TopologiesCircuit Stability IssuesPower Dissipation IssuesTransient Protection IssuesPCB IssuesSemiconductor Overstress Issues

  • V-I Circuit Analyze, Synthesize, Tina-ize ObjectivesProvide Synthesis Techniques for Common TopologiesProvide Tools to Simplify Stability AnalysisProvide Analysis Techniques for Power DissipationProvide Solutions for Common Transient ProblemsProvide Tips for PCB LayoutsProvide Tricks for Tina-TI Analysis

  • Power Amplifiers Strategy for Markets1. High Volume GrowthCommunications Optical Networking ONET (TECs, Laser Diode Pumps, Avalanche Photodiode Bias HV)DLP Digital Light Projectors (high voltage OPA)Industrial Electromechanical (OPA, PWM)Automotive Electromechanical (OPA, PWM)2. Gen Std Catalog Products Steady Growth Industrial, Medical, Lab, ATE, Some Audio, ConsumerHigh Speed Buffers, High Voltage, High Current OPAs

  • Power Amplifiers Applications in Markets1. Test, Particularly Automated ATEAnalog Pin Driver, Power V & I Excitation2. Power Line CommunicationHigh Pulse Current Drive Through Transformeror Capacitor Coupled ac Power Line (Residential & Commercial)3. Displays High Current Driver for Dithering Projected Light Beam, High Voltage for Ink Jet Printers4. Industrial, Medical, Scientific, Analytical, and Laboratory TEC Drivers, Electromechanical Linear Valve/Positioner Drivers, Motors, Power Supplies5. Optical Networking / Gen Laser SystemsTEC Drivers (Thermo-electric Coolers), Laser Pumps 6. Some AudioHeadphone and Speaker Drivers7. Some AutomotivePower Steering Pumps, Window MotorsCOMPETITION1. Mostly Discrete2. National Semiconductor, ST, Maxim, Allegro, ON-SEMI, International Rectifier, Infineon, Toshiba

  • Review - Essential Principles Poles, Zeros, Bode Plots Op Amp Loop Gain Model Loop Gain Test and 1/ Rate-of-Closure Stability Criteria Loop Gain Rules-of-Thumb for Stability RO and ROUT

  • Commercial Break(Shameless Self-Promotion)See 15 Part Series: Operational Amplifier Stabilityhttp://www.analogzone.com/acqt0704.htm

  • Poles and Bode PlotsPole Location = fPMagnitude = -20dB/Decade SlopeSlope begins at fP and continues down as frequency increasesActual Function = -3dB down @ fPPhase = -45/Decade Slope through fPDecade Above fP Phase = -90Decade Below fP Phase = 0A(dB) = 20Log10(VOUT/VIN)

    AC

    R

    C

    VIN

    VOUT

    A = VOUT/VIN

    Single Pole Circuit Equivalent

    X100,000

    0

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    Frequency (Hz)

    A (dB)

    +90

    -90

    +45

    +-45

    10

    100

    1k

    10k

    100k

    1M

    10M

    Frequency (Hz)

    0

    q

    (degrees)

    -20dB/Decade-6dB/Octave

    -45o @ fP

    -45o/Decade

    fP

    -90o

    0o

    G

    0.707G = -3dB

    Straight-Line Approximation

    Actual Function

  • Zeros and Bode PlotsZero Location = fZMagnitude = +20dB/Decade SlopeSlope begins at fZ and continues up as frequency increasesActual Function = +3dB up @ fZPhase = +45/Decade Slope through fZDecade Above fZ Phase = +90Decade Below fZ Phase = 0A(dB) = 20Log10(VOUT/VIN)

    AC

    R

    C

    VOUT

    A = VOUT/VIN

    Single Zero Circuit Equivalent

    X100,000

    0

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    1M

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    Frequency (Hz)

    A (dB)

    +90

    -90

    +45

    +-45

    10

    100

    1k

    10k

    100k

    1M

    10M

    Frequency (Hz)

    0

    q

    (degrees)

    +90o

    0o

    +45o/Decade

    +45o @ fZ

    fZ

    +20dB/Decade+6dB/Octave

    Straight-Line Approximation

    G

    1.414G = +3dB(1/0.707)G = +3dB

    Actual Function

  • Op Amp: Intuitive Model

    +

    -

    K(f)

    VDIFF

    IN+

    IN-

    RIN

    RO

    VO

    VOUT

    x1

  • Op Amp Loop Gain ModelVOUT/VIN = Acl = Aol/(1+Aol)If Aol >> 1 then Acl 1/Aol: Open Loop Gain: Feedback FactorAcl: Closed Loop Gain1/b = Small Signal AC Gainb = feedback attenuation

    +

    -

    +

    -

    S

    VOUT

    b network

    b

    RF

    RI

    VIN

    Aol

    S

    +

    -

    VOUT

    VIN

    VFB

    VFB

    RF

    RI

    b =VFB/VOUT

    VOUT

    b network

  • Stability Criteria

  • Traditional Loop Gain TestOp Amp Loop Gain ModelOp Amp is Closed LoopSPICE Loop Gain Test:Break the Closed Loop at VOUTGround VINInject AC Source, VX, into VOUTAol = VY/VX

    +

    -

    +

    -

    b network

    RF

    RI

    VIN

    VFB

    VOUT

    +

    -

    +

    -

    RF

    RI

    VIN

    b network

    VFB

    VOUT

    VX

    VY

    1GF

    1GH

    Short for ACOpen for DC

    Open for ACShort for DC

  • and 1/ is easy to calculate as feedback network around the Op Amp1/ is reciprocal of Easy Rules-Of-Thumb and Tricks to Plot 1/ on Op Amp Aol Curve

    +

    -

    +

    -

    VOUT

    b network

    RF

    RI

    VIN

    VFB

    VFB

    RF

    RI

    b =VFB/VOUT

    VOUT

    b network

  • Loop Gain Using Aol & 1/Plot (in dB) 1/ on Op Amp Aol (in dB)Aol = Aol(dB) 1/(dB)Note how Aol changes with frequency

    Proof (using log functions): 20Log10[Aol] = 20Log10(Aol) - 20Log10(1/) = 20Log10[Aol/(1/)] = 20Log10[Aol]

    0

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    1k

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    Frequency (Hz)

    Aol (dB)

    fcl

    1/b

    Acl

    Aol

    Aol b(Loop Gain)

    Closed Loop Response

    Open Loop Response

  • Stability Criteria using 1/ & AolAt fcl: Loop Gain (Aolb) = 1

    Rate-of-Closure @ fcl =(Aol slope 1/ slope)*20dB/decade Rate-of-Closure @ fcl = STABLE**40dB/decade Rate-of-Closure@ fcl = UNSTABLE

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    10k

    1k

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    Frequency (Hz)

    Aol (dB)

    Aol

    1/b1

    1/b2

    1/b3

    1/b4

    fcl1

    fcl4

    fcl3

    fcl2

    *

    *

    **

    **

  • Loop Gain Bandwidth Rule: 45 degrees for f < fclAol (Loop Gain) Phase PlotLoop Stability Criteria:
  • Poles & Zeros Transfer: (1/, Aol) to Aol

    Aol & 1/ PlotLoop Gain Plot(Aol)To Plot Aol from Aol & 1/ Plot:

    Poles in Aol curve are poles in Aol (Loop Gain)PlotZeros in Aol curve are zeros in Aol (Loop Gain) Plot

    Poles in 1/ curve are zeros in Aol (Loop Gain) PlotZeros in 1/ curve are poles in Aol (Loop Gain) Plot[Remember: is the reciprocal of 1/]

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    100k

    10k

    1k

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    Frequency (Hz)

    A (dB)

    Aol

    fcl

    1/b

    fp1

    fp2

    fz1

    Aol

    b

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    1

    Frequency (Hz)

    A (dB)

    fp1

    fz1

    fp2

    fcl

  • Frequency Decade Rules for Loop GainLoop Gain View: Poles: fp1, fp2, fz1; Zero: fp3

    Rules of Thumb for Good Loop Stability:

    Place fp3 within a decade of fz1 fp1 and fz1 = -135 phase shift at fz1 fp3 < decade will keep phase from dipping further

    Place fp3 at least a decade below fcl Allows Aol curve to shift to the left by one decade

    +

    -

    +

    -

    VIN

    RI

    RF

    VOUT

    CL

    Cn

    Rn

    0

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    1k

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    1

    Frequency (Hz)

    A (dB)

    fcl

    fp1

    fp2

    fz1

    fp3

    Aol

    1/Beta

    VOUT/VIN

  • Op Amp Model for Derivation of ROUT From: Frederiksen, Thomas M. Intuitive Operational Amplifiers. McGraw-Hill Book Company. New York. Revised Edition. 1988.ROUT = RO / (1+Aol)

    +

    -

    RDIFF

    xAol

    RO

    -IN

    +IN

    -

    +

    VE

    Op Amp Model

    1A

    VOUT

    VO

    RF

    RI

    IOUT

    VFB

    ROUT = VOUT/IOUT

  • Op Amp Model for Loop Stability AnalysisRO is constant over the Op Amps bandwidth RO is defined as the Op Amps Open Loop Output Resistance RO is measured at IOUT = 0 Amps, f = 1MHz (use the unloaded RO for Loop Stability calculations since it will be the largest value worst case for Loop Stability analysis)RO is included when calculating b for Loop Stability analysis

  • RO & Op Amp Output Operation Bipolar Power Op Amps CMOS Power Op Amps Light Load vs Heavy Load

  • RO Measure w/DC Operating Point: IOUT = 0mA

  • RO Measure w/DC Operating Point: IOUT = 0mARO = VOA / AM1RO = 9.61mVrms / 698.17Arms RO = 13.765

  • RO Measure w/DC Operating Point IOUT = 4.45mA Sink

  • RO Measure w/DC Operating Point IOUT = 4.45mA SinkRO = VOA / AM1RO = 3.45Vrms / 706.25Arms RO = 4.885

  • RO Measure w/DC Operating Point IOUT = 5.61mA Source

  • RO Measure w/DC Operating Point IOUT = 5.61mA SourceRO = VOA / AM1RO = 3.29mVrms / 700.98Arms RO = 4.693

  • RO Measure w/DC Operating Point IOUT = 2.74A Source

  • RO Measure w/DC Operating Point IOUT = 2.74A SourceRO = VOA / AM1RO = 314.31uVrms / 550.1Arms RO = 0.571

  • RO Measure w/DC Operating Point IOUT = 2.2A Sink

  • RO Measure w/DC Operating Point IOUT = 2.2A SinkRO = VOA / AM1RO = 169.92uVrms / 635.16Arms RO = 0.267

  • RO Measure w/DC Operating Point IOUT = 0A

  • RO Measure w/DC Operating PointIOUT = 0ARO = VOA / AM1RO = 4.42mVrms / 702.69Arms RO = 6.29

  • RO Measure w/DC Operating PointIOUT = 1A Sink

  • RO Measure w/DC Operating PointIOUT = 1A SinkRO = VOA / AM1RO = 166.76Vrms / 540.19Arms RO = 0.309

  • RO Measure w/DC Operating PointIOUT = 1A Source

  • RO Measure w/DC Operating PointIOUT = 1A SourceRO = VOA / AM1RO = 166.61Vrms / 540.34Arms RO = 0.308

  • Non-Inverting Floating Load V-I Basic TopologyStability Analysis (w/effects of Ro)1/b & Aol TestLoop Gain TestTransient TestSmall Signal BW for Current Control

  • Non-Inverting V-I Floating LoadIOUT = VP / RSIOUT = {(R2*VIN) / (R1A + R1B + R2)} / RS+5V3.03A-5V-3.03AVPVPVPOp Amp Point of Feedback is VRSOp Amp Loop Gain forces +IN (VP) = -IN = VRS +1V-1V

  • Non-Inverting V-I Floating LoadRO Reflected Outside of Op Amp

  • Non-Inverting V-I Floating LoadFB#1 DC 1/b Derivation

  • Non-Inverting V-I Floating LoadFB#1 1/b Derivation

  • Non-Inverting V-I Floating LoadFB#1 1/b Data for RO No Load & Full Load

  • OPA548 Data Sheet Aol

  • Non-Inverting V-I Floating LoadFB#1 1/b Plot for RO No Load & Full Load

  • Non-Inverting V-I Floating LoadFB#1 1/b Tina SPICE

  • Non-Inverting V-I Floating LoadFB#1 1/b Tina SPICE Results

  • Non-Inverting V-I Floating LoadFB#1 1/b Tina SPICE Results

  • Non-Inverting V-I Floating LoadFB#1 Loop Gain Tina SPICE Results

  • Non-Inverting V-I Floating LoadFB#1 Transient Analysis Tina SPICE Circuit

  • Non-Inverting V-I Floating LoadFB#1 Transient Analysis Tina SPICE Results

  • Non-Inverting V-I Floating LoadAdd FB#2 and Predict 1/bNote: Load Current Control begins to roll-off in frequency where FB#2 dominates

  • Large Small Answer: The largest (smallest 1/) will dominate!How will the two feedbacks combine?

    +

    -

  • Non-Inverting V-I Floating LoadFB#2 Circuit

  • Non-Inverting V-I Floating LoadFB#2 High Frequency 1/b

  • Non-Inverting V-I Floating LoadFB#2 fz1

  • Non-Inverting V-I Floating LoadTina SPICE Loop Test

  • Non-Inverting V-I Floating LoadAol and 1/b Tina SPICE Results

  • Non-Inverting V-I Floating LoadLoop Gain Tina SPICE Results

  • Non-Inverting V-I Floating LoadIOUT/VIN AC Response Circuit

  • Non-Inverting V-I Floating LoadIOUT/VIN AC Tina SPICE Results

  • Non-Inverting V-I Floating LoadIOUT/VIN Transient Circuit

  • Non-Inverting V-I Floating LoadIOUT/VIN Transient Tina SPICE Results

  • Inverting V-I Floating LoadIOUT = {-VIN*(RF/RI)} / RSIOUT = -VIN*{RF/ (RI*RS)}+5V-3.03A-5V+3.03AOp Amp Point of Feedback is VRSOp Amp Loop Gain forces VRS = -VIN (RF/RI)-1V+1VStability Analysis & Compensation Techniques similar to Non-Inverting V-I Floating Load

  • Grounded Load V-IImproved Howland Current Pump Basic TopologyStability Analysis (w/effects of Ro)1/b & Aol TestLoop Gain TestTransient TestSmall Signal BW for Current Control

  • Improved Howland Current PumpIL Accuracy CircuitRT allows for trim to optimum ZOUT and improved DC Accuracy

  • Improved Howland Current PumpV-I DC Accuracy Calculations1% Resistors (w/RT=0) could yield only 9% Accuracy at T=25C

    Still useful for V-I control in Motors/Valves V-Torque ControlOuter position feedback adjusts V for final position

  • Improved Howland Current PumpGeneral EquationSet RX=RF and RZ=RI

  • Improved Howland Current PumpSimplified Equation

  • Improved Howland AC AnalysisOp Amp sees differential [(-IN) (+IN)] feedbackb = b- - b+ (Must be positive number else oscillation!)RFRI

  • Improved Howland AC Analysis

  • Improved Howland AC AnalysisInclude Effects of RORFRI

  • Improved Howland b- Calculation

  • Improved Howland b+ Calculation

  • Improved Howland 1/b Calculation

  • Improved Howland b- CalculationRO = Full Load

  • Improved Howland b+ CalculationRO = Full Load

  • Improved Howland 1/b CalculationRO = Full Load

  • Improved Howland 1/b CalculationNo Load & Full Load

    Change in RO from No Load to Full Load has nosignificant impact on the 1/b Plot

  • OPA569 Data Sheet Aol

  • Improved Howland 1/b Plot - Full Load

  • Improved Howland 1/b Tina SPICE Plot - Full Load

  • Improved Howland Loop Gain Tina SPICE Plot - Full Load

  • Improved Howland Tina Transient Analysis CircuitRFRI

  • Improved Howland Tina Transient Analysis Results

  • Improved HowlandModified 1/b for Stability

  • b+ FB#2 Calculation to Modify 1/b for Stability

  • Improved Howland AC AnalysisFinal Design for StabilityRFRI

  • Improved Howland AC Analysis1/b - Final Design for Stabilityfcl

  • Improved Howland AC AnalysisLoop Gain - Final Design for Stabilityfcl

  • Improved Howland AC Transfer AnalysisIL/VIN - Final Design for StabilityRFRI

  • Improved Howland AC Transfer AnalysisIL/VIN - Final Design for Stability

  • Improved Howland Transient AnalysisIL/VIN - Final Design for StabilityRFRI

  • Improved Howland Transient AnalysisIL/VIN - Final Design for Stability

  • High Current V-I General ChecklistLarge Signal & Transient SOA Considerations (V=L*di/dt)Bipolar Output Stages & OscillationsHigh Current GroundingHigh Current PCB TracesHigh Current Supply IssuesPower Supply Bypass (Low f & High f)Transient Protection (Supply, VIN, VOUT)Power Dissipation Considerations (see V-I Circuits Using External Transistors section)Consider:Short Circuit to Ground Power Dissipation Heatsink SelectionCurrent Sense Resistor (RS) Power Dissipation

  • V-I Large Signal Limits: V=Ldi/dt

  • Violate the Laws of Physics and Pay the Price!

  • Instant V-I Reversal SOA Violations

  • Output Stages fosc > UGBW oscillates unloaded? -- no oscillates with VIN=0? -- noSome Op Amps use composite output stages, usually on the negative output, that contain local feedback paths. Under reactive loads these output stages can oscillate.The Output R-C Snubber Network lowers the high frequency gain of the output stage preventing unwanted oscillations under reactive loads.PROBLEMSOLUTION

    -VS

    LOAD

    +

    -

    +

    -

    4.7kW

    VIN

    RF

    RI

    100kW

    100kW

    VOUT

    RSN

    CSN

    10W to 100W

    0.1mF to 1mF

  • Ground Loops fosc < UGBW oscillates unloaded? -- no oscillates with VIN=0? -- yesGround loops are created from load current flowing through parasitic resistances. If part of VOUT is fed back to Op Amp +input, positive feedback and oscillations can occur.

    Parasitic resistances can be made to look like a common mode input by using a Single-Point or Star ground connection. SOLUTIONPROBLEM

    +

    -

    +

    -

    -VS

    +VS

    RL

    RGy

    RGx

    RGv

    RGw

    RF

    RI

    Ground

    IL

    VIN

    VOUT

    +

    -

    +

    -

    RG

    StarGround Point

    VIN

    VOUT

    -VS

    +VS

    RL

    RF

    RI

  • PCB Traces fosc < UGBW oscillates unloaded? -- may or may not oscillates with VIN=0? -- may or may notDO NOT route high current, low impedance output traces near high impedance input traces.DO route high current output traces adjacent to each other (on top of each other in a multi-layer PCB) to form a twisted pair for EMI cancellation.

    +

    -

    +

    -

    VIN

    VOUT

    RI

    RF

    Rs

    GND

  • Supply LinesLoad current, IL, flows through power supply resistance, Rs, due to PCB trace or wiring. Modulated supply voltages appear at Op Amp Power pins. Modulated signal couples into amplifier which relies on supply pins as AC Ground.Power supply lead inductance, Ls, interacts with a capacitive load, CL, to form an oscillatory LC, high Q, tank circuit. fosc < UGBW oscillates unloaded? -- no oscillates with VIN=0? -- may or may notPROBLEMPROBLEM

    GainStage

    Power Stage

    RL

    IL

    -vs

    Rs

    +

    -

    +vs

    Ls

    CL

  • Proper Supply Line DecoupleCLF: Low Frequency Bypass10F / Amp Out (peak) Aluminum Electrolytic or Tantalum< 4 in (10cm) from Op Amp CHF: High Frequency Bypass0.1F Ceramic Directly at Op Amp Power Supply Pins

    RHF: Provisional Series CHF Resistance1 < RHF < 10 Highly Inductive Supply LinesSOLUTION

    +

    -

    RHF

    RHF

    CHF

    CHF

    CLF

    CLF

    +VS

    -VS

    < 4 in

  • Transient Protection

  • V-I Circuits Using External Transistors Choosing the Transistor Power Dissipation Considerations Traditional Floating Load Circuit Novel V-I Using Opposite Polarity Transistor

  • Example: OPA335 and Bipolar TransistorSupply: 5VUtility Gain BufferOutput Swing: 0V to 5VLoad:20ohm (250mA max)

    How do we choose the BJT?

  • Bipolar Junction Transistor (BJT)

    rb

    iout = hfe x ib

    vin

    +

    -

    ib

  • Design Process for Selecting Transistor

  • Simple Rule of Thumb CalculationsPower / PackageCollector CurrentBase Current Vceo (Collector to Emitter Break Down Voltage) Vbe (Base to Emitter Voltage)

  • DC Power DissipationWhen is there maximum power in the output transistor?DC SignalP

  • AC Sinusoidal SignalAC Power DissipationWhen is there maximum power in the output transistor?P

  • Maximum Power in the External Transistor

    Use the DC Maximum Power Dissipation for Worst Case

    Double the power for margin over temperature

  • Characteristics of Different Package TypesFor our example

    PackageMaxPower TA = 25C No heat sinkMaxPower TA = 85CNo heat sinkMaxPower TC = 25CRJARJA1in2 padRJCSOT-230.30.151400250--na--SOT-2230.750.43175 80--na--

    DPACIPAC1.50.6520100506.25TO-220215062.5--na--2.78TO-34.22.210030--na--1.25

  • TO-3TO-220IPAKDPAKSOT-223SOT-23Different Package Types

  • Simple Rule of Thumb CalculationsPower / PackageCollector CurrentBase Current Vceo (Collector to Emitter Break Down Voltage) Vbe (Base to Emitter Voltage)Weve looked at Power.Now lets investigate current.

  • Max Collector Current in the External TransistorThe OPA335 is a rail-to-rail out Vout_max = Vopa_max Vbe = 5V 0.6V = 4.4V Max Output Current = (Vout_max)/RL =4.4V / (20) = 220mAAdd 20% margin Ic_max rating > (220mA)(1.5) = 330mA

  • Maximum Base Current in the External TransistorStandard BJT Power Transistor: Typical hfe_min = 20.Base Current = Ic_max / hfe_min = 220mA / (20) = 11mA (too high)

    Use a Darlington. Typical minimum hfe_typ = 1000.Base Current = Ic_max / hfe_min = 220mA / (1000) = 220uA (good)Use less than 2mA for good swing to the rail.Darlington

  • Simple Rule of Thumb CalculationsPower / PackageCollector CurrentBase Current Vceo (Collector to Emitter Break Down Voltage) Vbe (Base to Emitter Voltage)Now lets investigate voltage ratings.

  • BJT Breakdown Voltages Max voltage across any junction is 5V Most transistor breakdown > 50V Add a protection resistor in the base Limit base current Provide Capacitive Isolation

  • Design ProcessHere is the are the results of the rule of thumb calculationsPower Rating > 225mWPackage Type: SOT23Ic_max rating > 330mAType: Darlington NPN

    Using Digikey parametric searchNarrow from 4638 8 transistors.

  • The result of the Digikey parametric search. We choose the least expensive one MMBT6427 @ $0.104.Parametric Search Results

  • Design ProcessNow we verify if our choice will really work!

  • MMBT6427 Data Sheet Look at the Maximum RatingsNo problem -- were working with 5V.Ic_max= 220mA (lots of margin)

  • Maximum Power / Junction Temperature Maximum power dissipation dictates device (junction) temperature Device temperature is also effected by -- Ambient temperature-- Package Type (Data specifications)-- Heat sink-- Air flow

  • Maximum Power / Junction TemperaturePower_Maximum = 112.5mWRule of thumb: double Power_Maximum.Power_Rating > 225mW (edge of Spec)Are we ok?MMBT6427 Transistor

  • Look at Thermal ModelThermal model with no heat sinkAnalogous to an electrical circuit TJ= PD( RJA) + TAT is analogous to voltageR is analogous to resistanceP is analogous to current

    PD

    RJA

    TA

    TJ

    TA

  • Use the Thermal ModelAssuming TA = 25oCTJ = PD( RJA) + TA = (112.5mW)(556oC/W) + 25oC = 87.5oCWhat is the maximum ambient operating temperature? Tmax_ambient = 150oC 62.5oC = 87.5oC (Enough margin?)

  • TJ = PD( RJC + RCS + RSA) + TA

    PD The power dissipation of the transistorTJ The junction temperatureTC The case temperature TS The heat sink temperatureTA The ambient temperatureThermal Model for the Heat Sink

    PD

    RJC

    RCS

    RSA

    TJ

    TC

    TS

    TA

  • Here is the Mechanical Description

  • T= PD( RJC + RCS + RSA) + TAJunction to Case RJC Typical Transistor in a TO220 Package

  • T= PD( RJC + RCS + RSA) + TACase to Sink RCS

  • T= PD( RJC + RCS + RSA) + TASink to Ambient RJC Example Heat Sink

  • T= PD( RJC + RCS + RSA) + TASink to Ambient RJC Natural Convection is 100 Feet /min

  • Detailed Analysis So FarBreakdown VoltagesIc_maxPower / Junction Temperature VBE / Output SwingIB / Op-Amp Drive

  • Output Swing (Consider Vbe) Vout_buffer_max = 5V 1.4V = 3.6VDisadvantage of the Darlington DarlingtonMMBT6427 Transistor1.4V

  • Typical Vbe = -2mV/oC At -25oCVbe = (-2mV/oC)(T Troom)Vbe = (-2mV/oC)(-25oC 25oC) = 0.1VVbe = 1.4V + 0.1V = 1.5V

    At 85CVbe = 1.4V - 0.12V = 1.28VOutput Swing (Consider Vbe over Temperature)

  • Whats the Real Output Swing?Whats the Real Max Current Out?Iout_max Estimate:Iout_max = Vout/RL = 5/20 = 250mAFrom the Graph:Vbe = 1.4VRefine Iout_max:Iout_max = (Vout Vbe)/RL = (5 -1.4)/20 = 180mARefine Vbe:Vbe = 1.37VMMBT6427 Transistor

  • Is the Base Current Okay?Worst Case hfe = 2.7kIb_max = Ic_max / hfe_minIb_max = 250mA / 2700 = 92.5uA (no problem)MMBT6427 Transistor

  • Summary of Buffer Design Using Bipolar Transistor

    Spec.Design Worst CaseTransistor Data Sheet RatingCommentMax Current250mA500mAMax Vbe1.5VLimits the buffer output swing to 3.5VMax Ambient Temperature87.5CDetermined using power dissipation and the thermal model. Ib Max Base Current92.5uAVce5V40VVcb540V

  • Bipolar Junction Transistor (BJT)

    rb

    iout = hfe x ib

    vin

    +

    -

    ib

  • What about design using Power MOSFETS?

    rin

    iout = gm x vin

    vin

  • Power MOSFET vs Power BJTPower MOSFET Voltage to Current device no gate current Vgs depends on transistor and Id Vgs typically ranges 2V to 10V

    Power BJT Current to Current I device base current significant Vbe = 0.7V for standard Vbe = 1.4V for Darlington

    Design process for MOSFET similar to BJT

  • Current Sources Design Example Two Different TopologiesTraditional Floating Load Inverted Transistor Floating Load Easy To StabilizeHeadroom Limited by VBE (VGS)Bandwidth Limited By Load

    More Difficult to StabilizeMore headroom than TraditionalWider Bandwidth than Traditional

  • Standard Floating Load Current Source with BJT Current BoostVin = VG1*1k/(1k+9k)Vin = 0.1VG1Vrsen = VinI_load = Vrsen/RsenLOADSense Resistor +Vrsen -

  • LOADSense Resistor +Vrsen -Series Resistor Limits Base Current and Isolates Op-Amp From Capacitance.Traditional Floating Load Current Source DC AnalysisAsymmetrical suppliesIncreased output swing faster di/dt

  • DC Analysis of Transistor BD675

    SpecDesign Worst CaseTransistor Data sheetIb max1.5A/750 = 2mAhfe_min = 750Op-Amp Swing25 1.0 = 24V @125C25 1.5 = 23.5V @-25COutput Swing BJT24 2.4 = 21.6V @125C23.5 2.6 = 20.9V @-25CIout Max21.6V/15 = 1.39A @125C20.9V/15 = 1.39A @-25CIcmax=4APmax(25)2/(4*15)=10.12W--see Tj --Ta max76.5C (Ta max> 60C)Tj @ Ta=60C=Pd(Rjc + Rjs + Rsa) + Ta=10.12W(3.13 + 0.44 + 3.7) + 60=133CTjmax=150C(Using heat sink)

  • AC Stability Analysis Short out the signal sourceAdd in the test circuitry

  • Before Tina SPICE Do a Hand AnalysisFind 1/ by looking at the feedback path. 1/ = Vtest/VfbThis section is a simple buffer

  • Before Tina SPICE Do a Hand AnalysisReplace the buffer with a wire, and analyze as a series circuit.

  • Hand Analysis of (1/) High and Low Frequency Extremes Transfer Function

  • Using Information from the Transfer FunctionAOL

  • Add another feedback path to stabilize the circuit.This circuits 1/ plot.Using Information from the Transfer FunctionHow will the two feedbacks combine?

  • Large Small Answer: The largest (smallest 1/) will dominate!

    How will the two feedbacks combine?

    +

    -

  • General Example: How would the red and blue curves add? Remember curves shown are 1/ curves, not curves!

  • General Example: How would the red and blue curves add? Remember that the curves shown are 1/ curves, not Curves!The combined feedback will follow the smallest 1/ curve (the larges ).

  • How to Select FB#2 to Stabilize the Circuit

  • How to Select FB#2 to Stabilize the Circuit

  • How to Separate the Two PathsBreak the FB#1 path here!

  • Solve for

  • Plot for 1/

  • Values Required for this Examplef = 15Hz, High Freq 1/ = 50dB

  • Using f = 15Hz, High Freq 1/ = 50dBSolve for Rd and Cf

  • Verify Stability Using Tina-SPICEPlenty of phase marginWorst Case 45o

  • Look at Transient Response Using Tina-SPICE

  • Look at Transient Response Using Tina-SPICE

  • The AC Transfer Function Using Tina-SPICE

  • Current Sources Design Example Two Different TopologiesTraditional Floating Load Inverted Transistor Floating Load Easy To StabilizeHeadroom Limited by VBE (VGS)Bandwidth Limited By Load

    More Difficult to StabilizeMore headroom then TraditionalWider Bandwidth then Traditional

    Done with the traditional floating loadLets look at the inverted topology.

  • Inverted Transistor Floating Load DC AnalysisSourceDrainGateCommon source configuration. Vgs does not effect headroom.

  • Inverted Transistor Floating Load DC AnalysisZener protects gate from over voltage.Resistor Isolates Op-Amp from Gate Capacitance

  • Inverted Transistor Floating Load AC AnalysisAdd test circuitDC Bias Required for proper functionality

  • Stability Analysis of Inverted Transistor Floating Load Circuit with No Compensation Note the Complex Conjugate zero (180o phase shift).60dB Rate of Closure

  • Add a Zero into Feedback Path

  • Add a Zero into Feedback Path

  • AC Stability Result Zero In FeedbackNote: The complex conjugate zero is gone.Loop Gain=0Phase margin < 0

  • Use another Feedback PathFB#2 will dominate at high frequencies

  • Use another Feedback Path

  • Hand Calculations for New Feedback Path

  • 20dB/dec0dBfc = 1kHzIn this exampleHand Calculations for New Feedback Path

  • We want to set the cut frequency at about 1kHz Hand Calculations for New Feedback Path

  • Final Compensation: Look at AC Stability

  • Plenty of phase margin (65deg)The composite 1/ is relatively flat for all significant loop gain.Final Compensation: Look at AC Stability

  • Final Compensation: Look at Transient

  • Final Compensation: Look at Transient

  • The AC Transfer Function Using Tina-SPICE

  • Current Sources Design Example SummaryTraditional Floating Load Inverted Transistor Floating Load Easy To StabilizeHeadroom Limited by VBE (VGS)Bandwidth Limited By Load

    More Difficult to StabilizeMore headroom then TraditionalWider Bandwidth then Traditional

    For the example:Vout Swing Max = 20.9VBandwidth = 100Hz(Bandwidth is maximized)For the example:Vout Swing Max = 24.65VBandwidth = 800Hz(This could be compensated for wider bandwidth)

  • High Power V-I Circuit Applications Power Packages Parallel Outputs for Higher Current V-I Using External Shunt V-I Using Internal Shunt (Burr-Brown Exclusive) Bridge Tied Load Constant Current PWM Driver

  • Power Operational Amplifier Packages

  • Power Operational Amplifier Packages

  • Power Amplifier OPA567, 569, 561 & DRV103, 104Adapter Boards Available From Tucson

  • Paralleling OutputsforMore Drive CurrentPower Op Amps

  • OPA548 Power Op Amp Application Paralleling for More Output Current+8V to 60V Total SupplyNOTES: (1) Works well for G < 10. Input offset causes output current to flow between amplifiers with G > 10. Gains (resistor ratios) of the two amplifiers should be carefully matched to ensure equal current sharing. (2) As configured (ILIM connected to V) output current limit is set to 10A (peak). Each amplifier is limited to 5A (peak). Other current limit values may be obtained, see Figure 3, Adjustable Current Limit.

    3A cont3A cont6A continuousOutput Swing to Rail Spec with 3A Load (V+) 4.1V(V) + 3.7V

  • OPA569 Power Op Amp Application Paralleling for More Output CurrentVos is Averaged and BW, SR are That of One Amplifier+2.7V to 5.5V Total Supply2A cont2A contOutput Swing to Rail with 2A Load (V+) 0.3V(V) + 0.3V4A continuous

  • Bridge Tied LoadforFloating OutputPower Op Amps

  • OPA549 Power Op Amp ApplicationBridge => 2x Voltage & 4x Power OutVTEC = 14VWont Swing Very Close to Supply Rail but Drives 8A Out+24V 5VHigh Power TEC, up to 8A+24V 5VNeil Albaugh Circuit SimulationPhysical Contact With a Circuit

  • OPA569 Power Op Amp ApplicationBridge => 2x Voltage & 4x Power OutCan be 3VUsually +2.5VOutput Needs to Swing Close to Supply RailOnly IC in Industry That Does This!!! 300mVPhysical Contact With a CircuitCan be 3VHigh Power TEC, up to 2A

  • FeedbackusingExternal Shunt ResistorDesigning Power Current Sources

  • OPA541 Power Op Amp ApplicationHowland Power Current SourceTransfer Function500mA out per 10V in= 50mA per VoltRS1Rtrim1IVRL

  • OPA541 Power Op Amp ApplicationHowland Power Current SourceTransfer Function600mA out per 10V in= 60mA per Volt

  • OPA541 Power Op Amp ApplicationHowland Power Current Source

  • OPA569 Power Op Amp Application -5V Single Supply with +VinConstant Current Using Ext ISHUNT FeedbackGrounded Anode

  • OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver

    Scope Photo+1V0V0V-1.25V-2. 25VLED OnLED Off0VMinus VoltagePlus Voltage

  • OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver

    Scope PhotoLED OnLED Off40sec Fall50sec FallMinus Voltage+1V0V0V-1.25V-2. 25V0VPlus Voltage

  • OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver

    Scope PhotoLED OffLED On15msec Rise Slow100sec RiseMinus Voltage+1V0V0V-1.25V-2. 25V0VPlus Voltage

  • OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver

    Scope PhotoLED OnLED Off12sec Fall12sec FallMinus Voltage+1V0V0V-1.25V-2. 25V0VPlus Voltage

  • OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver

    Scope PhotoLED OffLED On1.5msec Rise Slow12sec RiseMinus Voltage+1V0V0V-1.25V-2. 25V0VPlus Voltage

  • OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver

    Scope PhotoLED OffLED OnMinus Voltage+1V0V0V-1.25V-2.25V0VPlus Voltage

  • FeedbackusingInternal Current Monitor(Instead of External Shunt Resistor)Designing Power Current Sources

  • OPA569 Power Op Amp Application 2.5V Bipolar Supplies with -VinConstant Current Using IMONITOR Feedback-+Io Constant CurrentVin-4.2kFeedback Through IMONTIOROPA569+2.5V-2.5VR156912 1317 18RSET33k350mAIMONTIOR = (1/475 x Io)314 15-2.5V+2.5VLuxeon Star-0High Power LED on Heat Sink-2.5V+2.5VIo is Independent of changes in Rload (LED aging).Iin = 2.5V / 4.2k = 0.6mAVo pinIo = Iin x 475

    Io = (Vin / Rin) x 475

    = 285mAGrounded Cathode

  • OPA569 Power Op Amp Application 2.5V Bipolar Supplies with -Vin Grounded Cathode LED DriverLED OnLED Off+2.5V-2.5V+2.5V-2.5V+2.5V-2.5VScope Photo

  • OPA569 Power Op Amp Application 2.5V Bipolar Supplies with -Vin Grounded Cathode LED DriverLED OnLED Off+2.5V-2.5V+2.5V-2.5V+2.5V-2.5VScope Photo

  • OPA569 Power Op Amp Application +5V Single Supply with +VinConstant Current Using IMONITOR Feedback-+Io Constant CurrentVin-4.2kFeedback Through IMONTIOROPA569+5VR156912 1317 18RSET33k350mAIMONTIOR = (1/475 x Io)314 150V+5VLuxeon Star-0High Power LED on Heat Sink0V+2.5VIo is Independent of changes in Rload (LED aging) and +5V.Iin = +2.5V / 4.2k = +0.6mAIo = Iin x 475

    Io = (Vin / Rin) x 475

    = 285mAVo pin+5VUse REF3025 to make independent of +5V.+2.5V+5V0V+2.5V1,500pFVoutVLED10k10k+5V to Anode

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin+5V to Anode LED Driver

    Scope Photo+5V0V+5V0V+2.5V+5V0V+2.5VLED OnLED Off

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin+5V to Anode LED Driver

    LED OnLED OffScope Photo+5V0V+5V0V+2.5V+5V0V+2.5V

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin+5V to Anode LED Driver

    LED OffLED OnScope Photo+5V0V+5V0V+2.5V+5V0V+2.5V15sec Fall35sec DelayCharging Internal Gate Cap25sec Fall

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin+5V to Anode LED Driver

    LED OnLED OffScope Photo+5V0V+5V0V+2.5V+5V0V+2.5V5sec Rise4sec Rise

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin+5V to Anode LED Driver

    Scope Photo+5V0V+5V0V+2.5V+3.6V0V+2.5VLED OnLED Off+5V

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin+5V to Anode LED Driver

    Scope Photo+5V0V+5V0V+2.5V+3.6V0V+2.5VLED OnLED Off+5V

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin+5V to Anode LED Driver

    Scope Photo+5V0V+5V0V+2.5V+3.6V0V+2.5VLED OnLED Off+2.5V

  • OPA569 Power Op Amp Application +5V Single Supply with +VinConstant Current Using IMONITOR Feedback-+Io Constant CurrentVin+4.2kFeedback Through IMONTIOROPA569+5VR156912 1317 18RSET33k350mAIMONTIOR = (1/475 x Io)314 15+0.25V+2.75VLuxeon Star-0High Power LED on Heat SinkIo is Independent of changes in Rload (LED aging) and +5V.Iin = +2.5V / 4.2k = +0.6mAIo = Iin x 475

    Io = (Vin / Rin) x 475

    = 285mAVo pin0V+2.5V1,500pFVout+0.25V+0.25V offset is used to maintain min voltage on IMONITOR Current SourceGrounded Cathode

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED DriverScope Photo+5V0V0V+2.8V0V+2.5V+2.5VLED OnLED Off

  • OPA569 Power Op Amp Application +5V Single Supply with +VinGrounded Cathode LED DriverScope Photo+5V0V0V+2.8V0V+2.5VLED OnLED Off+2.5V

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED DriverScope Capture0V+2.5V0V+2.5VLED OnLED Off0V+2.5VVery Clean, Cf = 33,000pFClean (small overshoot), Cf = 1,500pFOscillation (333kHz, 0.64Vp-p), Cf = 0 pFV: 0.2V / small div T: 0.5us / small div3us per cycle => 333kHzLoop InstabilityStableStable0.64Vp-p

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED DriverScope Photo+5V0V0V+2.8V0V+2.5VLED OnLED Off+2.5V5sec Fall5sec Fall

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED DriverScope Photo+5V0V0V+2.8V0V+2.5VLED OnLED Off+2.5V12sec Rise12sec Rise

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED DriverScope Photo+5V0V0V+2.8V0V+2.5VLED OnLED Off+2.5V

  • OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED DriverScope Photo+5V0V0V+2.8V0V+2.5VLED OnLED Off+2.5V

  • FeedbackusingInternal Current Monitor(Instead of External Shunt Resistor)Designing Power Current Sources

  • OPA569 Power Op Amp Application +5V Single Supply, Current SourceTina Simulation

  • OPA569 Power Op Amp Application +5V Single Supply, Current SourceTina Simulation

  • OPA569 Power Op Amp Application +5V Single Supply, Current SourceTina Simulation

  • OPA569 Power Op Amp Application +5V Single Supply, Current SourceTina Simulation

  • Voltage Source DriveDesigning Power Voltage SourcesTina Simulations

  • OPA569 Power Op Amp Application +5V Single Supply, Voltage SourceTina Simulation

  • OPA569 Power Op Amp Application +5V Single Supply, Voltage SourceTina Simulation

  • OPA569 Power Op Amp Application +5V Single Supply, Voltage SourceTina Simulation

  • Bridge Tied LoadforFloating Output

    With Constant Current SourcePower Op Amps

  • OPA551 Power Op Amp Application 24V Single Supply, Current Source

  • OPA551 Power Op Amp Application 24V Single Supply, Current Source

  • OPA551 Power Op Amp Application 24V Single Supply, Current Source

  • OPA551 Power Op Amp Application 24V Single Supply, Current Source

  • OPA725 + Power Transistors Power Op Amp Application 5V Single Supply, Current Source

  • OPA725 + Power Transistors Power Op Amp Application 5V Single Supply, Current Source

  • OPA725 + Power Transistors Power Op Amp Application 5V Single Supply, Current Source

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationResistive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationResistive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationResistive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationResistive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationResistive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationResistive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationInductive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationInductive Load

  • OPA569 Power Op Amp Application +5V Single Supply, Bridge Current SourceTina SimulationInductive Load

  • DRV103 / DRV104 Low or Hi PWM DriversPWMConstant Output Current Application

  • DRV103 Constant Current PWM DriverUp to 3A OutSO-8 PowerPad8V-40V-+DelayVrefOscPWM0.1

    Load5.29mHINA139OPA3402.2nF10K2.2nF191K100K100KNCIset1A/VInput5V5VDRV1036541328Low-side SwitchDMOS Power Transistor

  • DRV103 Constant Current PWM Driver

    Chart1

    0.8285

    0.8302

    0.832

    0.832

    0.8297

    0.8273

    0.8226

    0.8151

    Iavg

    Vsup(V)

    I-load(A)

    Iset = 0.8VDRV103

    Sheet1

    VsIavg

    360.8285

    320.8302

    280.832

    240.832

    200.8297

    160.8273

    120.8226

    80.8151

    VsIavg

    320.8139

    280.8133

    240.8127

    200.8116

    160.8104

    120.8086

    80.8081

    Sheet1

    0

    0

    0

    0

    0

    0

    0

    0

    Iavg

    Vsup(V)

    I-load(A)

    IavgDRV103

    Sheet2

    0

    0

    0

    0

    0

    0

    0

    Iavg

    Vsup(V)

    I_Load(A)

    IavgDRV104

    Sheet3

  • DRV104 Constant Current PWM DriverUp to 1.5A peakSO-8 PowerPad8V-32VDMOS Power Transistor-+DelayVrefOscPWMLoad5.29mHINA139OPA3402.2nF10K2.2nF191K100K100KNCIset0.5A/VInput5V5V470pF0.2

    DRV104108,956,71113214High-side Switch

  • DRV104 Constant Current PWM Driver

    Chart3

    0.8139

    0.8133

    0.8127

    0.8116

    0.8104

    0.8086

    0.8081

    Iavg

    Vsup(V)

    I_Load(A)

    Iset = 1.6VDRV104

    Sheet1

    VsIavg

    360.8285

    320.8302

    280.832

    240.832

    200.8297

    160.8273

    120.8226

    80.8151

    VsIavg

    320.8139

    280.8133

    240.8127

    200.8116

    160.8104

    120.8086

    80.8081

    Sheet1

    0

    0

    0

    0

    0

    0

    0

    0

    Iavg

    Vsup(V)

    I-load(A)

    IavgDRV103

    Sheet2

    0

    0

    0

    0

    0

    0

    0

    Iavg

    Vsup(V)

    I_Load(A)

    IavgDRV104

    Sheet3

  • The EndOr Just the Beginning of High Current V-I Circuits?John Brown520-746-7348brown_john@ti.comTim Green520-746-7780green_tim@ti.comArt Kay520-746-6072kay_art@ti.comTina SPICEwww.designsoftware.com

    The lower diagram is the traditional control loop model which represents an op amp circuit with feedback. The top diagram depicts the sections of a typical op amp circuit with feedback which correspond to the control loop model. This model of an op amp circuit with feedback we will call the Op Amp Loop Gain Model. Notice that the Aol is the Op Amp data sheet parameter Aol, and is the open loop gain of the op amp. (Beta) is the amount of output voltage from VOUT which gets fed back as feedback. The network in this example is a resistor feedback network.

    In the derivation of VOUT/VIN we see that the closed loop gain function is directly defined by Aol and . When analyzing a circuit built in SPICE for simulation the traditional Loop Gain Test breaks the closed loop op amp circuit through the use of an inductor and capacitor. A very large value of inductance ensures the loop is closed at DC (a requirement for SPICE simulation is to be able to calculate a DC Operating Point first before performing an AC Analysis) but open at AC frequencies of interest. A very large value of capacitance ensures that our AC Small Signal Source is not connected at DC but is directly connected at the frequencies of interest.Before we simulate a circuit in SPICE we will want to know what the approximate outcome will be. Remember GIGO (Garbage In Garbage Out)!!Beta () and its reciprocal 1/Beta (1/) along with the data sheet Aol Curve will provide a powerful method for first-order approximations of Loop Gain analysis before we run SPICE. Beta () is easy to compute and its reciprocal even easier to plot!The 1/ plot plotted on the Aol curve will provide a clear picture of exactly what the Loop Gain (Aol) plot is. From our derivation above we clearly see that the Aol magnitude plot is simply the difference between Aol and 1/ when we plot 1/ in dB on an Aol curve. Note that as frequency increases Aol decreases. Aol is the gain left to correct for errors in the VOUT/VIN or Closed Loop response. So as Aol decreases the VOUT/VIN response will become less accurate until the point where Aol goes to 0dB where from then on the VOUT/VIN response will simply follow the Aol curve.Once we plot 1/ on the Aol curve there is an easy first-order check for stability called Rate-Of-Closure. This Rate-Of-Closure stability check is defined as the rate of closure of 1/ curve with the Aol curve at fcl, where loop gain goes to 0dB. A 40db/decade rate-of-closure implies an UNSTABLE circuit and a 20dB/decade rate-of-closure implies a STABLE circuit. The 40dB/decade rate-of-closure implies instability because it implies two poles in the Aol plot before fcl which can mean a 180 phase shift. Four examples are shown above with their respective rate-of-closure computed below.

    fcl1: Aol-1/1 = -20dB/decade - +20dB/decade = -40dB/decade 40dB/decade rate-of-closure & UNSTABLEfcl2: Aol-1/2 = -20dB/decade - 0dB/decade = -20dB/decade 20dB/decade rate-of-closure & STABLEfcl3: Aol-1/3 = -40dB/decade - 0dB/decade = -40dB/decade 40dB/decade rate-of-closure & UNSTABLEfcl4: Aol-1/4 = -40dB/decade - -20dB/decade = -20dB/decade 20dB/decade rate-of-closure & STABLEThe established loop stability criteria is less than a 180 degree phase shift at fcl, the frequency at which loop gain goes to zero. How close the phase shift is to a full 180 degrees phase shift at fcl is defined as phase margin. As detailed in this slide the recommended rule-of-thumb for real world circuits is to design for 135 degree phase shift (45 degree phase margin) throughout the loop gain bandwidth (f < fcl). This allows for the real world cases of power-up, power-down and power-transient conditions where the op amp can have changes in its Aol curve which may result in transient oscillations. This is especially undesirable in power op amp circuits. This rule-of-thumb also allows for extra phase margin in the loop gain bandwidth to account for additional real world phase shifts due to parasitic capacitances and PCB layout parasitics. Also, phase margins less than 45 degrees within the loop gain bandwidth can result in undesired peaking in the closed loop transfer function. The lower the phase margin dip and the closer it is to fcl, the more pronounced the closed loop peaking will be. This slide reminds us of the relationship between the Loop Gain plot and the Aol plot with a 1/ plot included on it. This relationship allows us to use the manufacturers Aol curve from an op amp data sheet and plot our feedback curve, 1/, on it. From these two plots it is easy to infer what is going on in the Loop Gain plot and therefore easy to synthesize what we need to modify our feedback to for good stability. Think of the Loop Gain plot as a open loop plot. The Aol plot is already an open loop plot and therefore poles in the Aol plot are poles in the Loop Gain plot, and zeros in the Aol are zeros in the Loop Gain plot. The 1/ plot is a plot of small-signal AC closed loop gain. If we want to open the loop and look at the effects of the feedback network we will see an inverse relationship as we analyze the network. A simpler way to remember the translation between the 1/ plot and Loop Gain plot is that the Loop Gain plot is Aol and the closed loop feedback plot is 1/. Therefore, since , is the reciprocal of 1/, poles in the 1/ plot will become zeros in the Loop Gain (Aol) plot and zeros in the 1/ plot will become poles in the Loop Gain plot (Aol). The decade rules for frequency in the Loop Gain plot are detailed in the slide above. These frequency decade rules will be used for 1/ plots and Aol plots as well as Aol, loop gain plots, which we can predict directly from the Aol and 1/ plots. For the circuit shown in this slide the Aol curve contains a second pole, fp2, around 100kHz due to the capacitive load, CL, and the op amps RO, the details of which will be presented in Part 6 of this series. We will create a feedback network that will meet our Loop Gain Bandwidth rule of 45 degrees margin for f< fcl. We will analyze and synthesize the feedback network using the 1/ plot and Aol plot with the knowledge of what we are doing to the Loop Gain plot, Aol. fp1 gives us a first pole at 10Hz in the Loop Gain plot which implies a 45 degree phase shift at 10Hz with phase shifting to a 90 degrees by 100Hz. At 1kHz, fz1, a zero in the 1/ plot, we add a pole in the Loop Gain plot and another 45 degree phase shift at 1kHz. Our total phase shift now is -135 degrees at 1kHz. But if we continue on in frequency with just fz1 we will reach -180 phase shift at 10kHz!! So we add fp3, a pole in the 1/ plot, which is a zero in the Loop Gain plot at 10kHz. This keeps the phase shift at 1kHz to -135 degrees and flattens the phase plot to -135 degrees phase shift from 1kHz to 10kHz (remember poles and zeros have an effect a decade above and a decade below their actual frequency location). fp2 adds another pole in the Loop Gain plot at 100kHz since fp2 is from the Aol plot. Between 10kHz, where fp3 is, and 100kHz, where fp2 is, we expect no change in phase shift since fp3 is a Loop Gain plot zero and fp2 is a Loop Gain plot pole.

    So if we keep poles and zeros spaced a decade away from each other they will keep the phase shift from dipping between them since each has an effect on one another a decade above and a decade below their location. The final key part of the Frequency Decade Rules for Loop Gain is to place fp3 no closer than a decade away from fcl. This allows for a decade shift in Aol towards the lower frequency range before we would be in a marginal stability condition. Typical Aol curves may shift as much as decade in the real world.

    The VOUT/VIN for this circuit is predicted to be flat until loop gain goes away at 100kHz, at which point it will then follow the Aol curve on down. As hinted at in the previous slide RO and ROUT are related. ROUT is RO reduced by loop gain. This slide will define the op amp model used for the derivation of ROUT from RO. This simplified op amp model focuses solely on the basic DC characteristics of an op amp. A high input resistance (100m to G), RDIFF develops an error voltage across it, VE, due to the voltage differences between -IN and +IN. The error voltage , VE, is amplified by the open loop gain factor Aol and becomes VO. In series with VO to the output, VOUT, is RO, the open loop output resistance. This slides summarizes the key points of RO.1. Power the maximum power that a transistor can dissipate is a primary concern. This is closely related to the Package used.2. Collector Current the maximum collector current is often a limiting factor when selecting a transistor.3. Base Current this current is typically supplied by the Op-Amp output and can be large for power devices.4. Vceo (Collector to Emitter Break Down Voltage) This voltage is typically large (Vceo > 50V). So, this parameter is most important for high voltage consideration.5. Vbe (Base to Emitter Voltage) This voltage drop can be significant in low voltage considerations.

    1. Power the maximum power that a transistor can dissipate is a primary concern. This is closely related to the Package used.2. Collector Current the maximum collector current is often a limiting factor when selecting a transistor.3. Base Current this current is typically supplied by the Op-Amp output and can be large for power devices.4. Vceo (Collector to Emitter Break Down Voltage) This voltage is typically large (Vceo > 50V). So, this parameter is most important for high voltage consideration.5. Vbe (Base to Emitter Voltage) This voltage drop can be significant in low voltage considerations.

    1. Power the maximum power that a transistor can dissipate is a primary concern. This is closely related to the Package used.2. Collector Current the maximum collector current is often a limiting factor when selecting a transistor.3. Base Current this current is typically supplied by the Op-Amp output and can be large for power devices.4. Vceo (Collector to Emitter Break Down Voltage) This voltage is typically large (Vceo > 50V). So, this parameter is most important for high voltage consideration.5. Vbe (Base to Emitter Voltage) This voltage drop can be significant in low voltage considerations.

    1. Power the maximum power that a transistor can dissipate is a primary concern. This is closely related to the Package used.2. Collector Current the maximum collector current is often a limiting factor when selecting a transistor.3. Base Current this current is typically supplied by the Op-Amp output and can be large for power devices.4. Vceo (Collector to Emitter Break Down Voltage) This voltage is typically large (Vceo > 50V). So, this parameter is most important for high voltage consideration.5. Vbe (Base to Emitter Voltage) This voltage drop can be significant in low voltage considerations.

    Using the above results and Digikey parametric search, we can narrow the search from 4638 transistors to 8 transistors. Of the 8 we select the least expensive.

    Another consideration with this design is the base to emitter voltage drop (VBE). This voltage directly impacts the output swing of the buffer circuit.Vout_buffer_max = 5V 1.4V = 3.6V Note that the large base to emitter voltage is a major disadvantage of the Darlington configuration (its actually two diodes in series).

    Another consideration with this design is the base to emitter voltage drop (VBE). This voltage directly impacts the output swing of the buffer circuit.Vout_buffer_max = 5V 1.4V = 3.6V Note that the large base to emitter voltage is a major disadvantage of the Darlington configuration (its actually two diodes in series).

    Another consideration with this design is the base to emitter voltage drop (VBE). This voltage directly impacts the output swing of the buffer circuit.Vout_buffer_max = 5V 1.4V = 3.6V Note that the large base to emitter voltage is a major disadvantage of the Darlington configuration (its actually two diodes in series).

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