J Comput ElectronDOI 10.1007/s10825-013-0483-6

Performance estimation of sub-30 nm junctionless tunnel FET(JLTFET)

Punyasloka Bal · M.W. Akram · Partha Mondal ·Bahniman Ghosh

© Springer Science+Business Media New York 2013

Abstract In this paper we examined the short channel be-havior of junction less tunnel field effect transistor (JLTFET)and a comparison was made with the conventional MOSFETon the basis of variability of device parameter. The JLT-FET is a heavily doped junctionless transistor which usesthe concept of tunneling, by narrowing the barrier betweensource and channel of the device, to turn the device ON andOFF. The JLTFET exhibits an improved subthreshold slope(SS) of 24 mV/decade and drain-induced barrier lowering(DIBL) of 38 mV/V as compared to SS of 73 mV/decadeand DIBL of 98 mV/V for the conventional MOSFET. Thesimulation result shows that the impact of length scaling onthreshold voltage for JLTFET is very less as compared toMOSFET. Even a JLTFET with gate length of 10 nm hasbetter SS than MOSFET with gate length of 25 nm, whichenlightens the superior electrostatic integrity and better scal-ability of JLTFET over MOSFET.

Keywords Band to band tunneling (BTBT) · Draininduced barrier lowering (DIBL) · Scaling · Junctionlesstunnel field effect transistor (JLTFET) · Subthreshold slope(SS)

P. Bal (�) · M.W. Akram · P. MondalDepartment of Electrical Engineering, Indian Institute ofTechnology Kanpur, Kanpur 208016, Indiae-mail: punya@iitk.ac.in

M.W. Akrame-mail: mwakram@iitk.ac.in

P. Mondale-mail: partham@iitk.ac.in

B. GhoshMicroelectronics Research Center, University of Texas at Austin,10100 Burnet Road, Austin, TX, 78758, USAe-mail: bghosh@utexas.edu

1 Introduction

As we scale down the metal oxide semiconductor field ef-fect transistor (MOSFET) to sub-30 nm regime, it faces fun-damental challenges and major difficulties in fabrication ofsharp doping gradient at the source and drain junction [1, 2].Poor electrostatic control and diminished short channel be-havior of conventional MOSFET gives rise to low value ofdrain induced barrier lowering (DIBL) and high leakage cur-rent in OFF state. The MOSFET is named as the inversionmode (IM) device due to the formation of inversion layer formaking the path of current to flow. Scaling down the supplyvoltage and threshold voltage in IM devices is a major con-tributor to the subthreshold leakage which leads to excessivepower consumption. The limitation in subthreshold swing(SS) due to Fermi Dirac distribution of energy becomes thebottleneck for further scaling of supply voltage. A low valueof subthreshold swing gives a lower subthreshold leakagewhich further gives rise to low power dissipation. A con-ventional MOSFET cannot overcome this theoretical limita-tion due to its drift diffusion mechanism of current conduc-tion. Over the last few decades, alternative transistors havebeen proposed to achieve SS lower than 60 mV/decade atroom temperature, because of low power demand. The mostcommonly reported among alternative transistors is tunnelfield effect transistor (TFET) [3], which does not suffer fromshort channel effects (SCEs) due to its tunneling barrier.Though conventional TFET has better subthreshold slope(SS) than inversion mode (IM) device, it has low ON cur-rent and fabrication becomes challenging in sub-20 nm re-gion for both TFET and IM device. Based on lilienfeld’sfirst transistor architecture [4], very recently, a transistor hasbeen proposed and named as junctionless field effect transis-tor (JLFET). The JLFET is basically an accumulation mode

J Comput Electron

Fig. 1 Schematicrepresentation of (a) structure ofJLTFET (b) structure ofinversion mode (IM) device

device which does not require any ultra-steep doping profileat the source and drain junctions. This shows that JLFET isa promising device for future technology as it reduces thefabrication complexity as well as cost of fabrication. To op-timize the performance of JLFET, new design approaches,such as, SOI JLFET, bulk planar JLFET, nanowire junction-less transistors [5–7], gate all around FET [8] have beenproposed. By taking the fabrication issue and limitation insupply voltage scaling into account, a new structure namedjunctionless tunnel field effect transistor (JLTFET) has beenproposed [9, 10], which is a tunnel FET without any sharpdoping profile. A JLTFET is a heavily doped junctionlesstransistor which uses the concept of band to band tunnel-ing, by narrowing the barrier between source and channelof the device, to turn the device ON and OFF [11]. SinceJLTFET is based on junctionless principle, so intrinsically ithas better short channel effects and variability. Though theconventional tunnel FET shows an improved IOFF and sub-threshold slope, however it is still limited due to its low ONcurrent. The newly proposed JLTFET overcomes the chal-lenges of low ON current suffered by conventional tunnelFET and also have improved subthreshold slope than con-ventional MOSFET. In this paper we explore the perfor-mance of JLTFET and conventional MOSFET and compar-ison was made on the basis of variation of gate length andoxide thickness.

2 Device structure and operation

Figure 1(a) shows the structure of JLTFET for n-channel op-eration. The JLTFET is a junctionless transistor with twogates; one is the controlling gate and second is the fixed gate.The function of fixed gate is to make the source of JLFETbehave as p-type by work function engineering. By mak-ing the source p type, we made JLFET to behave similar toTFET where, by fixing the side gate voltages and sweepingthe voltage of the control gate from 0 to VDD, we made thedevice ON and OFF.

The JLTFET is basically a junctionless transistor withuniform doping throughout the source, drain, and channelregion, however the operation of JLTFET is similar to thatof conventional tunnel FET. Figure 1(b) shows the struc-ture of IM device, which has similar device parameter asthat of JLTFET for performance comparison. Both the de-vice have a uniform doping of 2 × 1019 cm−3 for sourceand drain and are simulated for same threshold voltage ofVth = 0.407 V at a drain bias of VDS = 1 V. The spacerwidths of 5 nm and gate dielectric thickness of 2 nm aretaken same for both the devices. For JLTFET the fixed gateuses platinum as the gate material, with a work function of5.93 eV and the control gate uses p.polysilicon as gate ma-terial with work function of 4.7 eV. For inversion mode de-vice we have used p.polysilicon as gate material with a workfunction of 4.89 eV. Figure 2 shows the band diagram of

J Comput Electron

Fig. 2 Valence band and conduction band profile of ON state(VGS = 1 V) and OFF state (VGS = 0 V) of JLTFET with gate lengthLg = 25 nm

Table 1 Parameters for device simulation

Parameter JLTFET MOSFET

Channel doping (Nd) 2 × 1019 cm−3 2 × 1015 cm−3

Gate oxide thickness (TOX) 2 nm 2 nm

Gate work function 4.7 eV 4.89 eV

Channel length (Lg) 25 nm 25 nm

Silicon thickness (Tsi) 5 nm 5 nm

Width of spacers 5 nm 5nm

Work function of fixed gate 5.93 eV –

OFF state and ON state of JLTFET. When a positive voltageis applied to the control gate the band bending occurs andtunneling phenomenon begins, where electrons tunnel fromsource side to channel region to make device ON. The basicapproach is to convert the (N + N + N+) source, channeland drain of junctionless FET into a (P− I− N) structurewithout any physical doping. Hence JLTFET by combin-ing advantage of both JLFET and TFET signifies its impor-tance both in high ION/IOFF ratio and improved subthresh-old slope without any fabrication issue.

3 Results and discussion

All simulations are carried out using Silvaco Atlas version5.15.32 R [12] which uses non-local band to band tunnelingmodel (BTBT) to account for the current accumulated dueto tunneling of electron from source to channel side of theregime [12, p. 245]. We include the effect of Fermi Diracstatistics in the calculation of the intrinsic carrier concen-tration required in the expressions for Shockley Read Hall(SRH) recombination. We have used non local band to bandtunneling model and calibrated it with models used in [11].Assuming high doping concentrations Band gap narrowing(BGN) and auger recombination models are included in the

Fig. 3 ID–VG characteristic of JLTFET and MOSFET with gate lengthof 25 nm

simulations. Because of presence of high impurity atom inthe channel and also consideration of an interface trap (ordefect) effect, Shockley-Read -Hall (SRH) model is also in-cluded [14]. The interface trap effect on BTBT is also en-abled, by inclusion of trap assisted tunneling (TAT) modelgiven by Schenk [15, 16]. With the assumption of high k

metal stack direct gate tunneling was not included in thesimulation [13]. Figure 1(a) and (b) shows the structure ofJLTFET and MOSFET respectively and all the relevant pa-rameters used for simulation are listed in Table 1. The sim-ulated JLTFET structure has uniform doping throughout thesource, drain and channel region. For inversion mode de-vice the channel is doped P-type with a concentration of2 × 1015 cm−3 and source and drain doping remain samefor both the devices. Both the device (IM mode and JLT-FET) were optimized for same threshold voltage i.e. Vth =0.407 V (at a drain voltage of VDS = 1 V) (Vth extractionwas done using constant current method i.e. at VDS = 1 V atIDS = 10−7 Amp/µm). All other simulation parameters likeoxide thickness (Tox), gate dielectric constant (K), siliconthickness (Tsi), gate length (Lg) were remain same for boththe device.

The electrical characteristics of JLTFET and conven-tional MOSFET are compared in Fig. 3. We can observethat JLTFET has better ION/IOFF ratio and also have betterDIBL and subthreshold slope than conventional MOSFET.As the current conduction in MOSFET is due to diffusionmechanism, the theoretical limit of sub threshold slope is 60mV/decade. On the other hand, a JLTFET does not expe-rience the same theoretical limitation because here the cur-rent conduction mechanism is due to tunneling of electronby lowering the barrier height between source and channelof the device.

Figure 4 shows the qualitative comparison of junction-less tunnel FET and MOSFET at different drain voltages.By considering the operating point A, we can observe thatdue to sub-thermal subthreshold swing, TFET offers not

J Comput Electron

Fig. 4 Qualitative comparison of JLTFET and MOSFET at differentdrain bias. At operating point A due to sub thermal sub-threshold swingJLTFET offers an improved performance in terms of high ON currentand improved ION/IOFF

Fig. 5 ON state and OFF state current as a function of drain bias,Nd = 2 × 1019 cm−3, Tox = 2 nm, Tsi = 5 nm, Lg = 25 nm

only an improved ION/IOFF but also superior performancein terms of high ON current as well as steep SS (drainvoltages VDS = 50 mV and VDS = 1 V) than that of con-ventional MOSFET. SO TFET shows a good power saving(same ION at lower voltage) at the same performance of con-ventional MOSFET. At lower gate bias (for different drainbias), TFET can be a good switching device as comparedto MOSFET but as we go towards higher gate voltage (con-sider point B) then it can use as a good switching alternativeonly for drain bias of 1 V. For 50 mV of drain bias MOSFETcan be a better solution in case of efficient switching perfor-mance which provides high ON current at same voltage ascompared to JLTFET.

3.1 Supply voltage scaling

Figure 5 shows the plot for ON state current and OFF statecurrent as a function of different supply bias. We can ob-serve an interesting phenomenon like at low drain bias VDS

ranging from 50 mV to 0.7 V, the ON current of JLTFET is

Fig. 6 Effect of ON to OFF ratio as a function of drain bias for JLT-FET and MOSFET, Nd = 2 × 1019 cm−3, Lg = 25 nm and Tsi = 5 nm

lower than that of MOSFET but OFF state current is signifi-cantly lower than the conventional one. At higher drain biasON state current both almost lies in the same order for boththe devices but OFF state current of JLTFET has a marginallower value as compared to OFF state current of MOSFET.So the JLTFET not only gives high ION/IOFF but also pro-vides improved performance in terms of low OFF currentand low SS at same drain voltage, than that of conventionalMOSFET. At drain bias of 0.5 V the optimized performanceis observed in terms of good ON state current as well as lowleakage. The threshold voltages of devices are fixed at 0.4 V,which degrades the performance of JLTFET in terms of lowON current below 0.4 V. The performances can be improvedby decreasing the threshold voltages by fixing the metal gatework function to some lower value.

Figure 6 shows the comparative study of ION/IOFF forboth conventional MOSFET and JLTFET. As discussedfrom Fig. 5 due to lower OFF state current at lower drainbias, JLTFET offers an improved ION/IOFF as compared toconventional MOSFET. At higher drain bias the value al-most lies in same order as negligible difference observed be-tween the ON state current and OFF state current at higherbias. So JLTFET can be a good alternative for switchingapplication in terms of good ION/IOFF and better SS at adrain bias of 0.5 V. This value can be lowered by making thethreshold voltage minimum. At drain bias of 50 mV there issignificant improvement is observed, but at lower gate bias.With increase of VG the JLTFET fails to provide improvedON current as compared to MOSFET.

3.2 Length scaling

Figure 7 shows the performance comparison of DIBL andsubthreshold slope of JLTFET and IM device, as a func-tion of gate length and we observed that JLTFET have betterDIBL and subthreshold slope than that of IM device. Thesimulation results illustrates that, even a 10 nm gate length

J Comput Electron

Fig. 7 DIBL and subthreshold slope of JLTFET and IM device as afunction of gate length scaling

Fig. 8 Variation of threshold voltage as a function of gate length forboth the device with Nd = 2 × 1019 cm−3, Tox = 2 nm, Tsi = 5 nm

JLTFET have better subthreshold slope (∼32 mV/decade)and DIBL (∼49 mV/V) than a 25 nm inversion mode de-vice (where SS = ∼73 mV/decade, DIBL = ∼98 mV/V),which illuminates the better immunity of JLTFET towardsshort channel effects over conventional MOSFET.

Figure 8 shows the variation of threshold voltage of JLT-FET and conventional MOSFET as a function of gate length,with gate length scale down from 25 nm to 10 nm at VDS =1 V. We can see the variation in threshold voltage of MOS-FET is more as compared to JLTFET. With scaling of gatelength threshold voltage of IM device drops from 0.407 V at25 nm to 0.25 V at 10 nm, whereas for JLTFET it remainsinsensitive to channel length scaling. The gate capacitance(which include oxide related capacitance Cox) in MOSFETdepends on the thickness of gate dielectric (Tox). The cur-rent in MOSFET is inversely proportional to thickness ofgate dielectric (Tox), so the variation in Tox changes the ONcurrent and subthreshold slope as well. But in JLTFET theon current mainly depends on the height and width of tun-neling junction between source and channel of the region.

Fig. 9 ION/IOFF ratio and subthreshold slope as a function of ox-ide thickness for JLTFET and MOSFET with gate length of 25 nm,Tox = 2 nm, Tsi = 5 nm and Nd = 2 × 1019 cm−3

3.3 Gate dielectric

Figure 9 shows the ION/IOFF ratio and subthreshold slopeof JLTFET and conventional MOSFET versus different ox-ide thickness. Through simulation we observed that JLT-FET with Tox = 5 nm have better subthreshold slope(∼38 mV/decade) than inversion mode device with Tox =2 nm (SS = ∼70 mV/decade), taking all other device param-eter same for both JLTFET and IM device. The ION/IOFF ofboth the devices are obtained by taking the ON state cur-rent (at drain bias of 1 V and gate bias of 1 V) and OFFstate current (at drain bias of 1 V and gate bias of 0 V) into account. At Tox = 2 nm, the JLTFET has an ION/IOFF

of 4.08 × 109 and for MOSFET the ratio is approximately1.39 × 109, which is three times less in magnitude as com-pared to ION/IOFF of JLTFET. As we increase the oxidethickness to 5 nm (JLTFET offers an ION/IOFF of 1.85×108

and for MOSFET the value is 1.825 × 105), the differencein ION/IOFF for both the devices increases and at thickergate oxide JLTFET offers an improved performance bothin terms of low SS and high ION/IOFF (more than 3 or-der in magnitude than that of MOSFET). The conventionalthermally grown silicon dioxide (SiO2) will soon reach thethickness limit to serve as an effective gate dielectric forMOS devices. For performance optimization a new dielec-tric with a high dielectric constant (ex., HfO2, TiO2, Ta2O5,and ZrO2) is needed for serving the purpose of gate ox-ide [17–19]. Tantalum oxide (Ta2O5) is widely used as ahigh-k (K = 26) dielectric material due to its superior di-electric properties (low band gap of 4.4 eV and electronband offset of 0.3 eV). For future technology node the high-k gate dielectric film should be small (in the range of 0.6–1.1 nm) to serve for the performance optimization. The Tan-talum oxide (Ta2O5) can be grown in to an ultra-thin filmby postdeposition annealing (PDA) atmosphere [20]. In oursimulation we have taken a high K dielectric with effectiveoxide thickness of 2 nm [10]. We have neglects the gate leak-age in the calculation of tunneling current as we are using

J Comput Electron

Fig. 10 ION/IOFF ratio and subthreshold slope as a function ofgate dielectric constant (from SiO2 with K = 3.9 to TiO2 withK = 80) for JLTFET and MOSFET with gate length of 25 nm andNd = 2 × 1019 cm−3

the high-K as gate dielectric [5, 6]. The further improve-ment in different performance parameters could be done bywork function engineering, uses of III–V compound semi-conductor materials as a channel material, proper selectionof source drain extension length with optimized silicon bodythickness. An improvement can also be done by choosingproper isolation thickness between the gates.

The effect of sub-threshold swing and ION/IOFF on thedielectric constant of gate material is studied and resultsare compared for both JLTFET and MOSFET as shown inFig. 10. For our simulation we have considered different di-electric materials (such as TiO2 (k = 80), HfO2 (k = 25),Al2O3 (k = 9), Si3N4 (k = 7.5), SiO2 (k = 3.9)), and the di-electric constants of different materials are taken from [14].It is observed from above figure that the material with higherdielectric constant gives a higher ON current and also an im-proved SS. The improved ION and SS are observed, becauseof a higher gate coupling offered by high-k dielectric gatematerial of higher dielectric constant value ranging from 3.9to 80, keeping the physical thickness of the gate oxide fixedand equal to 2 nm. The ON state current (ION) and OFFstate current (IOFF) are measured at the supply voltages of(VDS = 1 V, VGS = 1 V) and (VDS = 1 V, VGS = 0 V), re-spectively. The highest ION/IOFF for JLTFET is observedat gate dielectric constant of k = 80, taking TiO2 as gate di-electric and the value is approximately 6×1011, whereas forMOSFET with same simulation environment we observedan ION/IOFF of 4.2 × 1011. Looking at the same plot weobserved that with increase of gate dielectric from 3.9 to80, the SS decreases for both the device (in case of JLTFET27 mV/decade at k = 3.9 to 11 mV/decade at k = 80 andfor MOSFET 102 mV/decade at k = 3.9 to 60 mV/decade atk = 80). However from the above results it can be concludedthat, JLTFET with a low k dielectric with k = 3.9 can pro-vide an improved SS of 37 mV/decade which is much lowerthan the SS of MOSFET with a high k dielectric with k = 80(SS = 60 mV/decade).

Fig. 11 Effect of SS and DIBL as a function of silicon film thicknessranging from 5 nm to 12 nm, with gate length of 25 nm

3.4 Thin film thickness

Figure 11 shows the effect of silicon film thickness on theshort channel behavior of JLTFET and MOSFET in termsof SS and drain induced barrier lowering. We observed thatwith increase of silicon thickness from 5 nm to 12 nmboth SS and DIBL increase, but interestingly JLTFET atTsi = 12 nm offers an improved SS and lower DIBL thanMOSFET with layer thickness of 5 nm, which signifies theshort channel integrity and superior performance of JLTFETover conventional MOSFET. With increase of Tsi from 5 nmto 12 nm, sub-threshold swing of JLTFET increases from24 mV/decade to 56 mV/decade (below the theoretical limitof MOSFET) and DIBL from 30 mV/V to 98 mV/V respec-tively. Whereas observing the same behavior of MOSFET, itcan be concluded that at higher silicon thickness the MOS-FET has a very poor short-channel performance as com-pared to JLTFET.

3.5 Effect of temperature variations

Figure 12 shows the dependence of OFF state current withvariation of temperature. We have studied the behavior ofJLTFET and MOSFET for temperature values of 243 K,300 K and 393 K. With increase of temperature OFF cur-rent increases to significant amount due to shift in thresh-old voltages of the device. When temp rises from 300 K to393 K there is difference in OFF current of more than twoorders in magnitude is observed for MOSFET, whereas incase of JLTFET the temp rise affects the OFF current byincreasing its value to one order in magnitude as shown inFig. 12. So JLTFET has better temperature stability in nano-scale regime than conventional MOSFET.

The variation of sub-threshold slope with temperature in-stability is shown in Fig. 13. It is clear from the picturethat with increase in temperature SS increases, which de-grades the switching behavior of both the devices. It can beconcluded that JLTFET has better temperature stability than

J Comput Electron

Fig. 12 Comparative study of OFF state behavior of JLTFET andMOSFET with variation of device temperature with gate length of25 nm, Tox = 2 nm, Tsi = 5 nm and Nd = 2 × 1019 cm−3

Fig. 13 Sub-threshold slope as a function of variation of temperatureranging from 243 K to 393 K

that of conventional MOSFET. This can be demonstrated bylooking at the change in SS of both the devices. (For JLTFETat temperature of 243 K, SS = 9 mV/decade is observedwhich further increases to 36 mV/decade with increase indevice temperature to 393 K. But in case of MOSFET SSof 64 mV/decade is observed even at lower temperature of243 K which increases to 93 mV/decade at further increasesin temperature to 393 K.) So the short channel performanceof JLTFET is more stable towards the temperature variationas compared to metal oxide FET.

4 Conclusion

In this paper the short channel performance of both JLT-FET and MOSFET are compared. By doing extensive sim-ulations it can be concluded that in deep deca-nanometer(sub-30 nm) region JLTFET offers improved performancein terms of very low subthreshold swing and high ION/IOFF

ratio as compared to conventional MOSFET. The JLTFET isless sensitive to temperature variation as compared to con-ventional MOSFET. Moreover JLTFET would be simpler tofabricate and less prone to variability and short channel ef-fect than conventional MOSFET. So JLTEFT can be a futuredevice for many applications, which offers combined advan-tages of both TFET and JLFET without need of any sharpdoping gradient.

Acknowledgement The authors thank the University of Texas atAustin, USA, and the Ministry of Human Resource and Development,Government of India, for funding this project.

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