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aDepartment of Electrical Engineering, India

208016, India. E-mail: pranavasthan32@gmbMicroelectronics Research Center, Universit

Bldg. 160, Austin, TX, 78758, USA. E-mail:

Cite this: RSC Adv., 2014, 4, 22803

Received 19th January 2014Accepted 5th March 2014

DOI: 10.1039/c4ra00538d

www.rsc.org/advances

This journal is © The Royal Society of C

Optimal design for a high performance H-JLTFETusing HfO2 as a gate dielectric for ultra low powerapplications

Pranav Kumar Asthana,*a Bahniman Ghosh,ab Shiromani Bal Mukund Rahia

and Yogesh Goswamia

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor

(TFET) using HfO2 as a gate dielectric. The device principle and performance are investigated using a 2D

simulator. During this work, we investigated the transfer characteristics, output characteristics,

transconductance, Gm, output conductance, GD, and C–V characteristics of our proposed device.

Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in ION of �0.23

mA mm�1, IOFF of �2.2 � 10�17 A mm�1, ION/IOFF of �1013, sub-threshold slope (SS) of �12 mV dec�1,

DIBL of �93 mV V�1 and Vth of x0.11 V at room temperature and VDD of 0.7 V. This indicates that the

H-JLTFET can play an important role in the further development of low power switching applications.

I. Introduction

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)present several challenges for sub-20 nm technology because oftheir steep doping proles at source and drain junctions.Junctionless FETs provide a solution to this problem as they donot have doping junctions.1–3 They are also suited for high speedapplications but their high subthreshold swing, as in Comple-mentary Metal Oxide Semiconductors (CMOS), makes thempower consuming devices. TFETs have received attention forlow power applications because of their low subthresholdswing.4–7 However, the low ON current hinders them frommanyother high speed applications. Now, Junctionless Tunnel FETs(JLTFETs) are the subject of intensive studies in device researchas they have a low subthreshold swing along with a higher ONcurrent, giving a better speed.8,9 This device structure utilizesquantum tunneling using a charge plasma concept. Addition-ally, it does not have any doping junctions. It has establisheditself as one of the most promising candidates for future logiccircuits, which operate at supply voltages smaller than 0.5 V.Moreover, the process budget is reduced because of the junc-tionless channel. Also, JLTFETs show better electrical perfor-mance and less variability thanMOSFETs10 because there are nop–n junctions. In this paper we proposed and investigated a newstructure, a H-JLTFET. This structure takes advantage of dualmaterial channels causing higher tunneling in an ON state andreduced tunneling in an OFF state. As a result, there is a drastic

n Institute of Technology Kanpur, Kanpur

ail.com

y of Texas at Austin, 10100, Burnet Road,

bghosh@utexas.edu

hemistry 2014

improvement in performance. We have optimized our devicestructure using Silvaco TCAD Atlas 2D.

II. Device structure and parameters

Fig. 1 shows the proposed device structure of the Si:Ge hetero-junctionless tunnel eld effect transistors. An n+ Poly Gate and ap+ Poly Source are used to provide an appropriate work functiondifference between the gate and channel for the creation of p–i–nregions. The lower band gap material germanium on the sourceside causes higher tunneling in the ON state, while drain sidetunnelling weakens because of the higher band gap material,silicon. There are many reports indicating successful attemptsto fabricate Si and Ge interfaces.10,11 The parameters used in oursimulations for Si:Ge H-JLTFET are: gate length ¼ 20 nm, gatedielectric, HfO2 thickness (Tox)¼ 2 nm, Si:Ge lm thickness (Tsi)¼ 5 nm, low-k spacer thickness ¼ 2 nm, work function of thepoly n+ region of the gate ¼ 4.2 eV, work function of the poly

Fig. 1 Cross sectional view of the device structure of the Si:Ge hetero-junctionless tunnel field effect transistor.

RSC Adv., 2014, 4, 22803–22807 | 22803

Fig. 3 Electron and hole concentration profiles of the H-JLTFET asa function of the position along the x-direction in (a) the ON state(VDS ¼ 0.7 V, VGS ¼ 0.7 V) and (b) OFF state (VDS ¼ 0.7 V, VGS ¼ 0 V) atthe channel and HfO2 interface.

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p+ region of the gate¼ 5.3 eV, supply voltage ¼ 0.7 V and carrierconcentration in the uniformly doped channelND¼ 1.0� 1018 cm�3.The Si-TFET has the same parameters as Si:Ge H-JLTFET exceptfor the channel with doping junctions, with a channel regiondoping concentration of 1016 cm�3 and source/drain dopingconcentration of 1018 cm�3. Similarly, the Si-JLTEFT has thesame parameters, except a Si channel is used instead of a Si:Geinterface.

Fig. 2 shows the valence and conduction band energyproles along the x-direction at the channel and HfO2 interfaceof the H-JLTFET shown in Fig. 1. It is observed that, in the OFFstate, the tunneling barrier is too large, which causes a negli-gible tunneling probability of electrons. In the OFF state, only asmall leakage current ows in the device. Fig. 3 shows theelectron and hole charge concentration proles along the x-direction at the channel and HfO2 interface of the H-JLTFET.From Fig. 3, it is observed that on applying the gate voltage onthe control gate (named gate in our proposed structure, asshown in Fig. 1), the electron concentration beneath this gateincreases. This result shows that the applied gate voltage causeslowering of the tunneling barrier between the source andchannel. For a tunnel FET, it is found that the ON currentincreases exponentially with a decrease of the tunnelingbarrier.11 From Fig. 2, it can be noted that in the ON state, thebarrier width is sufficiently lowered, causing an increase in thetunneling probability of electrons from the valence band to theconduction band, resulting in sufficient current ow in thedevice. Further use of a high-k gate dielectric material, HfO2,improves the gate control and hence the ON current andsubthreshold slope. All simulations are done using SILVACOATLAS 2D V5.15.32 R soware.12 A dri-diffusion currenttransport model, Lombardi mobility model and SRH recombi-nation model are used for simulations.12,13 Apart from that, aBand Gap Narrowing (BGN) model is used because of the highlydoped channel,14 and a non-local band to band tunnelingmodelis used to study the effect of tunneling.12 For further accuracy,

Fig. 2 Energy band diagrams taken horizontally across the channel ofthe hetero-structure bulk junctionless tunnel FET, in the ON state(VDS ¼ 0.7 V, VGS ¼ 0.7 V) and OFF state (VDS ¼ 0.7 V, VGS ¼ 0 V) alongthe x-direction at the channel and HfO2 interface for the H-JLTFET.

22804 | RSC Adv., 2014, 4, 22803–22807

Schenk’s Trap Assisted Tunneling (TAT) model and QuantumConnement (QC) model are incorporated.12,15 Grid points arekept at 0.2 nm spacing in the x-direction and at 0.5 nm spacingin y-direction.

III. Results and discussions

Fig. 4 shows a comparison of the ID–VG characteristics of ourproposed device with the Si-JLTFET and Si-TFET with the samedimensional parameters. It can be observed that the proposeddevice has much better device characteristics than the othertwo. Further, ION, of 0.23 mA mm�1, 0.82 mA mm�1 and 0.08 mAmm�1; IOFF, of 2.2 � 10�17 A mm�1, 1.9 � 10�14 A mm�1 and1.6 � 10�15 A mm�1; ION/IOFF, of 10

13, 4.3 � 107 and 5 � 107 areobserved for the H-JLTFET, JLTFET and TFET, respectively. TheTFET has a lower OFF state current than the JLTFET, as theJLTFET has no physical junction but rather junctions created bycharge plasma concept. However, the ON state current of theJLTFET is much higher than the TFET because of the inheri-tance of a junctionless FET. TFET and junctionless FET blended

Fig. 4 Comparison of the transfer characteristics of the Si-TFET,Si-JLTFET and Si:Ge H-JLTFET with the same dimensional parameters.

This journal is © The Royal Society of Chemistry 2014

Fig. 6 Output characteristics at VGS from 0.1 to 0.7 V for theH-JLTFET.

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JLTFETs have signicantly higher ION/IOFF than the TFET. TheSi:Ge hetero-structure tremendously improves performance incomparison to the JLTFET, due to the increased band to bandtunneling on the source side in the ON state. Fig. 4 clearlydepicts that from the subthreshold slope to the ON and OFFstate currents, the H-JLTFET has enhanced device characteris-tics. Transfer characteristics of the proposed device are shownin Fig. 5 for different drain voltages. This gure also indicatesthe drain induced barrier lowering which is highly suppressed.‘X’ On Insulator (XOI) and junctionless FETs with highlycontrolled tunneling employing hetero-structures at very lowvoltages are the reason for the highly suppressed drain inducedbarrier lowering (DIBL). This result shows that our device workswell for a wide range of applied voltages from 0.0 V to 0.7 V.DIBL is calculated from the following formula16

DIBL ¼ VthVDS¼0:7V� VthVDS¼0:05V

VDS¼0:7V � VDS¼0:05V

(1)

where VthVDS¼0:7V is the threshold voltage at VDS ¼ 0.7 V. The H-JLTFET has a DIBL of 73 mV V�1. Also, a subthreshold slope of12 mV per decade is calculated for VDS ¼ 0.7 V and VGS ¼ 0.7 Vusing the following formula

Average subthreshold slope ðSSÞ ¼ Vth � Vref

logIth

Iref

: (2)

The International Technology Roadmap for Semiconductors(IRTS) made predictions in 2013 that 22 nm High Performance(HP) will have ION of 2.2 mA mm�1 and IOFF of 0.37 mA mm�1,while 22 nm Low standby Power (LSTP) will have ION of 0.5 mAmm�1 and IOFF of 2 � 10�11 mA mm�1.17,18 Clearly, the H-JLTFETsurpasses both limits of both technologies.

The output characteristics of the H-JLTFET for VGS rangingfrom 0.1 V to 0.7 V are shown in Fig. 6. We observed an expo-nential increase in the drain current with increasing gatevoltage, demonstrating better gate control. Also, the saturationregion is atter, indicating negligible channel length

Fig. 5 Drain current versus gate voltage for the H-JLTFET at VDS from0.05 V to 0.7 V.

This journal is © The Royal Society of Chemistry 2014

modulation. Besides, other short channel effects reportedpreviously, especially the kink effect, are highly suppressed.19,20

Fig. 7 shows transconductance as a function of gate voltage forVDS ranging from 0.05 V to 0.7 V. The transconductanceobtained for the gate voltage resembles the conventional curveat lower gate voltages. However, deviation is observed forhigher values of gate voltage, as tunneling is a nonlinearphenomena and depends on the orientations of the band

structure. Similarly, output conductance,�GD ¼ vID

vVDS

�char-

acteristics are compiled in Fig. 7 for VGS ranging from 0.1 to 0.7V. A hump is observed in GD around VGS/2 due to Drain InducedTunneling (DIT). At high VGS and low VDS, a small increase inVDS causes more tunneling. Hence, the drain voltage mimics thebehaviour of the gate voltage at low VDS, but for VDS > VGS/2 DITfades as the rate of tunneling decreases and hence trans-conductance follows conventional behaviour aerwards (Fig. 8).

Fig. 9(a) and (b) show a comparison of the gate-to-drain andgate-to-source capacitance, respectively, for the H-JLTFET andJLTFET as a function of the gate voltage at a drain voltage of

Fig. 7 Transconductance, Gm versus gate voltage for the H-JLTFET atVDS from 0.05 V to 0.7 V.

RSC Adv., 2014, 4, 22803–22807 | 22805

Fig. 8 Drain conductance, GD vs. VDS at VGS from 0.1 to 0.7 V for theH-JLTFET.

Fig. 9 Variation of (a) gate-to-drain capacitance, CGD and (b) gate-to-source capacitance, CGS, with a gate voltage at VDS ¼ 0.7 V, frequency¼ 106 Hz and vss ¼ 0.01 V for the H-JLTFET.

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0.7 V, with a frequency of 1 MHz and a small signal voltage of0.01 V. The JLTFET provides a gate-to-drain/source capacitancethat is a little lower than the H-JLTFET at higher gate voltages.

22806 | RSC Adv., 2014, 4, 22803–22807

IV. Conclusions

In this work, we proposed an optimal design of a Hetero-Junc-tionless Tunnel Field Effect Transistor (H-JLTFET) using HfO2

as a gate dielectric and discussed its static operation. Throughsimulation, we also studied the characteristics of the H-JLTFET,especially for switching applications. The device provides highspeed operation even at very low supply voltages, with lowleakage and a reduced number of steps in the fabricationprocess, which indicates that the H-JLTFET is a promisingcandidate for switching performance. In addition, it has thepotential for further scalability.

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