ISSN: 2278 International Journal of Advanced …ijarece.org/wp-content/uploads/2015/05/IJARECE-VOL-4...BMS College of Engineering Swathi M is from the Department of Electronics and

ISSN: 2278 – 909X

International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 4, Issue 5, May 2015

1225 All Rights Reserved © 2015 IJARECE

Abstract—This paper presents an overview of the design and

development of an FPGA-based implementation of the Advanced

Encryption Standard (AES) algorithm. We live in an age where

digital data, and its security, are of prime importance. Just as the

complexity of networks and data transmission methods grows, so

also the rise in incidence of digital crimes and the increase in

complexities of network security attack methods.

Given the rapid evolution of attack methods and toolkits,

software-based solutions to secure the network infrastructure

have become overburdened. Therefore, the use of hardware

implementations for securing the network infrastructure has been

considered.

Field Programmable Gate Array (FPGA) devices have commonly

been proposed for this purpose because they feature both the

flexibility of software and the high performance of hardware. In

this paper, we present an overview of our project, in which we

implemented a complex encryption algorithm, the AES, on an

FPGA and compared it with its software implementation.

Index Terms—Hardware implementation, AES, FPGA,

execution time.

I. INTRODUCTION

RUCE SCHNEIER SAID IT RIGHT. “Hardware is easy to

protect: lock it in a room, chain it to a desk, or buy a

spare. Information poses more of a problem. It can exist

in more than one place; be transported halfway across the

planet in seconds; and be stolen without your knowledge!”

We live in a digital world. A world where more than 700TB of

data is transferred every minute. A world where digital

communication is far more prevalent than face-to-face

communication. A world where our professional and personal

lives are becoming increasingly dependent on technology.

Thus, today, information security is the most important

buzzword. It is unimaginable to think of transmitting data as-

is. There is a need to ensure the confidentiality of data, to

guarantee its authenticity and to protect systems from

network-based attacks such as viruses and hacking. In this

regard, a number of encryption & decryption algorithms have

been developed.

Anupama Gopalan is from the Department of Electronics and Communication, BMS College of Engineering.

Janani Ganesh is from the Department of Electronics and Communication,

BMS College of Engineering Swathi M is from the Department of Electronics and Communication, BMS

College of Engineering.

Indeed, these algorithms, their development and application

are part of a profession by themselves. The field of network

security is growing at a fast pace, and has great scope.

However, thereal challenge is not only to make these

algorithms fool-proof, but also to increase their speed of

computation. If the time taken to encrypt my data securely is

as much as the time taken to process or transfer it; the very

point of time criticalness in real-world communication is lost!

Also, the cost of implementing the encryption and decryption

algorithms must be very small, in order to improve efficiency.

Thus, the need of the hour is to make these algorithms fast,

flexible, and low-cost; in a range of applications such as

embedded hardware. It would be quite ridiculous to use an

implementation that takes up the maximum part of the total

execution time of my application. Equally absurd would be the

use of an implementation that is so rigid that a lot of effort has

to be put in to make changes in it for every small modification

in my application. Similarly, it would make no sense to use an

implementation that places a lot of burden on the main

processor, as the overall efficiency of the application or

process would reduce only because of the security algorithm,

which is only a part of the total process.

Recent research has shown that the use of reconfigurable

hardware for the implementation of these algorithms would

improve speed, throughput and efficiency. Chen et al. [1] have

averred that the traditional software-based solutions to

information security attacks have become overburdened.

Today, hardware implementation of security functions

shows more promise. Traditional network intrusion detection

systems (NIDS) are inefficient and do not perform well in the

face of the constantly increasing speed of the Internet. Li et

al. [2] have proposed that the use of reconfigurable hardware

for detection of intrusions would improve the network security

system. The performance-gap between the execution speed of

security software and the sheer amount of data to be processed

is widening, and this is a serious issue. Thus, to address this, it

is critical to start implementing hardware solutions in

environments requiring high security.

Advanced cryptographic techniques, such as hash functions

and message authentication codes, are now being used in

modern systems dealing with storage and manipulation of

sensitive data. A study by Nickolas and Sivasankar [3] has

asserted that such algorithms are far too demanding to be

implemented in software for the processing speeds expected

today in an embedded system. Therefore, hardware

FPGA-based Message Encryption and

Decryption

Anupama Gopalan, Janani Ganesh and Swathi.M

B

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components have to be used to realize the same in an efficient

manner.

In particular, implementation on FPGAs is gaining traction in

the industry. An FPGA (Field-Programmable Gate Array) is

basically a reprogrammable semiconductor device; i.e. its

features and functions can be programmed, and its hardware

reconfigured, even after it has been manufactured. FPGAs

consist of programmable logic components called „logic

blocks‟, which perform complex combinational functions and

include memory devices.

An FPGA can implement any logical function that an ASIC

can, with the added advantage of being able to re-program it

even after its release into the market as a product. An FPGA is

specified using a Hardware Description Language (HDL).

FPGAs have quickly become very popular for use in a myriad

of applications ranging from automotive to telecom to

networking. As stated earlier, their ability to be re-

programmed makes them highly attractive to users.

An article by Villasenor et al. [4] states that current FPGAs

can be reconfigured within a millisecond, and ultimately, they

will be able to adapt themselves almost continuously –

meaning, they can be reprogrammed every 10-3

s (or less).This

makes them highly suitable for building encryption systems,

and implementing algorithms such as the DES, AES, and hash

functions with higher speed and efficiency.

This paper is concerned with the implementation of the AES

(Advanced Encryption Standard) algorithm on an FPGA. The

AES, developed at the start of this millennium to replace the

existing standard, the DES, is used in scores of applications

from the security mechanism of file systems in Windows to

compression tools such as WinZip to disk encryption

algorithms to the Linux kernel‟s Crypto API.

Another major application of the AES is in the security

mechanism of the new IEEE standard 802.11i (set to replace

the current standard, 802.11 WEP, quite soon), known as

„CCM Mode Encryption‟. This security system spends most of

the computation power in performing the AES algorithm. A

paper by Vu and Zier [5] has shown that the use of an FPGA

to implement the AES would largely speed up the process.

Their study proves that ultimately, communication rates could

be increased and both security as well as speed improved, by

this technique. Further, Satoh et al. [6] have written that an

„authenticated encryption system‟ (one of the newest security

concepts), when implemented on an FPGA, would generate a

higher throughput.

A review paper by Tonde and Dhande [7] lucidly sums up the

literature surveyed. An example of a very high-security

application, electronic transactions, has been taken. An FPGA-

based implementation of the AES is clearly shown as having a

number of advantages, including ease of algorithm

modification based on the application, architecture efficiency,

higher throughput, low latency and cost efficiency.

Besides providing security for the textual data we work with

every day, multimedia data security is quickly emerging as a

crucial aspect of this domain. This is owing to the steadily

increasing use of digital images and videos in our day-to-day

communications. Kotel et al. [8] have affirmed that

multimedia encryption algorithms implemented on FPGAs

have emerged as the most viable solution, and the most

worthwhile due to the efficiency of computation.

At the same time, the necessity to encrypt speech is growing,

especially in environments where all communications,

whether they are text-based or speech-based, are classified

information. Hussain et al. [9] have stated that, once again, the

use of FPGAs is highly recommended for speech encryption.

One of the possible approaches to this would be by employing

speech-to-text conversion and vice-versa, by interfacing an

ADC and a DAC respectively to the FPGA.

The aim of this project, and this paper documenting the

findings of the project, is to study the advantages of

implementing a complex encryption algorithm, such

Advanced Encryption Standard (AES) in an FPGA design;

and assessing the improvements in speed and cost as

compared to a software implementation. The most important

application would be in any environment requiring high

security, such as the military, defence organisations or a

scientific laboratory.

II. THE AES ALGORITHM

The work on this project began with a study of the field of

cryptography. In very basic terms, it is the art and science of

securing data, by encryption of the data by the sender, so that

no interceptor can understand the message as it is being

transmitted. At the receiving end, the receiver must decrypt

the „cipher text‟ he receives in order to get back the „plain

text‟, i.e. the original information. In order that only the

correct receiver obtains the message, cryptographic keys are

used. These keys must remain secret, i.e. they must be known

only to the legitimate sender and receiver. The algorithms

used for encryption and decryption may be „symmetric-key‟

(same secret factor, or key, used for both encrypting and

decrypting) or „asymmetric-key‟ (a pair of keys is used by

both parties – one is public; used for encryption or

confirmation of authenticity; the other is private; used for

decryption or creation of an authenticity stamp. The keys are

linked by a mathematical function).

We started off by learning about one of the most popular

modern cryptographic algorithms, the Data Encryption

Standard (DES) Algorithm. Prominent in the eighties and

nineties, it was certainly the most prevalent symmetric-key

algorithm used for the encryption of electronic data. However,

owing to several limitations (such as small key size and

gradually, ease of breaking), it was replaced by the Advanced

Encryption Standard (AES) algorithm, standardized in 2001.

The AES is based on the Rijndael cipher, developed by John

Daemen and Vincent Rijmen. It is a block cipher, which

means that data is processed in the form of blocks of fixed

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size. For AES, the block is fixed at 128 bits, but there are three

versions wherein the key may be of length 128 bits, 192 bits or

256 bits and the number of rounds, or cycles of repetition, are

10, 12, or 14. The standard and most popular implementation,

with both block and key lengths of 128 bits, i.e. 16 bytes, and

of 10 rounds, is taken up here. Being a private-key, or

symmetric-key, algorithm; the key is shared only between the

sender and the receiver. The AES is a federal government

standard in the United States, and is now used worldwide for

securing secret information.

The AES is a substitution-permutation cipher. That is, it is

based on Shannon‟s theory of „confusion and diffusion‟.

According to Shannon, the two main qualities of any

cryptographic algorithm are : Confusion; meaning that the

plain text and the key, as well as the cipher text and the key,

are as different as possible; this reduces the chances of

discovering the key from the plain text or the cipher text; and

confusion is generated by substitutions.

Diffusion; meaning that change in one bit of the plain text

must generate changes in several bits of the cipher text; so that

any correlation between them is reduced, is generated by

performing permutations.

The AES encryption algorithm consists of 4 major stages,

repeated iteratively 10 times as illustrated below. The

procedure for the decryption algorithm is similar to that of

encryption, but in reverse.

Fig. 1: Flow of the AES encryption and decryption

As the first step, the user-inputted plain text of 16 bytes is

arranged in the form of a 4*4 matrix called the state array.

Following this, the user-defined key of 16 bytes, i.e. 4 words,

is expanded into 44 words by a module named Key

Expansion. Thus, 10 round keys are obtained; one for each

round. The original key, referred to as w[0,3] is XORed with

the original plain text byte by byte before the procedure

begins. In case of decryption, the eleventh obtained key,

w[40,43] is XORed with the cipher text at the beginning. Also,

at the end of every round, the corresponding round key is

XORed with the corresponding state array at that stage. This

module is named AddRoundKey.

In each round, the first step is named SubBytes (substitute

bytes), wherein each byte of the 4*4 state array is substituted

by a byte from the Rijndael S-Box (a universally defined

lookup table), using the higher nybble of the input byte as row

indicator and the lower nybble as the column indicator.

For example, if a byte of the state array is 6B, it is substituted

for the byte of the S-Box in row number 6 and column number

B.

For decryption, the step InvSubBytes is similar but the

Inverse- S-Box is used for substitution.

This substitution step generates confusion.

Next, the step ShiftRows is performed, in which the rows of

the state array are shifted cyclically to generate diffusion.

The first row is left unchanged, the second shifted by 1 to the

left, the third by 2 and the fourth by 3.

For decryption, InvShiftRows is similar except that the shift

is to the right.

The next step is MixColumns, in which the four bytes in each

column of the state array are combined using an invariable

linear transformation. The decryption step of InvMixColumns

is also similar.

As each input byte affects all four output bytes, this achieves

further diffusion.

During decryption, the steps explained above are executed in a

different order –InvShiftRows, InvSubBytes, AddRoundKey

and InvMixColumns. Hence, though the steps of decryption

are similar to those of encryption, the algorithm is different

and requires a different design.

The last, i.e. 10th round of encryption is special, in that the

step MixColumns is omitted. In case of decryption, the step

InvMixColumns is omitted in the last round. Thus, it is

necessary to define a variable to indicate if the current round is

the last round or not.

The user inputs a single 16 byte, or 4-word key. However, as

explained, the AES algorithm requires that each round use a

different key. Thus, the initial 4 words must be expanded to 44

words, i.e. a distinct key for each of the 10 rounds. This is

achieved by the module named Key Expansion.

If the 4 words of the ith round are wi, wi+1, wi+2, andwi+3, then

these are used to derive the 4 words of the (i+1)th round as

follows:

wi+5 = wi+4 ⊗ wi+1

wi+6 = wi+5 ⊗ wi+2

wi+7 = wi+6 ⊗ wi+3

The first word of this grouping, i.e. wi+4, is obtained from the

first word of the last grouping, XORed with what is returned

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by applying a function g() to the last word of the last grouping,

as follows:

wi+4 = wi⊗ g(wi+3)

And the function g() is defined as:

a. Perform a one-byte left circular rotation on the argument

4-byte word.

b. Perform a byte substitution for each byte of the word

returned by the previous step by using the same 16 × 16

lookup table as used in the SubBytes step of the

encryption rounds.

c. XOR the bytes obtained from the previous step with the

round constant of the ith round, Rcon[i].

Rcon[i] is a 4-byte value whose rightmost 3 bytes are always

0. That is, Rcon[i] = (RC[i], 0, 0, 0).

Its highest byte, RC[i] is defined as follows:

RC[1] = 0x01

RC[j] = 0x02 x RC[j-1]

A standard C++ implementation of the AES encryption and

decryption was carried out using Microsoft Visual Studio

Express 2013 on a laptop with Intel i5 processor. A hex input

of 16 bytes was given as plain text and another hex input of 16

bytes was chosen as the key. The correct cipher text output

block was obtained. A small code snippet written to measure

the execution time calculated the same as 16 milliseconds for

encryption and the same for decryption. This value will

certainly differ on different hardware platforms based on the

processor speed, but the inference drawn was that the

execution time in software is of the order of milliseconds.

Fig. 2: Calculated execution time of encryption in software

III. HARDWARE DESIGN

The hardware design of the algorithm was carried out in the

VHDL language, using the XilinxXC6SLX16 device.

The design for encryption is illustrated below.

Fig. 3: Controller block of the design for encryption

Fig. 4: FSM of the design for encryption

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Fig. 5: Hardware architecture of the design for encryption

As depicted in the figures, inputs to the design are the plain

text block, the key, rst and the clk. A signal text_key_sel is

used to determine if the input at a time instant is the plain text

or the key. In fact, text_key_sel is the select line of a 2x1

MUX. When it is 0, the user-inputted key is loaded and

load_key is set to 1. When text_key_sel is 1, the data, i.e. the

original plain text is loaded and load_data1 is set to 1.When

the 2-bit variable sel_data is 00, the original plain text is

XORed with the original key, w[0,3] before the start of the

first round. Following this, the 4 steps SubBytes, ShiftRows,

MixColumns and AddRoundKey of round 1 are executed as

explained in the previous section.

Following this, the rounds 2 to 9 are executed with the 4 steps

described earlier. The 10th round of encryption is special in

that the step MixColumns is omitted. Thus, another signal

last_rnd is used and set to 1 when round 10 commences. It is

in fact a select line of another 2x1 MUX. When it is 1, the

MixColumns step is sidestepped and the output of the last

ShiftRows is fed to the AddRoundKey block.

Another signal, eoc is used to indicate the completion of the

process. It is the select line of yet another 2x1 MUX. When 1,

it indicates that conversion is completed and thus the obtained

output is the final cipher text.

The design of the module for key expansionis illustrated

below. As has been expounded, this module is an integral part

of the encryption and decryption algorithms.

The design for decryption requires a separate key expansion

design. This is because the order in which the keys are used is

reversed during decryption, i.e., the cipher text is first XORed

with the last round key, w[40,43] from the key expansion

before going through the first round substitutions. The

AddRoundKey step of the first round uses the last but one key

from the key expansion and so on.

Fig. 6: Hardware architecture of the design for key expansion

Fig. 7: FSM of the design for key expansion

This key expansion module for decryption is used to obtain

the last round key after 10 cycles.

From the last round key, the other keys can be obtained using

an“on the fly” method.

The design of the module for decryption is illustrated below.

As has been explained earlier, although the steps of decryption

are similar to those of encryption, they are executed in a

different order. Thus, the decryption algorithm is substantially

different from the encryption algorithm.

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Fig. 8: Controller block of the design for decryption

Fig. 9: FSM of the design for decryption

Fig. 10: Hardware architecture of the design for decryption

As depicted in the figures, a signal decrypt is used to indicate

that the algorithm for decryption is running. This is required as

a separate key expansion module is used for decryption, as

explicated previously. During the decryption process, the last

round key, w[40,43] is XORed with the cipher text before the

start of the first round.In the wait state, the data, i.e. the cipher

text block is loaded and load_data set to 1. The signal rnd_1

indicates that the first round is being executed.The four steps

InvShiftRows, InvSubBytes, AddRoundKey and

InvMixColumns are executed as described in the previous

section. Following this, the rounds 2 to 9 are also run in a

similar fashion. For the last round, the InvMixColumns step is

bypassed. Once eoc is set to 1, the conversion is complete and

the original plain text block is obtained as the final output.

IV. SIMULATION AND SYNTHESIS

The tool used for simulation and synthesis of the VHDL

modules was Xilinx ISE 13.2.

Modular testing was carried out to ensure the correctness of

the various modules of the project. Finally, the entire code was

subjected to a behavioral simulation. Following the modular

testing, top-level testing was carried out and the results are as

follows.

Fig. 11: Result of simulation of the encryption top module

Fig. 12: Result of simulation of the decryption top module

After obtaining the expected results in simulation, the FPGA

was programmed with the written VHDL code using the tool

„iMPACT‟.We used the device XC6SLX16.

The inputs were hard-codedand the synthesis carried out. The

outputs, cipher text in the case of encryption and plain text in

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the case of decryption, were obtained as expected. A picture of

the project setup follows.

Fig. 13: Project setup

V. RESULTS, CONCLUSIONS AND FUTURE WORK

As stated earlier, based on our implementation of the AES in

C++, we could conclude that the execution time in software is

of the order of milliseconds.

Following this, as described earlier, The AES RTL Code was

downloaded onto the FPGA board. The user clock speed is

100MHz.

The AES Encryption module took 10 clock cycles to execute.

Hence, it took a total of 10/100MHz i.e., 100nsfor execution.

On the other hand, the Decryption algorithm has an initial

overhead of 11 clock cycles which consumes another 110ns.

The computation of plain text takes 10 cycles and thereby an

execution time of 10/100MHz which is another 100ns.

Thus, the execution time in hardware is of the order of

nanoseconds.

The throughput and latency of our design are tabulated below.

The value of throughput is calculated, as defined by Zambreno

et al.[16], as follows:

T = (128-fclk)/blocks_per_cycle

The value of latency is calculated as follows:

Lat = (10 * stages_per_round)/fclk

For encryption:

Target FPGA device XC6SLX16 [100 MHz

Clock frequency]

Encryption Throughput 1.280 Gbps*

Timing report

Speed Grade -3

Max Frequency 154.434 Mhz

Min period 6.475ns

Min. input arrival time

before clock

3.543ns

Max. output required time

after clock

7.049ns

Device Utilization

Number of Slice LUTs 2395/9112 [26%]

Number of occupied slices 895/2278 [39%]

Number of fully used LUT-

FF pairs

2430

For decryption:

Target FPGA device XC6SLX16 [100 MHz

Clock frequency]

Decryption Throughput 1.280 Gbps*

Timing Report

Speed Grade -3

Max Frequency 173.854 MHz

Min period 5.752ns

Min. input arrival time

before clock

7.049ns

Max. output required time

after clock

8.653ns

Device Utilization

Number of Slice LUTs 1853/9112 [20%]

Number of occupied slices 620/2278 [27%]

Number of fully used LUT-

FF pairs

1921

*implies after overhead.

The above work and its obtained result thus concluded that the

speed of execution of a complex security algorithm such as the

AES on hardware is much higher than in software.

Therefore, it is clearly a viable and worthwhile option to use

reconfigurable hardware for the implementation of security

algorithms, rather than using a slower software

implementation that increases the burden on the main

processor, thereby reducing its efficiency.

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Future work would involve testing the same on various other

boards, and making a comparative study of speeds and

throughputs. Post that, it is our intention to implement the

same for the encryption of other forms of communication,

such as speech and videos, as this is of increasing importance

in an age where multimedia communication is steadily gaining

prevalence and prominence.

VI. ACKNOWLEDGEMENT

We would like to thank our guide, Dr. K.P. Lakshmi, and our

Head of the Department, Dr. D. Seshachalam, for having

given us the opportunity to work on such a project, the chance

to write this paper, and for their constant support and

encouragement.

V. REFERENCES

[1] Hao Chen, Yu Chen, Douglas H. Summerville, “A

Survey on the Application of FPGAs for Network

Infrastructure Security,” IEEE Communications Surveys and

Tutorials, 2010.

[2] Shaomeng Li, Jim Torresen, Oddvar Sørasen,

“Improving a Network Security System by Reconfigurable

Hardware,” Department of Informatics, University of Oslo,

Norway, 2004.

[3] Deepthi Barbara Nickolas, Mr. A. Sivasankar, “Design of

FPGA Based Encryption Algorithm using KECCAK Hashing

Functions,” International Journal of Engineering Trends and

Technology (IJETT), Vol. 4, Issue 6, June 2013.

[4] John Villasenor, William H. Mangione-Smith,

“Configurable Computing,” Department of Electrical

Engineering, University of California, Los Angles, 1999.

[5] Khoa Vu, David Zier, “FPGA Implementation AES for

CCM Mode Encryption Using Xilinx Spartan-II,” Advanced

Cryptography, Oregon State University, Spring2003.

[6] Hori Y., Satoh A., Sakane H., Toda K., “Bit stream

encryption and authentication with AES-GCM in dynamically

reconfigurable systems,” Field Programmable Logic and

Applications, IEEE International Conference, FPL 2008.

[7] Ashwini R. Tonde, Akshay P. Dhande, “Review paper on

FPGA based Implementation of Advanced Encryption

Standard (AES) algorithm,” International Journal of Advanced

Research in Computer and Communication Engineering,

Vol. 3, Issue 1, January 2014.

[8] Sonia Kotel, Medien Zeghid, Adel Baganne, Taoufik

Saidani, Yousef Ibrahim Daradkeh, Tourki Rached, “FPGA-

Based Real-Time Implementation of AES Algorithm for

Video Encryption,” Laboratory of Electronics and

Microelectronics, University of Monastir, Tunisia, 2014.

[9] Hussain Mohammed Dipu Kabir, Saeed Anwar, Abu

Shahadat Md. Ibrahim, Md. Liakot Ali, Md. Abdul Matin,

“Watermark with Fast Encryption for FPGA Based Secured

Real-time Speech Communication,” Consumer Electronics

Times, Vol. 2, Issue 1, Jan. 2013.

[10] Francois-Xavier Standaert, Gael Rouvroy, Jean-Didier

Legat, Jean-Jacques Quisqater, “Compact and Efficient

Encryption/Decryption Module for FPGA Implementation of

the AES Rijndael Very Well Suited for Small Embedded

Applications”, Information Technology: Coding and

Computing, 2004. Proceedings. ITCC 2004, April 2004.

[11] Mohammed Benaissa and Tim Good, “AES on FPGA

from the fastest to the smallest”, ¬Cryptographic Hardware

and Embedded Systems, Sept. 2005.

[12] “ML505/506/507 Overview and Setup - Overview of the

Hardware Designs and Software Applications, How to set up

the equipment, software, CompactFlash, network, and

terminal programs”, Xilinx, Inc, June 2008.

[13] “ML505/506 Quickstart”, Xilinx, Inc, May 2009.

[14] Ashkan Ashrafi and Mark Sison, “Tutorial – Xilinx

Virtex-5 FPGA ML506 Edition”, San Diego State University.

[15] “Virtex-5 FPGA Configuration User Guide”, Xilinx, Inc,

Oct. 2012.

[16] Joseph Zambreno, David Nguyen, and Alok Choudhary,

“Exploring Area/Delay tradeoffs in an AES FPGA

implementation”, Proceedings of the 14th Annual

International Conference on Field-Programmable Logic and

Applications, 2004.

Anupama Gopalan is a final semester student of Electronics

and Communication Engineering at BMS College of

Engineering, Bangalore, India. Her interests include the fields

of embedded systems, network security, and computer

programming.

Janani Ganesh is a final semester student of Electronics and

Communication Engineering at BMS College of Engineering,

Bangalore, India. Her interests include the fields of digital

system design, VHDL coding, and embedded systems.

Swathi M is a final semester student of Electronics and

Communication Engineering at BMS College of Engineering,

Bangalore, India. Her interests include the fields of computer

communication networks, digital system design and embedded

systems.

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