ISSN: 2278 909X International Journal of Advanced Research ...ijarece.org/wp-content/uploads/2015/10/IJARECE-VOL... · Shailendra Mishra,Divya Mishra, R.P. Agarwal Fig.2: Single SWCNT

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)

Volume 4, Issue 10, October 2015

2577 All Rights Reserved © 2015 IJARECE

Abstract— An intentional effort is made to discuss the

circuit-oriented modeling techniques for mSWCNT

bundle interconnects. Based on the models, their

electrical performances have been predicted and

evaluated such as time delay, crosstalk effect, tphl

and tplh, tpdr, tpdf, tpd, tr, tf and average nodal

voltage for both the aggressors. The simulation is

performed strictly to satisfy the diametric conditions

of metallic SWCNT interconnect with three

variations. The lengths are varied with respect to

local, semi-global and global interconnects with

length variations to validate the conclusions drawn.

Index Terms—DIL, scaling factor ‘s’,mSWCNT,

TLM, Interconnects, Time domain analysis, Step

Response, λmfp, Pm , time delay, crosstalk effect, tphl

and tplh, tpdr, tpdf, tpd, tr, tf ,average nodal voltage.

I. INTRODUCTION

Interconnect dimensions are governed by the VLSI

technology scaling factor (s) where„s‟ is an integer

by which the dimensions of interconnects shrinks

down. Primarily, the three main parametric

constituents of the wire that are typically affected

by scaling includes resistance, capacitance and

inductance and concurrently affects the DIL system

[1].Here, scaling factor „s‟ is the pre-factor which

governs the reduction of dimensions such that

𝑠 > 1~1.4 resulting in 1

𝑠= 0.7. As a result,

technology is scaled by a factor of 0.7 every time.

Shailendra Mishra, Department of electronics &

Communication Engineering, Shobhit University, Meerut, India. Divya Mishra, PG.T. Physics, MCPS, Meerut.

Dr. R.P. Agarwal, Academic Advisor,Shobhit University,

Meerut, N.Delhi, India.

A more vivid portrayal of an interconnect system is

depicted in fig.1, while the dimensional aspect of

an isolated mSWCNT over a ground plane is

illustrated in fig.2

The device scaling is obtained attaining high

package density, speed, chip functionality and

power improvements. This assists to obtain reduced

component dimensions resulting the incorporation

of increased number of transistors on to the chip as

mentioned by Gordon Moore in the 1975 IDEM

(International Electron Device Meeting held in

1972).

Interconnect scaling is governed by the following

rules:

1. The linear dimensions such as wire length,

width, thickness, spacing and insulator

thickness are scaled down by the factor „s‟ as

the device.

2. Wire lengths are reduced by factor„s‟ to avoid

discontinuity with the linear dimension of

devices and circuits to which they connect for

maximum power transfer [2].

3. To avoid the disproportional increment of

fringe capacitance and emergence of crosstalk

(wire to wire coupling), both the wire and the

insulator thickness are scaled in accordance to

the lateral dimensions [3].

4. Material parameters such as metal resistivity

ρw and dielectric constant ξins remains

unaffected.

Electrical performance Analysis of Metallic

SWCNT Bundle Interconnects for 22nm

Technology Node Shailendra Mishra,Divya Mishra, R.P. Agarwal

Fig.2: Single SWCNT geometry with one ground

plane with separation between the SWNCT

center and the ground plane (H), SWCNT

diameter (D) and length (L) respectively

[23].

Fig.1: Complete view of Interconnect system

mounted on Si substrate




5. The wire capacitance is also scaled down by

factor„s‟, same as device capacitance while

the wire capacitance p.u.l remains unchanged.

6. In contrary to the device resistance which

remains unchanged, the wire resistance is

scaled up by„s‟. However, the wire resistance

p.u.l. scales up by s2.

7. The current density of interconnect

increments by a factor „s‟ indicating the

emergence of reliability issues such as

electronmigration with scaling down of wire

dimensions, a prominent issue with

conventional interconnect materials such as

Cu and Al.

8. The RC time delay also scales which depend

on the product of resistance p.u.l. and

capacitance p.u.l. of interconnect.

Hence it is realized that, RC delay and

power limitations imposed by the interconnect

system results in poor circuit performance with

dimensions shrink and the overscaling

interconnect on its own, is extremely problematic

because interconnect RC delay

increaseexponentially with scaling [21]. The

concept can be suitably visualized, assisted by the

Applied Materials chart in fig.3.

Resistances increasing faster than the scale

factor of the technology and capacitance

improvements being limited by mechanical

requirements results as limiting factor in both local

and global information transfer on a chip [4].

In reference to the above facts, as we move

towards deep submicron regime number of

interconnections are used to connect millions of

devices increasing wire resistance and giving rise

to propagation delay. Earlier Al & Cu interconnects

were viable enough, but the shrinking of device

dimensions caused these conventional

interconnects to suffer from problems like high

electromigration resistance, surface roughness,

grain boundary scattering, interconnect scaling,

multiple interconnect stacks, leakage power,

support to FinFET etc.

In addition, the prediction made by the

International Technology Roadmap for

Semiconductors (ITRS) suggests a substantial

increment in the width and the maximum current-

carrying density of Cu interconnects to reach 22 nm

and 5.8 × 106 A/cm2 by the year 2020, respectively

[5]. As a result, concerned reliability problems

needs to be addressed appropriately, which

primarily originates due to the Joule heating effect

of the Cu material as there is a significant increase

in its resistivity at the nanoscale [6]. Consequently,

alternate conductive materials with exceedingly

brilliant RF performance need to be opted for

interconnect development in the next-generation,

3D ICs.

Carbon nanotubes (CNTs) offer an attractive

option for VLSI interconnect applications as they

have remarkable electrical, mechanical, thermal

properties and large current-carrying capability due

to their small dimensions [7]–[11]. This novel

interconnect technology has the potential to replace

copper in future. CNTs respectively may exhibit

semi conductive or metallic properties depending

on the geometry and chiral vector. They have long

mean free paths (MFPs) in micrometer range

expressed as:

𝜆𝑚𝑓𝑝 ,𝑖 = 103𝑑𝑖

𝑇

𝑇0 −2

(1)

while, Cu at room temp has mean free path of 40

nm.The resistivity of CNTs is much smaller than

that of Cu in short-length interconnects [12, 13, 14]

and have large current capacities in excess of 1010

A/cm2 [15, 16] can alleviate the reliability problem

caused by electromigration in the Cu interconnects.

Although some challenging technological issues

still are associated with carbon nanomaterials, they

are highly desirable for next-generation

interconnect applications [17]-[19]. However, there

occurs some significant technical barriers for using

CNTs as building blocks in nanoelectronics [20].

Hence, a pragmatic analysis of the same becomes

essential to evaluate their performance.

Fig.3: Gate delay and Interconnect delay vs

technology node.

Source: B. Wu, A. Kumar, Applied

Materials




Physically, they may be single walled

(SWCNT), double walled (DWCNT) or

multiwalled (MWCNT). The present paper intends

to explore the future interconnect applications

operating at RF frequencies considering only the

metallic SWCNTs at local, semiglobal and global

level. Every caution has been considered to the best

of the capability to consider geometrical , physical

and parametric evaluation of metallic SWCNT

bundle interconnect for local, semiglobal and

global architecture.

In this article, circuit-oriented modeling

techniques for mSWCNT interconnect is

introduced first. The crosstalk effect is shown,

based on the circuit models for local, semiglobal

and global interconnects respectively which also

includes diameter and chirality variation. In order

to validate the model considered, other parametric

evaluations are followed to authenticate the

utilization of the model at local, semiglobal and

global levels of interconnect applications.

II. PARAMETRIC CONSIDERATIONS FOR THE

ISOLATED SWCNT MODEL

1. The equivalent circuit model of a single

SWCNT interconnect was first proposed by

Burke [18] bearing quantum resistance RQ at

each end included whose value is independent

of the SWCNT length[22], and it is given by

𝑅𝑄 = 𝑕

4𝑒2𝑁 (2)

where h and e are Planck‟s constant and the

electron charge, respectively. N is the number

of conducting channels, which is equal to 2 for

an isolated, metallic SWCNT. Accordingly,

fig.4 illustrates the interconnect setup with

respect to present simulation.

An excessive delay results for realistic

interconnect applications which may be

avoided considering bundled SWCNTs

connected in parallel for all configurations

such as local, intermediate, and global

interconnects resulting in reduced intrinsic

resistance . As a result, the TL theory has been

extended to bundles of SWCNTs in the

frequency domain.

2. SWCNT Transmission line model of an

Fig.5: Isolated SWCNT as Interconnect with driver and load positioning

Fig.4: Equivalent circuit model of isolated SWCNT interconnect




isolated CNT is modelled as a 1D quantum

wire [22] as shown in fig.5.

3. The interconnect parameters along with

driver and load for SWCNT as interconnect

are represented in fig.6 where driver and

load parameters are technology dependent

[23].

4. Resistive losses also occur at the interface

between the SWNT and the metal in the form

of contact resistance RC leading to current

crowding at the edge of the metal contact

resulting in a nonhomogeneous flow of current

from the SWNT bundle to the metal [24, 25,

26]. Of all the different techniques considering

the process variations in the contact resistance

under various loading thermal annealing

resulting in 40.7±0.7 Ω [27] is the preferred

value of the contact resistance for the

simulation setup presented in the paper.

5. Apart from RC, CNTs with length l > λCNT

have scattering-induced ohmic resistance

expressed as: [22]

𝑅0 = 𝑕

4𝑒2

𝑙

𝜆𝑚𝑓𝑝 (3)

hence, the total resistance exhibited by an

isolated SWCNT is given as

𝑅𝑆𝑊𝐶𝑁𝑇 + 𝑅𝐶 + 𝑅𝑄 + 𝑅0 (4)

6. The transmission line model of an isolated

SWCNT also includes quantum capacitance CQ

Electrostatic capacitance CE, kinetic

inductance LK and mutual inductance LM given

as:

𝐶𝑄 = 2𝑒2

h𝜐𝑓 (5)

𝐶𝐸 = 2𝜋𝜀

ln(𝑠

𝑑) (6) 𝐿𝐾 =

𝑕

2𝑒2𝜐𝑓

(7)

𝐿𝑀 = 𝜇0

2πln(

𝑦

𝑑) (8) The

expressions for CE and LM are technology

dependent. [22]. LM is negligible at higher

frequencies [22].

7. SWCNTs propose to be a good interconnect

material as they are 1D conductors having a

rich variety of low dimensional charge

transport phenomena, including ballistic

conduction, localization and 1D variable range

hopping [28]. The electron mean free

path(𝜆𝑚𝑓𝑝 ), is one of the important length

scales characterizing the different 1D transport

regimes. It has been experimentally confirmed

that𝜆𝑚𝑓𝑝 , is generally much higher for

MWCNTs than for SWCNTs indicating that

the scattering of electrons is strongly

suppressed in MWCNTs as predicted by Ando

et al. [29] and McEuen et al. [30]. The value

for 𝜆𝑚𝑓𝑝 obtained for the present paper is

derived as:

𝜆𝑚𝑓𝑝 ,𝑖 = 103𝑑𝑖

𝑇

𝑇0 −2

(9) Here, 𝜆𝑚𝑓𝑝 ,𝑖

is the mean free path, di the diameter with

respect to the ith shell, To =100K and T=300K

(temperature to be considered for present

simulation)

III. PARAMETRIC CONSIDERATIONS FOR THE

BUNDLE SWCNT MODEL:

The MTL model for the present simulation

considers the following conventions:

1. The SWCNT diameter is taken as d ≤ 2.5 nm

to exclude any possibility of including

MWCNT [31]. For the present paper the

diameters considered for bundled mSWCNT

are 2.16nm, 2.296nm and 2.43 nm condition of

metallic SWCNT as their chirality computes to

be m=n=16,17,18 respectively for armchair

orientation.

2. The length variations of interconnects

considered includes:

(1). 5µm, 8 µm and 9 µm for local

interconnects.

(2). 50 µm, 80 µm and 90 µm for semiglobal

interconnects.

(3). 100 µm, 400 µm and 700 µm for global

interconnects.

3. To form a VLSI interconnect, the CNTs must

be bundled in order to reduce their large

intrinsic resistance. One-third (Pm = 1/3) of

the CNTs are metallic in a bundle. The

remaining two-thirds are semiconducting and

do not contribute to any current conduction

[22]. The concept can be easily visualized in

fig.7 where H, T, S and W represents the

height of the bundle from ground plane,

Fig.6: Equivalent circuit model of isolated SWCNT interconnect




thickness of the bundle and separation between

two bundles and width of the bundle

respectively. The diameter of the isolated

SWCNT is d, Xi the inter CNT distance

between the two adjoining SWCNTs:

D = d+δ (10)

, considering densely packed SWCNT

bundlewhere δ = 0.34nm Vander Waal‟s gap.

4. All the physical dimensions such as width (w),

height (h) separation (s) inter-CNT distance

(D) are considered with respect to 22nm

technology. [32]

5. Considering the above mentioned parametric

values of isolated SWCNT the values of

bundled SWCNT are derived using below

mentioned formulae:

𝑅𝐵𝑢𝑛𝑑𝑙𝑒 = 𝑅𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑

𝑛𝐶𝑁𝑇 (11)

𝐿𝐵𝑢𝑛𝑑𝑙𝑒 = 𝐿𝐾4

𝑃𝑚 𝑛𝐶𝑁𝑇𝑙 (12)

𝐶𝐸𝐵𝑢𝑛𝑑𝑙𝑒 = 2𝐶𝐸 +

𝑛𝐻−2

2 𝐶𝐸𝐹 +

3

5 𝑛𝐻 −

2𝐶𝐸(13)

𝐶𝑄𝐵𝑢𝑛𝑑𝑙𝑒 = 4𝐶𝑄(𝑃𝑚𝑛𝐶𝑁𝑇)𝑙 (14)

𝐶𝐵𝑢𝑛𝑑𝑙𝑒 = 𝐶𝐸𝐵𝑢𝑛𝑑𝑙𝑒 +𝐶𝑄

𝐵𝑢𝑛𝑑𝑙𝑒

𝐶𝐸𝐵𝑢𝑛𝑑𝑙𝑒 ×𝐶𝑄

𝐵𝑢𝑛𝑑𝑙𝑒 (15)

𝑛𝐶𝑁𝑇 = 𝑛𝑊𝑛𝐻 −𝑛𝐻

2 (even number of rows)

(16)

𝑛𝐶𝑁𝑇 = 𝑛𝑊𝑛𝐻 −(𝑛𝐻−1)

2 (odd number of rows)

(17)

𝑛𝐻 = 𝐻−𝑑

3

2×𝑦

+ 1 , 𝑛𝑊 = 𝑤−𝑑

𝑦 (18)

𝐶𝐸𝐹 = 2𝜋𝜀

ln(𝑠+𝑤

𝑑) (19)

The resistance distribution of SWCNT is

quite large which can be reduced by the judicial

implementation of isolated SWCNTs as a compact

bundled interconnects as explained illustratively in

fig.8. and impedance matching is achieved easily as

shown in fig.9. For simple convenience the

interaction between adjacent SWCNTs is neglected

and all SWCNTs in the bundle are assumed to

carry currents independently [34]. Consequently,

effective resistance and inductance of the bundle

can be obtained with respect to the number of

mSWCNT in a bundle. The distributed capacitance

of each SWCNT comprising of quantum and static

values can be obtained using expression stated

above. For the present simulation purpose the

bundle width is chosen to be 22 nm, and the

aspectratio (A/R = H/W) is assumed to be two.

IV. SIGNAL DELAY OF SWCNT BUNDLE

INTERCONNECT

1. Once all the circuit parameters are realized, we

can estimate the signal delay of the SWCNT

bundle interconnect for local, semiglobal and

global with diameter variation respectively in

each regime.

2. The input excitation is assumed to be a step

signal, and the SWCNT interconnects are

Fig7: Bundle SWCNT with distribution

of semiconducting and metallic

SWCNTs.

Fig.8: Schematic view of the SWCNT bundle

interconnects, including three densely

packed SWCNT bundles with spacing

(δ= 0.34nm) between two neighboring

SWCNTs in each bundle, i.e. the Van

der Waal‟s gap.

Fig.9: Equivalent circuit model of SWCNT bundle interconnect




simulated in TSPICE using the equivalent

circuit model in Fig.8 where Lm is ignored

while estimating the inductance of the bundle

as Lm ˂˂ LK.

3. The parameters of driver and load are

technology dependent and their exact value can

be obtained from [34] for 22nm technology

node as required for present simulation.

V. CROSSTALK PREDICTION IN SWCNT

BUNDLE DIL SYSTEM

The growing density of ICs and the

continuous increase of signal switching speed

suggests nanoscale devices for the future

development of integrated electrical circuits.

However, such developments can induce crosstalk

effects among adjacent lines, generating overshoot,

undershoot, and additional time delay resulting

their electromagnetic (EM) performance a limiting

concern owing to radio frequency (RF) signal

transmission and integrity [35].

Crosstalk in particular, is the unexpected

voltage noise interference due to the

electromagnetic coupling of adjacent transmission

lines when the signal propagates in the

transmission lines. As a result, it may cause signal

delay and glitch that may be propagated to the

output of a receiver, resulting a logic error at the

output of the receiving device [36]. Consequently,

it is necessary to realize the influencing factors

affecting the crosstalk voltage of single-walled

carbon nanotube (SWCNT) interconnects and

measures to reduce the same.

Propagation delay under the crosstalk

influence has been analyzed for different

interconnect models using a capacitively coupled

three-line bus architecture (Rossi et al. 2007) as

shown in Fig. 4. Out of these three lines, two are

referred as aggressors and the middle one as victim.

The interconnect line in bus architecture is

represented by equivalent RLC models of different

CNT structures. Each line in the bus architecture is

driven by CMOS driver. The coupling capacitance

(Ccm) demonstrates the effect of crosstalk induced

delay that primarily depends on the spacing (Sp)

between aggressor and victim lines and can be

expressed as (Majumder et al. 2012a)

The present section aims to estimate the

extent of functional crosstalk that arises due to the

simultaneous switching of adjoining aggressors.

The effect is measured with the variation of

diameters and lengths of interconnect with respect

to local, semiglobal and global application. The

spacing between the neighboring bundled

interconnects is 2nm (fixed) and coupling

capacitance is estimated using the relation:

𝐶𝑐𝑚 =𝜋𝜀0

𝑐𝑜𝑠𝑕−1 𝑆𝑝

𝑑𝑎𝑣𝑔 . (20)

Firstly, three coupled SWCNT interconnects

are considered to form a standard parallel wire

architecture over a ground plane by calculating the

coupling capacitances between adjacent

interconnects. The model is then extended to the

SWCNT bundle by calculating the corresponding

parameters. The estimated value of Ccm is presented

in fig.10 (a,b,c)which clearly indicates the variation

in the value as the length and diameter of

mSWCNT bundle interconnect are varied with

respect to 22nm technology node. It is observed

that there is a combined effect of diameter and

length increment over the value of Ccm as the

spacing between the bundles is kept constant.

Ironically, the increment of length within the range

has a subdued effect over Ccm in comparison to the

effect of diameter increment as the value reduces

Fig.10 (c): Ccm variation with respect to

global mSWCNT bundle

interconnect

Fig.10 (b): Ccm variation with respect to

semi-global mSWCNT bundle

interconnect

Fig.10 (a): Ccm variation with respect to local

mSWCNT bundle interconnect




dramatically with increment in diameter for the

same interconnect length.

Based on the above parametric calculation

the estimated functional crosstalk for different

length and diametric variation with respect to local,

semi-global and global interconnect levels are

present in fig.11 (a, b, c) and the tabulated result is

presented in table1 respectively.

It has been also realized that the inductive

effect gains significance in Vcrosstalk at all

interconnect levels. Hence, the simulated results of

Vcrosstalk are specifically illustrated in fig.12(a, b, c)

for maximum length at each diametric variation

and interconnect level.

The presented table not only distincts the

existence of Vcrosstalk at all interconnect levels

but we can also draw the following conclusions.

1. There is an increment of functional crosstalk

voltage (Vcrosstalk) horizontally as the

interconnect length increases with fixed

diameter of mSWCNT bundle interconnect.

2. There is a “dramatic” reduction of functional

crosstalk voltage (Vcrosstalk) for fixed length as

the diameter varies.

3. There is a decrement of functional crosstalk

voltage (Vcrosstalk) vertically as the interconnect

diameter increases with static length of

mSWCNT bundle interconnect suggesting one

of the physical measures to reduce crosstalk

for interconnect of fixed length.

VI. DELAY ESTIMATION IN SWCNT BUNDLE

DIL SYSTEM

With the scaling down of physical

dimensions in VLSI technologies, interconnect

delay over powers the gate delay inestimating

circuit performance [37]. But, as we extend the

realization of VLSI circuits in deep submicron

regime itbecomes necessary to have

computationally economicaland accurate

interconnect delay models. Consequently, for the

design ofcomplex circuits, more accurate analytic

models are needed topredict the interconnect delay

accurately.

Initially, VLSI interconnects were modeled

as RC linesand single pole Elmore-based models

[38, 39]as longchannel device delay dominated

over negligible interconnectdelay. However for

high speed interconnects, inductanceeffects gain

significance and can no longerbe ignored. The

concept can be well realized by the simulations

presented in figs. 12 (a, b and c) where the

inductive effect introduces „ringing affect‟.

The delay effect for the current simulation

estimated is presented in table 2. and supported by

illustration in figs. 13 (a, b and c)

It is clearly visible from the tabulated result and fig.

12 (a) that there is an exponential decrement in

delay for interconnect of same length but with the

increase in the diameter of individual diameters of

mSWCNTs of respective bundles.

The illustration present in fig. 12 (b)

indicates that delay estimation for semiglobal

interconnects do not propose the difference in

extracted delay for diameter variation for same

interconnect lengths at local level where the lengths

are ×10 times the interconnects at local scale

indicating the significance of nonlinear effects for

longer interconnects.

Fig.11(c): Vcrosstalk with respect to global

mSWCNT bundle interconnect

Fig.11 (a): Vcrosstalk with respect to

local mSWCNT bundle

interconnect

Fig.11 (b): Vcrosstalk with respect to semi-


interconnect




The illustration present in fig. 12 (c)

indicates that delay estimation for global

interconnects do not propose the difference in

extracted delay for diameter variation for same

interconnect lengths at local level where the lengths

are ×100 times approx. the interconnects at local

scale indicating the significance of nonlinear

effects for longer interconnects.

The tabulated result also suggest the effect

of interconnect lengths on delay with respect to

individual diameters of mSWCNT bundle when we

move from local to global scale via semiglobal

interconnects.

VII. OTHER SIMULATION RESULTS FOR SWCNT

BUNDLE DIL SYSTEM

Beside, crosstalk voltage and delay

estimation otherparametric analytical results to

assist in analyzing the validity of SWCNT bundle

DIL system at local, semiglobal and global level

includes:

1. tphl and tplh defined as the time taken by

voltage at output nodes of two aggressor lines

and one victim line to fall from 90% to 10%

and rise from 10% to 90% of its maximal

value. The result is tabulated in table 3 and 4

respectively.

2. tpdr measures the rising propagation delay

from input to rising output and the result is

tabulated in table 5 respectively.

3. tpdf measures the rising propagation delay

from input to rising output and the result is


4. tpd is the average propagation delay. tpd =

(tpdr + tpdf)/2 and the result is tabulated in

table 7 respectively.

5. tr is the rise timewhich measures the output

crossing 0.2 VDD to 0.8 VDDand the result is


6. tf is the fall time which measures the output

crossing 0.8 VDD to 0.2 VDD and the result is


7. The average nodal voltage for both the

aggressors is estimated during the transient

sweep from the time 10 ns to 55 ns resulting

the following parametric result as “avgval” and

the result is tabulated in table 10 respectively.

VIII. CONCLUSION

The present paper discusses the circuit-

oriented modeling techniques for mSWCNT bundle

interconnects. Based on the models, their electrical

performances have been predicted and evaluated

such as time delay, crosstalk effect, tphl and tplh,

tpdr, tpdf, tpd, tr, tf and average nodal voltage for

both the aggressors. It has been found that,

SWCNT bundles can have superior performance

but decreased at the local interconnect level.

Therefore, SWCNT bundles are suitable for the

design of long interconnects in the advanced

technology nodes.

It has been also realised that there is a

significant variation in the electrical performance

of mSWCNT bundle interconnects with diameter

variation for the same interconnect length.

IX. ACKNOWLEDGMENT

This research paper has been solely made

possible by the unconditional support of my family

and few intellectuals who have really bestowed me

Fig.13 (a): Delay estimation with respect to

local mSWCNT bundle

interconnect.

Fig.13 (b): Delay estimation with respect to

semiglobal mSWCNT bundle

interconnect.

Fig.13 (c): Delay estimation with respect to


interconnect.




with their presence in my life like Dr. R.P.

Agarwal, Dr. B.K. Kaushik, Mr. Dinesh Chandra

and Mr. Manoj Kumar Majumder. Their

overwhelming support has always helped me to

progress technically

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Mr. Shailendra Mishra has done M.Tech

(VLSI Design) from UPTU Lucknow and

presently pursuing Ph.D. in CNT interconnects. He has a teaching

experience of fifteen years and areas of

interest includes VLSI design, Electromagnetism, Antenna and SPICE

simulations. He has few papers in

international journals and conferences to his repute.




Mrs. Divya Mishra has done M.Phil.

(Physics) from CCS Univ. Meerut and presently pursuing Ph.D. in Crosstalk

analysis. She has a teaching experience

of nine years and areas of interest includes VLSI design, Quantum Physic

and SPICE simulations. She has few

papers in international journals and conferences to her repute.

(Dr.) R. P. Agarwal is currently working as Academic Advisor, Shobhit University,

Meerut, India. He was former Vice

Chancellor of Shobhit University, Meerut. Prof. Agarwal has rich varied experience of

teaching, research, development and

administration. He has 41 years of teaching experience and has published more than

100 research papers in referred

International and National Journals

Table 1: Tabulated result of functional crosstalk voltage for different length and diameter variation with respect

to local, semiglobal and global interconnect levels.

Table 2: Tabulated result of delay estimation for functional crosstalk voltage for different length and diameter

variation with respect to local, semiglobal and global interconnect levels.

Table 3: Tabulated result of tphl for functional crosstalk voltage for different length and diameter variation

with respect to local, semiglobal and global interconnect levels.

Local interconnect Crosstalk (mV)

Diameter (nm) Length (µm)

5 8 9

2.16 600 900 1000

2.296 70 120 130

2.43 74 89 100

Semi-global Interconnect Crosstalk (mV)

Diameter (nm)

Length (µm)

50 80 90

2.16 3000 3200 3300

2.296 700 1300 1400

2.43 600 1000 1100

Global Interconnect Crosstalk (mV)

Diameter (nm)

Length (µm)

100 400 700

2.16 3200 3300 3400

2.296 1600 3200 3300

2.43 1200 3100 3200

Local interconnect Delay (s)


5 8 9

2.16 2.60E-09 2.74E-09 2.80E-09

2.296 2.39E-09 2.37E-09 2.38E-09

2.43 2.38E-09 2.36E-09 2.36E-09

Semi-global Interconnect

Diameter (nm)

Length (µm) Delay (s)

50 80 90

2.16 3.35E-10 3.59E-10 3.76E-10

2.296 1.62E-10 2.05E-10 2.27E-10

2.43 1.40E-10 1.77E-10 1.98E-10

Global Interconnect Delay (s)

Diameter (nm)

Length (µm)

100 400 700

2.16 3.91E-10 1.01E-09 2.05E-09

2.296 2.49E-10 8.96E-10 2.12E-09

2.43 2.19E-10 8.74E-10 2.12E-09

Local interconnect




Table 4: Tabulated result of tplh for functional crosstalk voltage for different length and diameter variation


Table 5: Tabulated result of tpdr for functional crosstalk voltage for different length and diameter variation with

respect to local, semiglobal and global interconnect levels.

Diameter (nm) Length (µm) Time (s)

5 8 9

2.16 6.85E-09 6.92E-09 6.96E-09

2.296 6.70E-09 6.68E-09 6.69E-09

2.43 6.69E-09 6.67E-09 6.68E-09


Diameter (nm)

Length (µm) ) Time (s)

50 80 90

2.16 6.79E-09 6.46E-09 6.38E-09

2.296 6.98E-09 7.06E-09 7.09E-09

2.43 6.92E-09 7.02E-09 7.05E-09

Global Interconnect

Diameter (nm)

Length (µm)Time (s)

100 400 700

2.16 6.32E-09 6.33E-09 7.45E-09

2.296 7.13E-09 7.00E-09 7.74E-09

2.43 7.08E-09 7.23E-09 7.91E-09

Local interconnect

Diameter (nm) Length (µm)Time (s)

5 8 9

2.16 6.39E-09 6.34E-09 6.31E-09

2.296 6.57E-09 6.58E-09 6.58E-09

2.43 6.57E-09 6.60E-09 6.59E-09


Diameter (nm)


50 80 90

2.16 5.81E-09 5.70E-09 5.66E-09

2.296 6.27E-09 6.19E-09 6.14E-09

2.43 6.33E-09 6.25E-09 6.21E-09


Diameter (nm)

Length (µm)Time (s))

100 400 700

2.16 5.62E-09 4.86E-09 3.59E-09

2.296 6.09E-09 4.92E-09 3.53E-09

2.43 6.18E-09 5.01E-09 3.56E-09

Local interconnect


5 8 9

2.16 6.39E-09 6.92E-09 6.31E-09

2.296 6.57E-09 6.58E-09 6.58E-09

2.43 6.57E-09 6.60E-09 6.59E-09


Diameter (nm)


50 80 90

2.16 5.81E-09 5.70E-09 5.66E-09

2.296 6.27E-09 6.19E-09 6.14E-09

2.43 6.33E-09 6.25E-09 6.21E-09

Semi-global Interconnect Delay (s)

Diameter (nm)


100 400 700




Table 6: Tabulated result of tpdf for functional crosstalk voltage for different length and diameter variation with


Table 7: Tabulated result of tpd for functional crosstalk voltage for different length and diameter variation


Table 8: Tabulated result of tr for functional crosstalk voltage for different length and diameter variation

with respect to local, semiglobal and global interconnect levels

2.16 5.62E-09 4.86E-09 3.59E-09

2.296 6.09E-09 4.92E-09 3.53E-09

2.43 6.18E-09 5.01E-09 3.56E-09

Local interconnect


5 8 9

2.16 6.85E-09 2.89E-10 6.96E-09

2.296 6.70E-09 6.68E-09 6.69E-09

2.43 6.69E-09 6.67E-09 6.68E-09


Diameter (nm)


50 80 90

2.16 6.79E-09 6.46E-09 6.38E-09

2.296 6.98E-09 7.06E-09 7.09E-09

2.43 6.92E-09 7.02E-09 7.05E-09


Diameter (nm)


100 400 700

2.16 6.32E-09 6.33E-09 7.45E-09

2.296 7.13E-09 7.00E-09 7.74E-09

2.43 7.08E-09 7.23E-09 7.91E-09

Local interconnect


5 8 9

2.16 6.62E-09 3.60E-09 6.64E-09

2.296 6.63E-09 6.63E-09 6.63E-09

2.43 6.63E-09 6.63E-09 6.63E-09


Diameter (nm)


50 80 90

2.16 6.30E-09 6.08E-09 6.02E-09

2.296 6.63E-09 6.63E-09 6.61E-09

2.43 6.62E-09 6.63E-09 6.63E-09


Diameter (nm)


100 400 700

2.16 5.97E-09 5.60E-09 5.52E-09

2.296 6.61E-09 5.96E-09 5.63E-09

2.43 6.63E-09 6.12E-09 5.73E-09

Local interconnect


5 8 9

2.16 2.60E-09 2.74E-09 2.80E-09

2.296 2.39E-09 2.37E-09 2.38E-09

2.43 2.38E-09 2.36E-09 2.36E-09






Table9: Tabulated result of tf for functional crosstalk voltage for different length and diameter variation with


Table 10: Tabulated result of avgval for functional crosstalk voltage for different length and diameter variation


50 80 90

2.16 3.35E-10 3.59E-10 3.76E-10

2.296 1.62E-10 2.05E-10 2.27E-10

2.43 1.40E-10 1.77E-10 1.98E-10


Diameter (nm)


100 400 700

2.16 3.91E-10 1.01E-09 2.05E-09

2.296 2.49E-10 8.96E-10 2.12E-09

2.43 2.19E-10 8.74E-10 2.12E-09

Local interconnect


5 8 9

2.16 2.63E-09 2.70E-09 2.72E-09

2.296 2.45E-09 2.43E-09 2.43E-09 2.43 2.44E-09 2.41E-09 2.42E-09


Diameter (nm)


50 80 90

2.16 2.93E-09 2.75E-09 2.71E-09

2.296 2.76E-09 2.85E-09 2.89E-09

2.43 2.70E-09 2.79E-09 2.82E-09


Diameter (nm)


100 400 700

2.16 2.67E-09 2.78E-09 3.94E-09

2.296 2.93E-09 3.32E-09 4.20E-09

2.43 2.86E-09 3.45E-09 4.34E-09

Local interconnect Voltage (V)


5 8 9

2.16 3.52E-01 3.52E-01 3.52E-01

2.296 3.52E-01 3.52E-01 3.52E-01

2.43 3.52E-01 3.52E-01 3.52E-01

Semi-global Interconnect Voltage (V)

Diameter (nm)

Length (µm)

50 80 90

2.16 3.53E-01 3.52E-01 3.52E-01

2.296 3.52E-01 3.53E-01 3.52E-01

2.43 3.52E-01 3.52E-01 3.52E-01

Semi-global Interconnect Voltage (V)

Diameter (nm)

Length (µm)

100 400 700

2.16 3.53E-01 3.53E-01 3.53E-01

2.296 3.52E-01 3.53E-01 3.53E-01

2.43 3.52E-01 3.53E-01 3.53E-01




Fig.12 (b): Vcrosstalk for max. length and diametric variation with respect to semi-global mSWCNT bundle

interconnect illustrating the inductive effect.

Fig.12 (a): Vcrosstalk for max. length and diametric variation with respect to local mSWCNT bundle





Fig.12 (c): Vcrosstalk for max. length and diametric variation with respect to global mSWCNT bundle


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ISSN: 2278 909X International Journal of Advanced Research ...ijarece.org/wp-content/uploads/2015/10/IJARECE-VOL... · Shailendra Mishra,Divya Mishra, R.P. Agarwal Fig.2: Single SWCNT