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© 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0 • 9/13/16

AN-4193 Design Guideline for Flyback Travel Adapter using FAN602

Abstract

Quasi-Resonant (QR) switching, compared to the traditional

continuous and discontinuous modes of operation in a

flyback converter, cuts turn-on losses at the power switch,

thus increasing efficiency and lowering device temperatures.

It is also known as variable frequency or valley switching

flyback and is largely used in low power SMPS applications

such as charger, adapter and auxiliary supply. Based on the

proposed design guideline, a design example with detailed

parameters demonstrates the performance of the controller.

Introduction

The new quasi-resonant PWM controller FAN602 is aimed

at achieving power density of ≥ 10 W/in3 in universal input

range AC/DC flyback isolated power supplies. It

incorporates quasi-resonant control with proprietary valley

switching with a limited frequency variation. QR switching

provides high efficiency by reducing switching losses while

valley switching with a limited frequency variation bounds

the frequency band to overcome the inherent limitation of

QR switching.

The FAN602 has a programmable blanking frequency range

that provides flexibility in choosing noise rejection in

targeted frequency zones. It incorporates user-configurable

minimum peak current, which allows controlling the burst

mode entry/exit power level, thereby enhancing light-load

efficiency and eliminating audible noise.

VOCOCCLMP

NP

DCLMP

RCLMP

CBLK2

NS

NA

RVS1

RVS2CVS

LF

CBLK1

AC INBridge

HV

GATE

CS

VDD

VSGND

FB

CSNRSN

RF1

RF2

CVDD

CCSF

RCS_COMP

RCS

RGF

RGR

DG

Photo

coupler Photo

coupler

Shunt

Regulator

RBias2

RBias1

RFC CFC

CComp

RHV1

FMAX

IMIN

RIMIN

CFB

TX

ChokeFuse

RFMAXCFMAX

RHV2

DAUX

XC

FAN602

GATE

DRAIN

SOURCE

VDD GND

VIN

SR

Controller

Front End Stage

CVS < 10pF

CCSF < 20pF

Figure 1.Typical Application Circuit

AN-4193 APPLICATION NOTE

© 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0 • 9/13/16 2

Operation Principle of Quasi-Resonant Flyback Converter

QR flyback converter topology can be derived from a

conventional square wave, Pulse-Width Modulation

(PWM), flyback converter without adding additional

components. Figure 2 and Figure 3 show the simplified

circuit diagram of a quasi-resonant flyback converter and its

typical waveforms. The basic operation principles are:

During the MOSFET on time (tON), input voltage

(VIN) is applied across the primary side inductor

(Lm). MOSFET current (IDS) increases linearly

from zero to the peak value (IPK). During this time,

the energy is drawn from the input and stored in

the inductor.

When the MOSFET is turned off, the energy stored

in the inductor forces the rectifier diode (D) to turn

on. During the diode ON time (tD), the output

voltage (VO) is applied across the secondary-side

inductor and the secondary-side current (IS)

decreases linearly from the peak value to zero. At

the end of tD, all the energy stored in the inductor

has been delivered to the output. During this

period, the output voltage is reflected to the

primary side as SPORO NNVV . Then, the sum of

input voltage (VIN) and the reflected output voltage

(VRO) are imposed across the MOSFET.

When the secondary-side current reaches zero, the

drain-to-source voltage (VDS) begins to oscillate by

the resonance between the primary-side inductor

(Lm) and the MOSFET effective output capacitance

(COSS-eff) with amplitude of VRO on the offset of

VIN, as depicted in Figure 3. Quasi-resonant

switching is achieved by turning on the MOSFET

when VDS reaches its minimum value. This reduces

the MOSFET turn-on switching loss caused by the

capacitance loading between the drain and source

of the MOSFET.

VO

D

CO

NP : NS

VINLm

IDS

IS

2

S

P

SECTransOSSeffOSS

N

N

CCCC

Figure 2.Schematic of QR Flyback Converter

IDS (MOSFET Drain-to-Source Current)

IPK

IS (Secondary Side Current)

IPK×Np/Ns

VDS (MOSFET Drain-to-Source Voltage)

VRO = VO x NP/NS

tON tD tF

VIN - VRO

VIN

VIN + VRO

VRO = VO x NP/NS

FDON

OPSttt

1f

effOSSmF CLt

2tF

Figure 3. Typical Waveforms of QR Flyback Converter

If the MOSFET is chosen to be turned on at the

minimum drain-to-source of the MOSFET, it is

called quasi-resonant operation. In practical, the

MOSFET can be turned on different minimum

drain-to-source voltage points, the first, and the

second even the ninth. However, as the switching

frequency (fS-OP) of QR flyback converter

increases, the load decreases. Therefore, the

blanking time (tBNK) is needed. For heavy load

condition (50%~100% of full load), the blanking

time for the valley detection is fixed such that the

switching time is between tBNK and tBNK+2tF. For

the medium load condition (25%~50% of full

load), the blanking time is modulated as a function

of load current such that the upper limit of the

blanking frequency varies from the maximum

blanking frequency as load decreases where the

blanking frequency reduction stop point is the

minimum blanking frequency.

IPK

VDS

tBNK tEXT tEXT tEXT

Fixed Blanking Time Modulated Blanking Time

tBNK tBNK tBNK tBNK

100% Loading

75% Loading50% Loading 25% Loading 10% Loading

Figure 4.Frequency Fold-back Function



Design Procedure

In this section, a design procedure is presented by using the

schematic of Figure 1 as a reference. An offline adaptive

charger with 24 W (12 V/ 2 A) rated output power has been

selected as a design example. The design specifications are

as summarized in the Table 1. Nominal output current is 2 A

and the over-current limit level is set at higher level

considering the tolerance of CC regulation.

Table 1. Specifications of The Design Example

Description Min. Typ. Max. Unit

Input Section

Line Voltage 90 - 264 Vrms

Line Frequency 47 60 63 Hz

Target Efficiency at Full Load 87 %

Output Section

Maximum Output Voltage 11.4 12.0 12.6 V

Minimum Output Voltage 4.75 5.00 5.25 V

Maximum Output Power 24 W

Minimum Output Power 10 W

Constant Output Current 2.3 2.4 2.5 A

System Specifications

Burst Mode entry level as % of nominal power

25 - 35 %

Over-Voltage Protection Point 13.2 14.4 15.6 V

Maximum Operation Frequency

140 kHz

Minimum Operation Frequency

75 kHz

[STEP-1] Estimate Input Rated Power

The maximum output power of adaptive charger application

is 24 W and the target efficiency is 87% at least to meet the

most stringent efficiency regulations such as Energy Star’s

5-Star Level, CoC Tier II, and DoE Level 6 specifications.

Therefore, the estimated efficiency of the QR flyback

converter stage at maximum output power to calculate the

maximum input power should be larger than 92 %

(Assuming the efficiency of front end is 95%). With the

estimated efficiency (Eff), the maximum input power is

given as:

ff

MAXOMAXIN

E

PP .

.

(1)

(Design Example)

Assuming the efficiency of QR flyback is 92%, the

maximum input power is obtained as:

WAV

P MAXIN 09.2692.0

212.

[STEP-2] Determine Input Bulk Capacitor Voltage Range and Input Bulk Capacitor (CBLK)

The bulk capacitor voltage after the bridge rectifier has

twice line frequency ripple as shown in Figure 5. For

universal input range (90~264 Vrms), the maximum input

bulk capacitor voltage is given as:

MAXLINEMAXBLK VV .. 2 (2)

where VLINE.MAX is the maximum line voltage.

The minimum bulk capacitor value for a given line voltage

is determined by the load condition and bulk capacitor

value. Therefore, the input bulk capacitor is selected based

on the minimum bulk capacitor voltage specification of the

system. With a given maximum input power and the

minimum bulk capacitor voltage, the required bulk capacitor

is calculated as:

2

.

2

.

.

.1

.

.

2

]

)2

(sin

5.0[

MINBLKMINLINE

MINLINE

MINBLK

MINLINE

MAXIN

BLK

VV

V

V

f

P

C

(3)

Where VLIN.MIN is the minimum line voltage, VBLK.MIN is the

given minimum input bulk voltage and fLINE.MIN is the

minimum line frequency. When selecting the bulk capacitor,

the tolerance of the capacitance should be also considered.

MINLINEV .2

MINBLKV .

MINLINEV .2

LINEf2

1

Figure 5.Input Bulk Capacitor Voltage Waveform

(Design Example)

The maximum line voltage of the system specification

determines the maximum input bulk capacitor voltage as:

VVV MAXLINEMAXBLK 3732 ..

By setting the minimum input bulk dc voltage as 91 VDC,

the minimum input bulk capacitor is obtained as:

FCBLK 42

)91(127

]

)127

91(sin

5.0[60

09.26

22

1

However, due to the crucial role of the bulk capacitor,

separated capacitors approach is preferred in practice. It

improves the reliability and reduces the total ESR, which

in turn reduces the losses. Two 22 µF capacitors in parallel

(44 µF in total) are used.



[STEP-3] Determine the Reflected Output (VRO)

Figure 6 shows the typical waveforms of the drain voltage

of quasi-resonant flyback converter. When the MOSFET is

turned off, the input voltage (VIN) together with the output

voltage reflected to the primary (VRO) is imposed on the

MOSFET and the maximum nominal voltage across the

MOSFET is

ROMAXBLKNOMDS VVV .. (4)

where VBLK.MAX is the maximum input bulk capacitor

voltage. By increasing VRO, the capacitive switching loss

and conduction loss of the MOSFET are reduced. However,

this increases the voltage stress on the MOSFET as shown

in Figure 6. Therefore, VRO should be determined by a trade-

off between the voltage margin of the MOSFET and the

efficiency. It is typical to set VRO as 75~100 V so that

VDS.NOM is 450~470 V (75~80% of MOSFET rated voltage).

The transformer turn ratio is obtained as:

)( . FMAXO

RO

S

P

VV

V

N

N

(5)

where VO.MAX is the maximum output voltage and VF is the

rectifier diode forward voltage drop.

VO

D

CO

NP : NS

VBLK.MAXVRO

VDS

VDS.NOM

VDS.NOM

VRO

VRO

VBLK.MAX

VRO

VRO VBLK.MAX

0V

VF

Figure 6.Schematic of QR Flyback Converter

[STEP-4] Determine the Maximum Blanking Frequency (FMAX)

The FAN602 allows adjusting the maximum blanking

frequency (FMAX) between fBNK-MAX (140 kHz) and fBNK-MIN

(60 kHz) through an external resistor on the FMAX pin to

provide flexibility in reducing temperature of primary

MOSFET at high line. As shown in Figure 7, an internal

current source IFMAX creates VFMAX across RFMAX. This

voltage sets the oscillator reference voltage which

determines the minimum blanking time tBNK-MIN

corresponding to FMAX. When PCB layout is poor, it may

cause noise on the FMAX pin. The FMAX pin needs to be in

parallel with the capacitor (CFMAX) less than 4.7 nF to filter

the noise.

VFMAX

RFMAX

VCC

Oscillator

Reference

Generator

IFMAX = 20µA

tBNK-MIN

CFMAX

FMAX

CFMAX:1nF ~4.7nF

Figure 7.The Maximum Blanking Frequency Circuit

via External Resistor on FMAX Pin

Figure 8.Relationship between fBNK-MAX and RFMAX

[STEP-5] Determine the Transformer Primary-Side Inductance (Lm)

To determine the primary-side inductance (Lm), the

following variables should be determined beforehand.

The Minimum Operation Frequency (fS-OP.MIN): The minimum operation frequency occurs at the

minimum bulk capacitor voltage and full-load

condition, which should be higher than the

minimum frequency for DCM fOSC-MIN-DCM

(50 kHz). By increasing fS-OP.MIN, the transformer

size can be reduced. However, this results in

increased switching losses. Therefore, fS-OP.MIN is

determined by a trade-off between switching losses

and transformer size. Typically, fS-OP.MIN is set to be

around 65 kHz~85 kHz.

The Falling Time of the MOSFET Drain

Voltage (tF): As shown in Figure 3, the MOSFET

drain voltage falling time is half of the resonant

period of the MOSFET’s effective output

capacitance (COSS-eff) and primary-side inductance.

By increasing tF, EMI can be reduced. Meanwhile,

40

60

80

100

120

140

160

0 5 10 15 20 25 30 35 40 45 50

f BN

K-M

AX

(kH

z)

RFMAX (kΩ)

fBNK-MAX vs RFMAX

(Design Example)

Since the power is operated with synchronous rectification

controller, the VF should be 0V and the transformer turns ratio

is calculated as:

33.8)012(

100

S

P

N

N



this forces an increase of the resonant capacitor

resulting in increased switching losses. The

MOSFET’s effective output capacitance (COSS-eff)

is:

2

S

P

SECTransOSSeffOSS

N

N

CCCC

(6)

where COSS is output capacitor of MOSFET. Usually it

can refer to Effective Output Capacitance (COSS(eff.)) in

the MOSFET’s datasheet. CTrans is the transformer

equivalent primary capacitor obtained from measuring

the resonating frequency of the device once a prototype

exists. CSEC is the sum of secondary-side capacitance

created by rectifier diode junctions or MOSFET output

capacitor of synchronous rectification.

To determine effective capacitance for the equation, below

method can be used. First choose MOSFET candidates and

check the COSS specification. Below table is the COSS

specification of FCU900N60Z and if there is a COSS(eff)

specification as below, that is good candidate for the use of

equation (6) because it is effective capacitance when VDS is

switching.

Table 2. COSS specification of FCU900N60Z

Symbol Parameter Test Condition Min. Typ. Max. Unit

COSS Output Cap. VDS=380V, VGS=0 V, f=1 MHz

- 11.1 - pF

COSS(eff) Effective

Output Cap. VDS=0 V to 480 V, VGS=0 V

- 48.6 - pF

If there is no COSS(eff) then from the COSS graph below it is

possible to choose the graphical mean. From FDMS86150,

one candidate for SR MOSFET, datasheet there is no

COSS(eff) and Figure 9 explains how to determine the

effective capacitance.

2012V

2000pF

Drain voltage change range

COSS change range

Figure 9.Capacitance vs, Drain to Source Voltage

Maximum output voltage should be chosen as a worst case

and, if we assume that is 12 V, then VDS, horizontal axis,

can be vary from 0 V to 24 V and it is possible to make a

COSS varying range as described in the picture. Based on that

COSS range, mean value is possible to regard as a COSS(eff)

and could be around 2000 pF in this case.

In the case of parasitic capacitance of transformer, it is

impacted by non linear parameters like winding length,

winding distance, and adjacent winding displacement so as a

rule of thumb it is appropriate to choose from 2~5 pF.

After determining fS-OP.MIN and COSS-eff the primary-side

inductance is obtained as:

2

.

.

.. ))11

(2(

1

MINOPSeffOSS

ROMINBLK

MINOPSMAXIN

m

fCVV

fP

L

(7)

where PIN.MAX is specified in equation (1) and fS-OP.MIN is the

minimum operation frequency.

After determining Lm, the maximum duty cycle is calculated

as:

MINOPSmMAXIN

MINBLK

MAX fLPV

D ..

.

21

(8)

Once DMAX is determined, the peak current and RMS current

of the MOSFET in normal operation are obtained as:

MINOPSm

MAXMINBLK

PKDSfL

DVI

.

.

.

(9)

3..

MAX

PKDSRMSDS

DII (10)

From above equation, tON.MAX can be calculated with given

Lm as:

MINBLK

PKDS

mMAXONV

ILt

.

.

. (11)

(Design Example)

Fairchild’s 600 V/ 4.5 A FCU900N60Z is selected for the

primary-side MOSFET and the COSS(eff.) is 48.6 pF.

Fairchild’s 100 V/ 80 A FDMS86150 is selected for the

secondary-side SR MOSFET. The maximum output is

12 V, so the SR drain-to-source voltage is 0 V to 24 V

during the resonant period and CSEC is around 2000 pF,

refer to Figure 9. Assuming the CTrans is around 2 pF, the

MOSFET’s effective output capacitance (COSS-eff) is

obtained as:

pFpFpFpF

pFC effOSS 8042.79233.8

20006.48

2

The minimum operation frequency of the system

specification is 75 kHz, PIN.MAX is 26.09 W, VBLK.MIN is

91 V and VRO is 100 V, the primary-side inductance is

obtained as:

HkpkLm 525])7580)100

1

91

1(7509.262[( 12

The maximum duty cycle is obtained as:



498.07552509.26291

1 kuDMAX

The maximum peak current and RMS current of the

MOSFET in normal operation are obtained as:

Aku

I PKDS 15.175525

498.091.

AI RMSDS 469.03

498.015.1.

The maximum on time can be calculated as:

sut MAXON 63.691

15.1525.

[STEP-6] Determine the Current Sense Resistor (RCS)

Constant output current (CC) level is achieved by an

internal circuit of FAN602, which regulates the output

current using primary-side information only. The CC level

(IO.CC) is determined by the sensing resistor value and

transformer turn ratio as:

ff

CCOPK

CCREF

S

P

CS EIA

V

N

NR

.

_ 1

2

1 (12)

where VREF_CC (1.2 V) is the reference voltage of the current

regulator error amplifier and APK (3.6 V/V) is an

amplifying gain. When RCS is determined, the maximum

drain current limit of primary MOSFET can be determined

by pulse-by-pulse current limit as:

CS

LIMCS

LIMDSR

VI

(13)

where VCS-LIM (0.9 V) is the pulse-by-pulse current limit

voltage.

[STEP-7] Determine the Proper Core and the Minimum Primary Turns

When designing the transformer, both the maximum flux

density swing in normal operation (ΔB) and the maximum

flux density in transient (BMAX) should be considered. The

maximum flux density swing in normal operation is related

to the hysteresis loss in the core while the maximum flux

density in transient is related to the core saturation. With the

chosen core, the minimum number of turns for the

transformer primary-side to avoid the over-temperature in

the core is given by:

6.

. 10

e

PKDSm

MINPAB

ILN

(14)

where Lm is specified in equation (7), IDS.PK is the peak drain

current specified in equation (9), Ae is the cross-sectional

area of the transformer core in mm2 and Δ B is the

maximum flux density swing in tesla. If there is no

reference data, use ΔB =0.25~0.30 T. Since the MOSFET

drain current exceeds and IDS.PK reaches IDS-LIM in a transient

or fault condition, the transformer should be designed not to

be saturated when the MOSFET drain current reaches IDS-

LIM. Therefore, the maximum flux density (BMAX) when

drain current reaches IDS-LIM should be also considered as:

6

. 10

eMAX

LIMDSm

MINPAB

ILN

(15)

where Lm is specified in equation (7), IDS-LIM is specified in

equation (13), Ae is the cross-sectional area of the

transformer core in mm2 and BMAX is the maximum flux

density in tesla. Figure 10 shows the typical characteristics

of ferrite core from Sumida (DMR95). Since the core is

saturated at low flux density as the temperature goes high,

the high temperature characteristics need to be considered.

If there is no reference data, use BMAX =0.38~0.41 T. The

primary turns should be determined as less than NP.MIN

values obtained from equation (14) and (15).

Figure 10.Typical B-H Characteristics of DMR95

(Design Example)

The constant output current specification is 2.4 A; the

sensing resistor is obtained as:

532.092.04.2

1

6.3

2.133.8

2

1CSR

The maximum drain current limit of primary MOSFET is

obtained as:

AI LIMDS 69.1532.0

9.0



[STEP-8] Determine the Number of Turns and VCC Auxiliary Winding

The turn ratio (n) between the primary winding and

secondary winding is calculated as:

)( . FMAXO

RO

S

P

VV

V

N

Nn

(16)

where VRO is determined in STEP-3 and VO.MAX is the

maximum output voltage and VF is the rectifier diode

forward voltage drop.

Then, the appropriate integer for NS is determined so that

the resulting NP is larger than NP.MIN as:

MINPSP NNnN . (17)

where n is obtained in equation (16) while NP and NS are the

number of turns for the primary-side and the reference

output respectively.

Since the supply voltage (VVDD) to the FAN602 is provided

from an auxiliary winding of the transformer, the turn ratio

between the auxiliary winding and secondary winding

(NA/NS) should be determined by considering the allowable

VVDD range.

Considering SR operation period and stopping operation

period cases to guarantee stable operation of FAN602

without shutdown by UVLO or VDD OVP, the minimum

and the maximum of VDD voltage should meet the

following conditions:

MAXOFFVDDFAFMINO

S

AMINVDD VVVV

N

NV ... )(

(18)

MINOVPVDDFASDMAXO

S

A

MAXVDD VVVVN

NV ... )(

(19)

where VO.MIN and VO.MAX are the minimum and the

maximum output voltages respectively, VFA is the forward

voltage drop of auxiliary winding diode, VF is the drain-

source voltage drop of secondary SR during SR operation

period, VSD is the drain-source voltage drop of secondary

SR during SR stopping operation period, VVDD-OFF.MAX is the

maximum VDD turn-off threshold voltage, and VVDD-OVP.MIN

is the minimum VDD OVP threshold.

Since VVDD.MIN is related to the standby power consumption,

the smaller NA/NS leads to lower standby power

consumption. However, the VDD voltage ripple, caused by

the burst mode operation, should be considered to prevent

shutdown due to Under-Voltage Lockout (UVLO).

From Equations (18) and (19), the range of NA/NS can be

obtained as follows.

SDMAXO

FAMINOVPVDD

S

A

FMINO

FAMAXOFFVDD

VV

VV

N

N

VV

VV

.

.

.

. (20)

(Design Example)

The number of primary turns (NP) and number of

secondary turns (NS) are obtained as:

TTNP 3562.41533.8

Then, NP is set to 42 turns.

The auxiliary-to-secondary turns ratio NA/NS can be

obtained with given VO.MIN = 4.75V, VO.MAX = 12.6 V, VF

= 0 V and VSD=1 V and VFA=0.7 V as:

07.216.12

7.05.2735.1

075.4

7.07.5

S

A

N

N

Based on above result, NA/NS is selected as 1.71.

The number of turns required for the auxiliary winding is

obtained as:

TNA 55.8571.1 .Then, NA is set to 9 turns.

[STEP-9] Determine the VS Pin Voltage Divider Resistors (RVS1 and RVS2)

As shown in Figure 11, the FAN602 indirectly senses the

line voltage through the VS pin when the MOSFET is

turned on. During the MOSFET turn-on period, the

auxiliary winding voltage (VAUX) is proportional to the input

bulk capacitor voltage (VBLK) due to the transformer

coupling between the primary and auxiliary windings.

During the MOSFET conduction time, since the line voltage

detector clamps the VS pin voltage to VVS_Clamp (0 V), the

current IVS flowing out of VS pin is expressed as:

P

A

VS

BLK

VSN

N

R

VI

1

(21)

IVS is used for line voltage compensation and brownout

protection. When IVS out of the VS pin during the MOSFET

conduction time is smaller than IVS-Brownout (450 μA) for

longer than tD-Brownout (16.5 ms), the brownout protection is

triggered. With given input bulk capacitor voltage to trigger

brownout protection (VBLK.BO), RVS1.MAX can be calculated

as:

P

AMINBLK

P

ABOBLK

MAXVSN

NV

N

NVR

4502.1450

..

.1

(22)

Considering the maximum VS source current capability (IVS-

MAX), RVS1.MIN can be calculated as:

(Design Example)

RM8 core (Ae = 62mm2) made by Sumida is selected for the

transformer. The Lm is 525 µH while ΔB and BMAX are

0.3 T and 0.41 T, respectively; the minimum number of

primary turns (NP.MIN) without core saturation can be

obtained as:

Tu

N MINP 3310623.0

15.1525 6

.

Tu

N MINP 35106241.0

69.1525 6

.

The minimum number of primary turns is selected as 35 T.



P

AMAXBLK

P

A

MAXVS

MAXBLK

MINVSN

N

m

V

N

N

I

VR

3

..

.1

(23)

VS Over-Voltage Protection (OVP) prevents possible

damage caused by an output over-voltage condition. When

abnormal system conditions occur, which cause VS

sampling voltage to exceed VVS-OVP (min. 2.8 V / max.

3.0 V) for more than 2 consecutive switching cycles (NVS-

OVP), PWM pulses are disabled and FAN602 enters Auto-

Restart (AR) protection. VS over-voltage conditions are

usually caused by open circuit of the secondary-side

feedback network or a fault condition in the VS pin voltage

divider resistors.

The VS voltage during SR conduction time can be obtained

as:

21

2)(VSVS

VS

FO

S

A

VSRR

RVV

N

NV

(24)

where VF is the drain-source voltage drop of secondary SR

during SR operation period.

For VS pin voltage divider design, the minimum RVS2 is

determined by the desired VO-OVP and given RVS1.MAX from

Equation (22) as:

1

.

.12 )1(

S

A

MAXOVPVS

FOVPO

MAXVSVSN

N

V

VVRR

(25)

where VO-OVP is the maximum output over-voltage

protection level due to abnormal operation.

Considering SR stopping operation case to guarantee stable

operation, in order to prevent abnormal protection, the

maximum RVS2 is determined by the VO-MAX level of normal

operation as:

1

.

.

.12 )1(

S

A

MINOVPVS

SDMAXO

MAXVSVSN

N

V

VVRR

(26)

where VO.MAX is the maximum output voltage level under

normal operation and VSD is the body diode voltage drop of

secondary SR during SR stopping operation period.

VS under-voltage protection (UVP) provides accurate fold-

back point control in CC regulation. When VS sampling

voltage is less than VVS-UVP-L (min. 0.625 V / max. 0.675 V)

for longer than debounce cycles NVS-UVP, VS UVP is

triggered and the FAN602 enters 2 cycle AR mode.

Therefore, considering both SR operation and stopping

operation cases to guarantee stable operation, RVS2 should

be determined by VO-UVP.MAX and VO-UVP.MIN specifications

as follows:

1

.

.

.12 )1(

S

A

MAXUVPVS

FMAXUVPO

MAXVSVSN

N

V

VVRR

(27)

1

.

.

.12 )1(

S

A

MINUVPVS

SDMINUVPO

MAXVSVSN

N

V

VVRR

(28)

where VO.UVP.MAX and VO.UVP.MIN are the maximum and the

minimum fold-back output voltage levels, respectively.

Aux.

IVS

Line Voltage

Detector

5V

RVS1

RVS2

IVS

VAux

NA

NP

Pri.VBLK

GATE

Line signal

VS-Clamp

VS

Figure 11.Line Voltage Detection Circuit

(Design Example)

With given NP=42, NA=9, when the minimum input bulk

dc voltage is 91 VDC, then RVS1.MAX can be calculated as:

kR MAXVS 3642

9

4502.1

91.1

When the maximum input bulk dc voltage is 373VDC,

then RVS1.MIN can be calculated as:

km

R MINVS 64.2642

9

3

373.1

Based on above result, RVS1 is selected as 35 kΩ. With

the desired VO-OVP=14.4 V, the range of RVS2 due to VS

OVP can be obtained:

kkRVS 58.4)15

9

3

04.14(35 1

2

kkRVS 75.4)15

9

8.2

112(35 1

2

Assuming cable drop voltage = 0.2 V at IO-CC=2.4 A, VO-

UVP.MAX and VO-UVP.MIN can be given as 3.7 V and 2.2 V

from output voltage fold-back specification (2 V~3.5 V)

respectively. Therefore, the range of RVS2 due to VS UVP

can be obtained as:

kkRVS 95.3)15

9

675.0

07.3(35 1

2

kkRVS 26.4)15

9

625.0

12.2(35 1

2

From above results, RVS2 can be set to 4.4 kΩ.

[STEP-10] Determine the Line Voltage Compensation Resistor (RCS_COMP)

Equation (12) is a theoretical-based derived equation and it

does not take system’s inherent delays into consideration.

The actual output current regulation is affected by the



accuracy of the primary peak current measurement. Due to

MOSFET’s turn-off delay and other system-related delays, a

mismatch between the estimated discharge time and the

actual one is introduced as shown in Figure 12 which results

in imprecise output current regulation.

The primary-side MOSFET current sensing voltage at the

falling edge of the gate drive signal is used to estimate the

output current for primary CC control. Since the actual

MOSFET current keeps increasing during the MOSFET

turn-off delay time (tOFF.DLY), CC control is affected by the

line voltage variation as illustrated in Figure 12. The peak

current detection error generated by the turn-off delay is

given as:

DLYOFF

m

BLK

PKDS tL

VI ..

(29)

Since the output current error is proportional to line voltage,

the FAN602 incorporates line voltage compensation shown

in Figure 13 to improve primary CC accuracy as following:

04167.01

1

VSP

A

BLKCOMPRN

NVI

(30)

Line voltage information is obtained through the VS pin

current during primary MOSFET turn-on time. This line

compensation current (ICOMP) is proportional to the input

bulk capacitor voltage. The line compensation resistor value

is obtained as:

25024

250250

.

1

.

_

DLYOFF

m

VSCS

A

P

COMP

CSPKDS

COMP

OFFSET

COMPCS

tL

RR

N

N

I

RI

I

VR

(31)

DISt

Actual diode current

Estimated diode current

GATE

tOFF.DLY

IDSRCS

IDSRCS

IDS-SHRCS

IDSPK

RCS

IDSPK

NP/NS

IDS-SHNP/NS

VGS

Figure 12.Effect of MOSFET Turn-off Delay

CCSF

RCS_COMPRCS

CS

ICOMP

+ -VOFFSETIDS

VOFFSET-H

VGS

tOFF.DLY

IDSRCS

VCSVOFFSET-L

VGS

tOFF.DLY

IDSRCS

VCS

VGS

VCS

IDSRCS

Low Line High Line

∆ IDSRCS ∆ IDSRCS

250Ω

Figure 13.Line Voltage Detection Circuit

(Design Example)

Typically the MOSFET turn-off delay time (tOFF.DLY) is

around 100 ns~150 ns. From the beginning, the MOSFET

turn-off delay time (tOFF.DLY) can be set to 150 ns.

Therefore, the compensation resistor (RCS_COMP) value

can be obtained as:

346250150525

35532.0

9

4224_ n

kR COMPCS

RCS_COMP can be modified if constant current level is not

the same at high/low line condition.

[STEP-11] Determine the Burst Mode Entry Level

FAN602 features burst mode operation with a

programmable burst mode entry load condition using the

minimum peak current control which enables light-load

efficiency to be optimized for a given application. As shown

in Figure 14, the IMIN pin can be programmed with

external resistor RIMIN to select the minimum VCS threshold

level (VCS-IMIN) for burst mode entry as following:

2.010

)(

IMINMINVS

IMINCS

RIVV (32)

Figure 15 shows VCS-IMIN according to RIMIN and VS voltage

(VVS). This is to maintain the burst mode entry level at same

percentage of nominal output power for adaptive output

voltage applications where the output voltage changes

according to the requirement of the load. VCS-IMIN can be set

between VCS-IMIN-MAX (0.45 V) and VCS-IMIN-MIN (0.2 V).

When the output demands load whose corresponding peak

current is smaller than the minimum peak current, the PWM

on time is limited at the minimum peak current without

decreasing as the feedback voltage commands. Due to

frequency fold-back function, the feedback voltage will



control the blanking frequency to regulate the output power.

When the feedback voltage is lower than VFB-BNK-L, the

blanking frequency is fixed at the minimum blanking

frequency (fBNK-MIN). Thus, more power is delivered to the

load than required and feedback voltage is pulled low below

the burst mode threshold (VFB-Burst) stop switching as shown

in Figure 16. The peak current of burst mode entry load

condition (IDS.BURST) can be obtained as:

mMINBNKff

BURSTO

BURSTDSLfE

PI

.

.

2 (33)

where PO.BURST is the burst entry output power, Lm is

specified in equation (7). Therefore, RIMIN can be calculated

as:

MIN

CSBURSTDSVS

IMINI

RIVR

)2.0(10 .

(34)

D

C

CLK

Q

Q

OSCPWM

VCS-IMIN

VFB-A

VCS

IIMIN = 10µA

VCC

IMIN

CS

FB

RIMIN

VS

RVS1

RVS2

VAUX

NA

S/H

Av

1/3.5

VVS

S/H = Sampling and Hold

VFB

VFB

VFB-Burst-H/L

Figure 14.IMIN Function Circuit

Figure 15.VCS-IMIN as a Function of RIMIN with

Variation of VVS

VCS

VDS

fBNK = 140kHz

Fixed Blanking Time Modulated Blanking Time

VCS-IMIN

fBNK = 140kHz fBNK = 100kHz fBNK = 75kHz fBNK.MIN = 60kHz

VFB-A

PO

VFB

VFB-Burst-L

VFB-Burst-H

VFB-BNK-HVFB-BNK-L

IDS.BURST x RCS

MINBNKBURSTDSmffBURSTO fILEP 2

..2

1

Fixed Blanking Time Figure 16.Burst-Mode Operation with VCS-IMIN

(Design Example)

With given the maximum output voltage VO.MAX is 12 V,

RVS1=35 kΩ, and RVS2=4.4 kΩ, VVS is calculated from

Equation (24) as:

Vkk

kVVS 41.2

4.435

4.4)012(

5

9

Assuming the burst entry load condition is about 25% at

PO.MAX=24 W, the peak current of burst mode entry load

condition (IDS.BURST) can be obtained with 60 kHz the

minimum blanking frequency (fBNK-MIN) as:

Ak

I BURSTDS 643.05256092.0

25.0242.

Therefore, RIMIN can be calculated with 10 µA IMIN

current as:

kRIMIN 9910

)2.0532.0643.0(1041.2

For the output voltage of 9 V and 5 V condition, the VVS

can be calculated as:

Vkk

kVVS 81.1

4.435

4.4)09(

5

9

Vkk

kVVS 00.1

4.435

4.4)05(

5

9

The minimum VCS threshold level (VCS-IMIN) for output

voltage of 9 V and 5 V can be obtained as:

Vk

V IMINCS 282.02.010

)991081.1(

Vk

V IMINCS 201.02.010

)991000.1(

The power level of burst mode entry with output voltage

of 9 V and 5 V can be calculated as:

WkP VBurstO 07.492.060532.0

282.0525

2

12

9__

WkP VBurstO 07.292.060532.0

201.0525

2

12

9__

The burst entry load condition is about 23% at

PO.MAX=18 W (9 V/2 A) and 21% at PO.MAX=10 W

(5 V/2 A).

[STEP-12] Determine the HV Pin Startup Resistor (RHV)

During startup, the internal startup circuit is enabled and the

bulk capacitor voltage supplies the current IHV to charge the

hold-up capacitor (CVDD) through RHV. When the VDD

voltage reaches VVDD-ON, the internal startup circuit is

disabled and the sampling circuit shown in Figure 17 is

turned on to sample the bulk capacitor voltage. Voltage

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VC

S-M

IN(V

)

VS-SH(V)

Adapitve VCS-MIN Curve

RIMIN = 0Ω RIMIN = 75kΩ



across RLS is compared with the reference voltage (VREF) of

the brown-in comparator which generates a command signal

to start PWM switching. The brown-in level of the system

can be obtained as:

)1(LS

JEFTHV

REFINBrownR

RRVV

(35)

Therefore, RHV can be designed under the desired VBrown-IN

as:

JEFT

REF

INBrown

LSHV RV

VRR )1(

(36)

If the line voltage is lower than the programmed brown-in

voltage, FAN602 enters auto-restart mode and keeps

charging and discharging the VDD capacitor until the input

bulk capacitor voltage exceeds VBrown-IN.

AC Line

CDD

HV

VDD

RHV

+-

VDD.ON/ VDD.OFF

VDD

Good

RLS=1.2kΩ

8

5

CX1

CX2

S1

S2

Brown IN+

-Vref = 0.845V

VDD=VDD-ON(17.2V)

RJFET=6.4kΩ

Figure 17.HV Startup Circuit

[STEP-13] Design the RCD Clamping Circuit in the Primary-Side

When the primary-side MOSFET is turned off, a high-

voltage spike is generated across the MOSFET drain-to-

source due to the transformer leakage inductance. This

excessive voltage can lead to an avalanche breakdown and

possible failure of the MOSFET. Therefore, a RCD

clamping circuit is used to limit the voltage, as shown in

Figure 18. The overshoot voltage (VOS) is related to the

power dissipation in the clamping circuit. Setting the

voltage overshoot too low can lead to severe power

dissipation in the clamping circuit.

It is typical to have a margin of 20~25% of the breakdown

voltage for the maximum MOSFET voltage stress. The

maximum voltage stress of the MOSFET is given as:

CLMPMAXBLKMAXDS

OSROMAXBLKMAXDS

VVV

VVVV

..

.. (37)

where VOS is the voltage overshoot of the drain voltage and

VCLMP is the maximum clamping capacitor voltage, as

illustrated in Figure 18.

When the drain voltage of the MOSFET reaches the voltage

of node X (sum of input bulk voltage and clamping

capacitor voltage), the clamping diode is turned on to limit

the drain voltage. It is assumed that the clamping capacitor

is large enough such that its voltage does not change

significantly during one switching cycle.

The maximum overshoot voltage occurs at the MOSFET

drain current reaches IDS-LIM in a transient or fault. The

power dissipated in the RCD network is given as:

ROCLMP

CLMP

LIMDSleakOPSCLMPVV

VILfP

2

2

1

(38)

where Lleak is the leakage inductance. The operation

frequency (fS-OP) at IDS-LIM is given as:

1

.

)(

effOSSm

RO

LIMDSm

MINBLK

LIMDSm

OPS CLV

IL

V

ILf

(39)

Once the power dissipation in the snubber is obtained, the

snubber resistor is calculated as:

2

)(2

LIMDSleakOPS

ROCLMPCLMP

CLMPILf

VVVR

(40)

where RCLMP is the clamping resistor.

The maximum ripple of the clamping capacitor voltage is

obtained as:

CLMPOPSCLMP

CLMP

CLMPVfR

VC

(41)

In general, 5~10% ripple of the selected capacitor voltage is

reasonable. The clamping capacitor should be ceramic or a

material that offers low ESR. Electrolytic or tantalum

capacitors are unacceptable.

(Design Example)

For brown-in threshold voltage at 80 VRMS, the HV

resistor RHV can be obtained as:

kkkRHV 1534.6)1845.0

280(2.1



+

VBLK

-

+

VO

-

Np: Ns

IDS

L

O

A

D

VGS

+

VDS

-

VDS

BVdss

20~25% of BVdss

VOS

-

VCLMP

+

CCLMP

RCLMP

LleakDCLMP

X

COSS

IDS

ICLMP

ICLMP

IDS.PK

ICLMP.PK

VRO

VBLK.MAX

VCLMP

-

VRO

+

-

VLleak

+

Figure 18.RCD Clamping Circuit and Waveforms

(Design Example)

Fairchild’s 600 V SuperFET FCU900N60Z is selected, the

voltage overshoot to limit the maximum drain voltage

below 580 V is:

VVV MAXBLKCLMP 207580 .

The leakage inductance and effective output capacitance of

MOSFET (COSS-eff) are calculated from the resonance

waveform as 1 µH and 80 pF, respectively.

The operation frequency (fS-OP) at IDS-LIM is given as:

kHzpf OPS 53)80525100

69.1525

91

69.1525( 1

The power dissipation in the clamping circuit is obtained

as:

k

kRCLMP 293

69.1153

)100207(20722

The maximum ripple of the clamping capacitor voltage is

obtained as:

nFkk

CCLMP 33.11053293

207

[STEP-14] Determine the Output Capacitor

The output capacitance (COUT) is designed in order to

guarantee the maximum output voltage ripple required by

the system’s specifications (ΔVO.SPEC).

The output voltage ripple (ΔVO) is affected by the output

ripple generated by COUT (ΔVCOUT) and the output ripple

generated by the equivalent series resistor (RES) of an output

capacitor (ΔVRES). For Flyback converter, the ΔVCOUT and

ΔVRES can be approximately obtained as:

O

MAXOPKDSm

OUT

COUTVn

IInL

CV

2

2

..

2

)(1

(42)

ESPKDSRES RInV . (43)

where n is the turn ratio of the primary-side and the

secondary-side.

According to the relative amplitude between ∆VRES and

∆VCOUT, the ∆VO can be approximately obtained as:

RESCOUTCOUTO VVatVV (44)

RESCOUTRESO VVatVV (45)

Since ΔVO should be less than the ΔVO.SPEC, the maximum

RES is limited to meet ΔVO.SPEC as:

PKDS

SPECO

ESIn

VR

.

.

(46)

The minimum CO can be obtained to meet ΔVO.SPEC as:

O

MAXOPKDSm

SPECO

OUTVn

IInL

VC

2

2

..

. 2

)(1

(47)

(Design Example)

With given IDS.PK = 1.15 A at PO.MAX = 24 W, turn ratio (n)

= 8.4 and ΔVO.SPEC =150 mV, the maximum RES is

calculated as:

mm

RES 52.1515.14.8

150

The minimum output capacitance can be calculated with

IO.MAX = 2 A at PO.MAX = 24 W, VO = 12 V and Lm =

525 μH as:

Fm

COUT

121124.82

)215.14.8(525

150

12

2

In the actually power board, the leakage inductance and

parasitic capacitor will cause larger spike current at the

secondary-side. For the lower RES value, two 330 µF

conductive polymer aluminum solid capacitors with the

maximum 30 mΩ RES (660 µF in total) are used in parallel.

The output voltage ripple is calculated as:

mVVCOUT 56.27124.82

)215.14.8(525

660

12

2

mVmVRES 45.725.715.14.8

The maximum ΔVO is around 72.45 mV.



[STEP-15] Design the Feedback Loop

Since the FAN602 operates a flyback converter in DCM

with a peak-current mode control, the control to output

transfer function of the power stage is given as:

P

ZV

AFB

O

OutputtoControl s

s

G

V

VsG

1

1

)(^

^

(48)

where OUTL

PCR

2

;OUTES

ZCR

1

; COUT is effective

output capacitance and RES is the effective series resistance

of the output capacitor.

The gain GV is defined as:

CSRO

m

BLK

mCSDSOPS

DSCS

O

VRV

L

V

LRIf

IR

VG

1)(

21

(49)

where IDS is the peak drain current at given operation

condition.

Since the control-to-output transfer function is first order,

the feedback control loop can be implemented with a one-

pole and one-zero compensation circuit. The transfer

function of the compensation network is given as:

1

1

^

^

)(CP

CZI

O

AFBrCompensato

s

s

sV

VsG

(50)

where FBbiasF

FFCVI

CRR

RRACTR

1

1)( ; CTR is current transfer

ratio of opto-coupler; AV is internal voltage attenuator of FB

pin; FBFB

CPCZ

1

1 and FCFFC

CZCRR

)(

1

1

1

Note that the opto-coupler introduces a mid-frequency pole

due to the collector-emitter junction capacitance. Since the

collector-base junction in a photo-transistor is used as a light

detector, its area is relatively large, which introduces a large

effective collector-emitter junction capacitance. The typical

collector-emitter junction capacitance (COPT) is about 3-

10 nF for the opto-coupler, which brings a pole at around

1 kHz with a bias resistor (ZFB) of 42 k as shown in Figure

20. This pole can occur around the desired crossover

frequency, making the system unstable. Therefore, this

additional pole should be considered when designing the

compensation network. The feedback control loop should be

implemented with a two-pole and two-zero compensation

circuit. The transfer function of the compensation network is

given as:

)()(

)()()(

21

21

CPCP

CZCZIrCompensato

ss

ss

ssG

(51)

where

OPTFBFBF

FFCCOMPVI

CZCR

RRCACTR

1

1)( ;

FBFB

CPCZ

1

1 ;OPTFB

CPCZ

1

2 ;FCFFC

CZCRR

)(

1

1

1

and COMPBias

CZCR

1

2

1

The procedure to design the feedback loop is as following:

The crossover frequency (fC) is chosen depending

on various design factors and constraints. In a

power converter, it is possible to approximate its

closed-loop output impedance by the output

capacitor impedance at the crossover frequency.

Therefore, the output voltage undershoot level, VU,

occurring during an output transient step, ∆IOUT,

can be approximated by the following :

CO

OUTU

fC

IV

2 (52)

where COUT is the effective output capacitance and fC is

the crossover frequency.

Let the product of GControl-to-Outp(s) and GCompensator(s)

be unity gain.

1)()(^

^

^

^

O

AFB

AFB

OrCompensatoOutputtoControl

V

V

V

VsGsG

Let ωCZ2 = ωCP2.

Let ωCZ1 = fC/2 ~ fC/10.

Let ωCP1 = 2fC ~ 10fC. It depends on the noise on

the FB pin.

Lm

+

VO

-

NP:NS

IDS

Gate

CS

RCS

FB

S

R

Q

Q

OSC

Av

+

-

VCS

Drv

VFB-AShunt

Regulator

RFCCFC

RBias1

RF1

CFB

1/3.5

RLCO

ZFB

COPT

+

VBLK

-

CCOMP

Figure 19.Feedback Loop Circuit



Figure 20.Frequency Response of Opto-Coupler

(Design Example)

Considering the delay time, which is the feedback voltage

from 0 to VFB-Burst-H, causes output voltage deep drop at

transient step ∆IOUT = 2 A, the output voltage undershoot

level VU should be set to 0.15 V. The crossover frequency fC

can be obtained as:

kHzu

fc 2.315.02660

2

The crossover frequency fC can be set at 4 kHz.

Then, the gain GV for low line and the maximum load

condition is obtained as:

29.10532.0

1)

100

525

91

525(

2

532.015.1751

15.1532.0

12

kGV

The pole and zero of system are obtained as:

HzCR

fOUTL

P 37.80660122

22

2

2

kHzmCR

fOUTES

Z 15.326605.72

1

2

1

The crossover frequency is 4 kHz and let the frequency be

4 kHz and GControl-to-Output (s) is obtained as:

2278.0

37.80

41

15.32

41

29.10)4(

kk

k

kHzG OutputtoControl

Let the product of GControl-to-Outp(s) and GCompensator(s) be unity

gain, the GCompensator(s) can be calculated as:

1)()( sGsG onCompensatiOutputtoControl

389.4)4(

1)4(

kHzGkHzG

OutputtoControl

rCompensato

With CTR = 0.5, ZFB = 42 kΩ, RF1 = 40 kΩ and AV = 1/3.5,

the RBias1 and RFC can be obtained as:

1

40

405.3

425.0389.4)4(

Bias

FC

rCompensatoR

Rk

k

kkHzG

RBias1 is selected to 1.5 kΩ and RFC is selected to 3.9 kΩ.

Assuming the opto-coupler brings a pole at around 1 kHz

with a bias resistor (ZFB) of 42 k, the COPT can be

estimated as:

nFkk

COPT 8.31422

1

Let fCZ2 = fCP2. The CCOMP can be calculated as:

nFkk

CCOMP 10615.12

1

Let fCZ1 = fC/10. The RFC can be calculated as:

nFk

CFC 063.94009.432

1

Let fCP1 = 10fC. The CFB can be calculated as:

pFkk

CFB 9440422

1

With given RF1=40 kΩ, RFC=3.9 kΩ, CFC=10 nF, RBais1

=1.5 kΩ, CCOMP =100 nF, ZFB = 42 kΩ, CFB = 0.1 nF, COPT =

3.8 nF, RES =15 mΩ and COUT = 660 μF, magnitude and

phase response of loop gain can be obtained as shown in

figures below. The control bandwidth is about 4 kHz and

phase margin is about 85 degrees.

-40

-20

0

20

40

60

80

100

120

0.1 1 10 100 1000 10000 100000

dB

frequency (Hz)

Gain

Control-to-output

Compensation

Closed Loop

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

0.1 1 10 100 1000 10000 100000

deg

rees

frequency (Hz)

Phase

Control-to-output

Compensation

Closed Loop



1. Design Summary

In this section, the operation of the Flyback DC/DC converter using FAN602, shown in Figure 21, is experimentally verified

for 24 W designs. The system’s components values are calculated according to the design procedure discussed in previous

sections. FAN6291 is used at secondary-side for adaptive charger application (5 V / 2 A, 9 V / 2 A and 12 V / 2 A).

VOCOUTCCLMP

NP

DCLMP

RCLMP

CBLK2

NS

NA

RVS1

RVS2CVS

LF

CBLK1

AC INBridge

HV

GATE

CS

VDD

VSGND

FB

RF1

RF2

CVDD

CCSF

RCS_COMP

RCS

RGF

RGR

DG

EL1018

EL1018

RBias1

RFC CFC

RHV1

FMAX

IMIN

RIMIN

CFB

RM8

Choke

Fuse

RFMAXCFMAX

RHV2

DAUX

FAN602

22μF 22μF

100μF

MDB10SV

80μF

15A/250V

TH

SCK053

5.1 kΩ

75 kΩ

75 kΩ

300 kΩ

FFM107

33 Ω

1 nF

470 pF

100 kΩ 1 nF 0 Ω

0.533 Ω22 pF

345 Ω

47 Ω

0 Ω 1N4148

22 uF

1N4148

N.C

35 kΩ

4.4 kΩ

1 nF30 Ω

660μF

40 kΩ

BLD

LGATE

VIN

VREF

GATE

LPC

DP

DN

GNDCS

DN

DP

IREFCC1CC1

SFBCC2CC2

Load Switch

FAN6291

0.03 Ω

169kΩ

11kΩ

FDMS86150L

10 Ω

100 Ω

10 kΩ

3.9 kΩ 10 nF

1.5 kΩ 100 nF

10 kΩ 47 nF

100 pF

FCU900N60Z

42 T 5 T

9 T

CCOMP

Figure 21. Flyback DC/DC Converter using FAN602

2. Experimental Results

In order to show the validity of the design procedure

presented in this application note, the converter of the

design example has been built and tested. All the circuit

components are used as designed in the design example.

Table 3 shows the measured efficiency at the end of board

according to line voltage, load, and output voltage

condition. The minimum average efficiency at 12 VO is

89.33 %, which is better than the 86.8 % target efficiency.

The minimum average efficiency at 9 VO is 88.42 %,

which is better than the 85.45 % target efficiency. The

minimum average efficiency at 5 VO is 85.77 %, which is

also better than the 79 % target efficiency. Therefore, the

measured efficiency meets CoC Tier 2.

Table 4 shows the measured output voltage ripple and

noise. The maximum output voltage ripple and noise is

149 mV at 90 VAC and max load condition, which is

below 150 mV design specification.

Table 3. Measured Efficiency at the end of Board

Table 4. Measured Output Voltage Tipple and Noise



References

[1] Application Note AN-4146,“Design Guidelines for Quasi-Resonant Converters Using FSCQ-series Fairchild Power

Switch (FPSTM

)”

[2] Application Note AN-6291,“Integrated Critical Mode PFC / Quasi-Resonant Current Mode PWM Controller

FAN6921”

Related Datasheets

FAN602-Offline Quasi-Resonant PWM Controller

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Is Now Part of - ON Semiconductor · Introduction The new quasi-resonant PWM controller FAN602 is aimed ... Maximum Output Voltage 11.4 12.0 12.6 V Minimum Output Voltage 4.75 5.00