12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial ... · 12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface ... Voltage Output Slew Rate SR 0.5 V/µs Voltage

General DescriptionThe MAX5742 quad, 12-bit, low-power, buffered volt-age-output, digital-to-analog converter (DAC) is pack-aged in a space-saving 10-pin µMAX package (5mm

3mm). The wide supply voltage range of +2.7V to+5.5V and 229µA supply current accommodates low-power and low-voltage applications. DAC outputsemploy on-chip precision output amplifiers that swingRail-to-Rail®. The MAX5742’s reference input accepts avoltage range from 0 to VDD. In power-down the refer-ence input is high impedance, further reducing the sys-tem’s total power consumption.

The 20MHz, 3-wire SPI™, QSPI™, MICROWIRE™ andDSP-compatible serial interface saves board spaceand reduces the complexity of opto- and transformer-isolated applications. The MAX5742 on-chip power-onreset (POR) circuit resets the DAC outputs to zero andloads the output with a 100kΩ resistor to ground. Thisprovides additional safety for applications that drivevalves or other transducers that need to be off onpower-up. The MAX5742’s software-controlled power-down reduces supply current to less than 0.3µA andprovides software-selectable output loads (1kΩ, 100kΩ,or high impedance) while in power-down. The MAX5742is specified over the -40°C to +125°C automotive tem-perature range.

ApplicationsAutomatic Tuning

Gain and Offset Adjustment

Power Amplifier Control

Process Control I/O Boards

Battery-Powered Instruments

VCO Control

Features Ultra-Low Power Consumption

229µA at VDD = +3.6V271µA at VDD = +5.5V

Wide +2.7V to +5.5V Single-Supply Range

10-Pin µMAX Package

0.3µA Power-Down Current

Guaranteed 12-Bit Monotonicity (±1LSB DNL)

Safe Power-Up Reset to Zero Volts at DAC Output

Three Software-Selectable Power-DownImpedances (100kΩ, 1kΩ, Hi-Z)

Fast 20MHz 3-Wire SPI, QSPI, and MICROWIRE-Compatible Serial Interface

Rail-to-Rail Output Buffer Amplifiers

Schmitt-Triggered Logic Inputs for DirectInterfacing to Optocouplers

Wide -40°C to +125°C Operating TemperatureRange

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12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface

________________________________________________________________ Maxim Integrated Products 1

1

2

3

4

5

10

9

8

7

6

OUTD

OUTC

OUTB

OUTAGND

VDD

SCLK

CS

MAX5742

µMAX

TOP VIEW

REFDIN

Pin Configuration

19-2122; Rev 2; 7/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Rail-to-Rail is a registered trademark of Nippon Motorola, Inc.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor, Corp.

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX5742EUB -40°C to +85°C 10 µMAX

MAX5742AUB -40°C to +125°C 10 µMAX

Functional Diagram appears at end of data sheet.

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values areVDD = +5V, TA = +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

VDD to GND..............................................................-0.3V to +6VOUT_, SCLK, DIN, CS, REF to GND...............-0.3 to (VDD+0.3V)Maximum Continuous Current Into Any Pin......................±50mAContinuous Power Dissipation (TA = +70°C)

10-Pin µMAX (derate 6.9 mW/°C above +70°C) ..........555mW

Operating Temperature Range .........................-40°C to +125°CJunction Temperature.......................................-65°C to +150°CStorage Temperature Range ............................-65°C to +150°CLead Temperature (soldering, 10s) ................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC ACCURACY (Note 1)

Resolution N 12 Bits

Integral Nonlinearity Error INL (Note 2) ±2 ±16 LSB

Differential Nonlinearity Error DNL Guaranteed monotonic (Note 2) ±1 LSB

Zero-Code Error OE Code = 000 0.4 1.5 % of FS

Zero-Code Error Tempco 2.3 ppm/°C

Gain Error GE Code = FFF hex ±3 % of FS

Gain-Error Tempco 0.26 ppm/°C

Power-Supply Rejection Ratio PSRR Code = FFF hex, ∆VDD = ±10% 58.8 dB

REFERENCE INPUT

Reference Input Voltage Range VREF 0 VDD V

In operation 32 45 63 kΩReference Input Impedance RREF

In power-down mode 2 MΩPower-Down Reference Current In power-down mode (Note 3) 1 10 µA

DAC OUTPUT

Output Voltage Range No load (Note 4) 0 VDD V

DC Output Impedance Code = 800 hex 0.8 ΩVDD = +3V 15

Short-Circuit CurrentVDD = +5V 48

mA

VDD = +3V 8Wake-Up Time

VDD = +5V 8µs

Output Leakage CurrentPower-down mode = output highimpedance

±18 nA

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_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values areVDD = +5V, TA = +25°C.)

TIMING CHARACTERISTICS (VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)

Note 1: DC specifications are tested without output loads.Note 2: Linearity guaranteed from code 115 to code 3981.Note 3: Limited with test conditions.Note 4: Offset and gain error limit the FSR.Note 5: Guaranteed by design.


DIGITAL INPUTS (SCLK, DIN, CS)

Input High Voltage VIH VDD = +3V, +5V0.7 xVDD

V

Input Low Voltage VIL VDD = +3V, +5V0.3 xVDD

V

Input Leakage Current IIN Digital inputs = 0 or VDD ±0.1 ±1 µA

Input Capacitance CIN 5 pF

DYNAMIC PERFORMANCE

Voltage Output Slew Rate SR 0.5 V/µs

Voltage Output Settling Time 400 hex to C00 hex (Note 5) 4 10 µs

Digital Feedthrough Any digital inputs from 0 to VDD 0.1 nV-s

Digital-Analog Glitch ImpulseMajor carry transition (code 7FF hex to code800 hex)

12 nV-s

DAC-to-DAC Crosstalk 2.4 nV-s

POWER REQUIREMENTS

Supply-Voltage Range VDD 2.7 5.5 V

All digital inputs at 0 or VDD = 3.6V 229 395Supply Current with No Load IDD

All digital inputs at 0 or VDD = 5.5V 271 420µA

Power-Down Supply Current IDDPD All digital inputs at 0 or VDD = 5.5V 0.29 1 µA


SCLK Clock Frequency f SCLK 0 20 MHz

SCLK Pulse Width High tCH 25 ns

SCLK Pulse Width Low tCL 25 ns

CS Fall to SCLK Rise Setup Time tCSS 10 ns

SCLK Fall to CS Rise Setup Time tCSH 10 ns

DIN to SCLK Fall Setup Time tDS 15 ns

DIN to SCLK Fall Hold Time tDH 0 ns

CS Pulse Width High tCSW 80 ns

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4 _______________________________________________________________________________________

-16

-4

-8

-12

0

4

12

8

16

0 512 1024 1536 2048 2560 3072 3584 4096

INTEGRAL NONLINEARITY vs.CODE, TA = +25°C

MAX

5742

toc0

1

CODE

INL

(LSB

)

VDD = +5V

VDD = +3V

-0.2

-0.4

-0.6

-0.8

-1.0

0.2

0

0.4

0.8

0.6

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

DIFFERENTIAL NONLINEARITY vs.CODE, TA = +25°C

MAX

5742

toc0

2

CODE

DNL

(LSB

)

-0.6

0.0

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

TOTAL UNADJUSTED ERROR vs.CODE, TA = +25°C

MAX

5742

toc0

3

CODE

TOTA

L UN

ADJU

STED

ERR

OR (%

)

VDD = +5V

VDD = +3V

-16

-4

-8

-12

0

4

12

8

16

0 512 1024 1536 2048 2560 3072 3584 4096

INTEGRAL NONLINEARITY vs.CODE, TA = -40°C

MAX

5742

toc0

4

CODE

INL

(LSB

)

VDD = +5V

VDD = +3V

-16

-4

-8

-12

0

4

12

8

16

0 512 1024 1536 2048 2560 3072 3584 4096

INTEGRAL NONLINEARITY vs.CODE, TA = +125°C

MAX

5742

toc0

7

CODE

INL

(LSB

)

VDD = +5V

VDD = +3V

-0.2

-0.4

-0.6

-0.8

-1.0

0.2

0

0.4

0.8

0.6

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

DIFFERENTIAL NONLINEARITY vs.CODE, TA = -40°C

MAX

5742

toc0

5

CODE

LSB

-0.6

0

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

TOTAL UNADJUSTED ERROR vs.CODE, TA = -40°C

MAX

5742

toc0

6

CODE

TOTA

L UN

ADJU

STED

ERR

OR (%

)

VDD = +5V

VDD = +3V

-0.2

-0.4

-0.6

-0.8

-1.0

0.2

0

0.4

0.8

0.6

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

DIFFERENTIAL NONLINEARITY vs.CODE, TA = +125°C

MAX

5742

toc0

8

CODE

DNL

(LSB

)

-0.6

0

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

TOTAL UNADJUSTED ERROR vs.CODE, TA = +125°C

MAX

5742

toc0

9

CODE

TOTA

L UN

ADJU

STED

ERR

OR (%

)

VDD = +5V

VDD = +3V

__________________________________________Typical Operating Characteristics(VREF = VDD, TA = +25°C, unless otherwise noted.)

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WORST-CASE INL AND DNLvs. TEMPERATURE

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toc1

0

-16

-12

-4

-8

8

12

4

0

16

INL

AND

DNL

(LSB

)

-40 20 40 600 80 100 120TEMPERATURE (°C)

MINIMUM DNL

MINIMUM INL

MAXIMUM DNL MAXIMUM INL

-200

0.5

1.0

1.5

2.0

2.5

3.0

0 42 6 8 10 12 14 16

SOURCE-AND-SINK CURRENT CAPABILITY(VDD = +3V)

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toc1

1

ISOURCE/SINK (mA)

V OUT

(V)

CODE = 000 HEX,SINKING CURRENT INTO OUT_

CODE = FFFHEX, SOURCINGCURRENT FROM OUT_

CODE = C00HEX, SOURCINGCURRENTFROM OUT_

CODE = 400 HEX,SINKING CURRENTINTO OUT_

0 42 6 8 10 12 14 16

SOURCE-AND-SINK CURRENT CAPABILITY(VDD = +5V)

MAX

5742

toc1

2

ISOURCE/SINK (mA)

V OUT

(V)

0

1.5

1.0

0.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

CODE = 000 HEX,SINKING CURRENT INTO OUT_

CODE = FFF HEX, SOURCINGCURRENT FROM OUT_

CODE = C00 HEX,SOURCING CURRENTFROM OUT_

CODE = 400 HEX,SINKING CURRENTINTO OUT_

0

160

80

320

240

400

480SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX

5742

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3

SUPPLY VOLTAGE (V)

SUPP

LY C

URRE

NT (µ

A)

2.7 3.7 4.23.2 4.7 5.2

CODE = 0 x 800CODE = 0 x FFF

CODE = 0 x 000

200

230

220

260

250

280

290SUPPLY CURRENT vs. TEMPERATURE

MAX

5742

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6

TEMPERATURE (°C)

SUPP

LY C

URRE

NT (µ

A)

-40 40-20 0 60 80 100

VDD = 5.5V

VDD = 3.6V

270

240

210

20 120

0

100

50

200

150

250

300

2.0 3.5 4.02.5 3.0 4.5 5.0 5.5

POWER-DOWN SUPPLY CURRENTvs. SUPPLY VOLTAGE

MAX

5742

toc1

4

SUPPLY VOLTAGE (V)

POW

ER-D

OWN

SUPP

LY C

URRE

NT (n

A)

0

200

100

500

400

300

800

700

600

900

0 21 3 4 5

SUPPLY CURRENT vs. CS INPUT VOLTAGE

MAX

5742

toc1

5

CS INPUT VOLTAGE (V)

SUPP

LY C

URRE

NT (µ

A)

VDD = +3V

VDD = +5V

Typical Operating Characteristics (continued)(VREF = VDD, TA = +25°C, unless otherwise noted.)

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6 _______________________________________________________________________________________

FULL-SCALE SETTLING TIME (VDD = +5V)

MAX5742 toc17

VOUT_1V/div

1µs/div

CODE 000 TO FFF HEXRL = 5kΩCL = 200pF

VSCLK, 5V/div

FULL-SCALE SETTLING TIME (VDD = +5V)

MAX5742 toc18

VOUT_1V/div

1µs/div

CODE FFF TO 000 HEXRL = 5kΩCL = 200pF

VSCLK, 5V/div


HALF-SCALE SETTLING TIME(VDD = +3V)

MAX5742 toc19

VOUT_1V/div

1µs/div

VSCLK, 5V/div

CODE 400 TO C00 HEXRL = 5kΩCL = 200pF

HALF-SCALE SETTLING TIME(VDD = +3V)

MAX5742 toc20

VOUT_1V/div

1µs/div

VSCLK, 5V/div

CODE C00 TO 400 HEXRL = 5kΩCL = 200pF

EXITING POWER-DOWN(VDD = +5V)

MAX5742 toc21

VOUT_1V/div

5µs/div

VSCLK, 5V/div

CODE 800 HEX

DIGITAL-TO-ANALOG GLITCH IMPULSE(VDD = +5V)

MAX5742 toc22

VOUT_AC-COUPLED,20mV/div

1µs/div

CODE 7FF HEX to 800 HEX

SCLK, fSCLK = 500kHz2V/div

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MAX5742 toc23


1µs/div

CODE 7FF HEX to 800 HEX

SCLK, fSCLK = 500kHz,2V/div


MAX5742 toc24


1µs/div

CODE 800 HEX to 7FF HEX

SCLK, fSCLK = 500kHz2V/div

____________________________Typical Operating Characteristics (continued)(VREF = VDD, TA = +25°C, unless otherwise noted.)


MAX5742 toc25


1µs/div

CODE 800F HEX to 7FF HEX

SCLK, fSCLK = 500kHz,2V/div

POWER-ON RESET, FAST RISE TIME(VDD = +5V)

MAX5742 toc26


20µs/div

VDD RISE TIME = 20µs

VDD2V/div

POWER-ON RESET, SLOW RISE TIME(VDD = +5V)

MAX5742 toc27


40µs/div


VDD2V/div

POWER-ON RESET, FAST RISE TIME(VDD = +3V)

MAX5742 toc28


20µs/div


VDD2V/div

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8 _______________________________________________________________________________________

POWER-ON RESET, SLOW RISE-TIME(VDD = +3V)

MAX5742 toc29


40µs/div


VDD2V/div

CLOCK FEEDTHROUGH(VDD = +5V)

MAX5742 toc30


2µs/div

SCLK,2V/div

CODE = 800 HEX,2µs/divfSCLK = 50kHz


CLOCK FEEDTHROUGH(VDD = +3V)

MAX5742 toc31


2µs/div

SCLK,2V/div

CODE = 800 HEX,2µs/divfSCLK = 50kHz

LINE TRANSIENT RESPONSE(VDD = +5V)

MAX5742 toc32


20µs/div

VDD,AC-COUPLED,100mV/div

LINE TRANSIENT RESPONSE(VDD = +3V)

MAX5742 toc33


20µs/div

VDD,AC-COUPLED,100mV/div

CROSSTALK (VDD = +5V)MAX5742 toc34

VOUTB,AC-COUPLED,2mV/div

4µs/div

CODE FFF HEX to 00B HEX

VOUTA,2V/div

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Detailed DescriptionThe MAX5742 contains four 12-bit, voltage-output, low-power digital-to-analog converters (DACs). Each DACemploys a resistor string architecture that converts a12-bit digital input word to an equivalent analog outputvoltage proportional to the applied reference voltage.The MAX5742 shares one reference input (REF)between all four DACs. The MAX5742 includes rail-to-rail output buffer amplifiers for each DAC, and inputlogic for simple microprocessor (µP), and CMOS inter-faces. The power-supply range is from +2.7V to +5.5V(Functional Diagram). The MAX5742’s reference inputaccepts a voltage range from 0 to VDD. In power-downmode the reference input is high impedance. TheMAX5742 is compatible with the 3-wire SPI, QSPI,MICROWIRE and DSP serial interface with Schmitt-trig-gered logic inputs.

Reference Input and DAC Output RangeThe reference input accepts positive DC and AC sig-nals. The voltage at REF sets the full-scale output volt-age of the four DACs. The reference input voltagerange is 0 to VDD. The impedance at REF is 45kΩ. Thevoltage at REF can vary from GND to VDD. The outputvoltages (VOUT_) are represented by a digitally pro-grammable voltage source as:

VOUT_ = (VREF D) / 212

where D is the decimal equivalent of binary DAC inputcode ranging from 0 to 4095. VREF is the voltage atREF.

Output Buffer AmplifiersAll DACs are internally buffered at the output. Thebuffer amplifiers have both rail-to-rail common mode

and (GND to VREF) output voltage range. The buffersare unity-gain stable with CL = 200pF and RL = 5kΩ.Buffer amplifiers are disabled during power-up andindividual DAC outputs are shorted to GND through a100kΩ resistor. Buffer amplifiers can individually or alto-gether be powered-down by programming the inputregister control bits. During power down, contents ofthe input and DAC registers remain the same. Onwake-up, all DAC outputs are restored to their pre-power-down voltage values.

Power-Down ModeIn power-down mode, the DAC outputs are pro-grammed to one of three output states, 1kΩ, 100kΩ, orfloating (Table 1). The REF input is high impedance(2MΩ typ) to conserve current drain from the systemreference; therefore, the system reference does nothave to be powered-down. The DAC outputs return tothe values contained in the registers when brought outof power-down. The recovery time, from total power-down to power-up, is 8µs. This extra time is needed toallow the internal bias to wake-up. Power-down modereduces current consumption to 0.3µA.

3-Wire Serial InterfaceThe MAX5742 digital interface is a standard 3-wire con-nection compatible with SPI/QSPI/MICROWIRE/DSPinterfaces. The chip-select input (CS) frames the serialdata loading at DIN. Immediately following CS high-to-low transition, the data is shifted synchronously andlatched into the input register on the falling edge of theserial clock input (SCLK). After 16 bits have beenloaded into the serial input register, it transfers its con-tents to the DAC latch. CS may then either be held lowor brought high. CS must be brought high for a mini-mum of 80ns before the next write sequence, since a

Pin Description

PIN NAME FUNCTION

1 CS Chip-Select Input

2 SCLK Serial-Clock Input

3 VDD Power-Supply Input

4 GND Ground

5 DIN Serial Data Input

6 REF External Reference Voltage Input

7–10 OUTA –OUTDDAC Voltage Outputs. Power-on reset sets DAC registers to zero, and internally connectsOUT to GND with 100kΩ resistor.

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10 ______________________________________________________________________________________

write sequence is initiated on a falling edge of CS. Notkeeping CS low during the first 15 SCLK cycles dis-cards input data. The serial clock (SCLK) can idleeither high or low between transitions.

The MAX5742 has two internal registers per DAC, theinput register and the DAC register. The input registerholds the data that is waiting to be shifted to the DACregister. All input registers can be loaded withoutupdating the output. This function is useful when all out-puts need to be updated at the same time. The inputregister can be made transparent. When the input reg-ister is transparent, the data written into DIN loadsdirectly to the DAC register and the output is updated.The DAC output is not updated until data is written tothe DAC register. See Table 2 for a list of serial-inter-face programming commands.

Power-On Reset (POR)The MAX5742 has an internal POR circuit. At power-up allDACs are powered-down and OUT_ is terminated toGND through 100kΩ resistors. Contents of input and DACregisters are cleared to all zero. An 8µs recovery timeafter issuing a wake-up command is needed before writ-ing to the DAC registers. Power-down mode control com-mands can be applied immediately with no recovery time.

C3-C0 are control bits. The data bits D11 to D0 are instraight binary format. All zeros correspond to zeroscale and all ones correspond to full scale.

Digital InputsThe digital inputs are compatible with CMOS logic. Inorder to save power and reduce input to output coupling,SCLK and DIN input buffers are powered down immedi-ately after completion of shifting 16 bits into the input shiftregister. A high to low transition at CS powers up SCLKand DIN input buffers.

EXTENDEDCONTROL

DATA BITS

C3 C2 C1 C0 D11–D5 D4 D3 D2 D1 D0

DESCRIPTION FUNCTION

1 1 1 1 X 0 0 0 0 0 DAC A DAC O/P, wakeup

1 1 1 1 X 0 0 0 0 1 DAC A Floating output

1 1 1 1 X 0 0 0 1 0 DAC A Output is terminated with 1kΩ

1 1 1 1 X 0 0 0 1 1 DAC A Output is terminated with 100kΩ

1 1 1 1 X 0 0 1 0 0 DAC B DAC O/P, wakeup

1 1 1 1 X 0 0 1 0 1 DAC B Floating output

1 1 1 1 X 0 0 1 1 0 DAC B Output is terminated with 1kΩ

1 1 1 1 X 0 0 1 1 1 DAC B Output is terminated with 100kΩ

1 1 1 1 X 0 1 0 0 0 DAC C DAC O/P, wakeup

1 1 1 1 X 0 1 0 0 1 DAC C Floating output

1 1 1 1 X 0 1 0 1 0 DAC C Output is terminated with 1kΩ

1 1 1 1 X 0 1 0 1 1 DAC C Output is terminated with 100kΩ

1 1 1 1 X 0 1 1 0 0 DAC D DAC O/P, wakeup

1 1 1 1 X 0 1 1 0 1 DAC D Floating output

1 1 1 1 X 0 1 1 1 0 DAC D Output is terminated with 1kΩ

1 1 1 1 X 0 1 1 1 1 DAC D Output is terminated with 100kΩ

1 1 1 1 X 1 0 0 0 0 DAC A-D DAC O/P, wakeup

1 1 1 1 X 1 0 0 0 1 DAC A-D Floating output

1 1 1 1 X 1 0 0 1 0 DAC A-D Output is terminated with 1kΩ

1 1 1 1 X 1 0 0 1 1 DAC A-D Output is terminated with 100kΩ

Table 1. Power-Down Mode Control

X = Don’t care

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Applications InformationUnipolar Output

The typical application circuit (Figure 3) shows theMAX5742 configured for a unipolar output, where theoutput voltages and the reference inputs have thesame polarity. Table 3 lists the unipolar output codes.

Bipolar OutputThe MAX5742 can be configured for bipolar operationusing a dual supply op amp (Figure 4). The transferfunction for bipolar operation is:

where NB is the decimal value of the DACs binary inputcode. Table 4 shows digital codes (offset binary) andcorresponding output voltages for the circuit in Figure 4.

Power Supply and Layout ConsiderationsCareful PC board layout is important for optimal systemperformance. To reduce noise injection and digital feed-through, keep analog and digital signals separate.Ensure that that the return path from GND to the supplyground is short and low impedance. Use a groundplane. Bypass VDD to GND with a 0.1µF capacitor asclose as possible to VDD.

V V2NB4096OUT REF=

−

1

CONTENTS OF SHIFT REGISTER

D15 (MSB) D0 (LSB)

C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 1. 16-Bit Input Word

SCLK X 1 2 3

tCL

tOS

tCSPWH tCSS tCSH

tOH

tCH

4 5 6 16 X

X C3 C2 C1 C0 D11 D10 D0D1 XDIN

CS

Figure 2. Timing Diagram

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12 ______________________________________________________________________________________

CONTROL DATA BITS

C3 C2 C1 C0 D11–D0DAC FUNCTION

0 0 0 0 X A Input register transparent, data shifted directly to DAC register, OUTA updated

0 0 0 1 X B Input register transparent, data shifted directly to DAC register, OUTB updated

0 0 1 0 X C Input register transparent, data shifted directly to DAC register, OUTC updated

0 0 1 1 X D Input register transparent, data shifted directly to DAC register, OUTD updated

0 1 0 0 X A Data shifted to input register, OUTA unchanged

0 1 0 1 X B Data shifted to input register, OUTB unchanged

0 1 1 0 X C Data shifted to input register, OUTC unchanged

0 1 1 1 X D Data shifted to input register, OUTD unchanged

1 0 0 0 X A Shift data from input register to DAC register, OUTA updated

1 0 0 1 X B Shift data from input register to DAC register, OUTB updated

1 0 1 0 X C Shift data from input register to DAC register, OUTC updated

1 0 1 1 X D Shift data from input register to DAC register, OUTD updated

1 1 0 0 X A–DInput registers transparent, data shifted directly to DAC registers, OUTA–OUTDupdated

1 1 0 1 X A–D Data shifted to input registers, OUTA–OUTD unchanged

1 1 1 0 X A–D Shift data from input registers to DAC registers, OUTA–OUTD updated

X = Don’t care

Table 2. Serial-Interface Programming Commands

DAC_

REF VDD

+2.7V TO +5.5V

OUT_

GND

IN OUT

GND

MAX6050

MAX5742

Figure 3. Typical Operating Circuit, Unipolar Output

DAC_

MAX5742

REF

V-

V+

VOUT

R1 R2

OUT_

R1 = R2

VDD

+2.7V TO +5.5V

Figure 4. Bipolar Output Circuit

MA

X5

74

2


______________________________________________________________________________________ 13

DAC CONTENTS ANALOG OUTPUT

1111 1111 1111

1000 0000 0001

1000 0000 0000

0111 1111 1111

0000 0000 0001

0000 0000 0000 0

DAC CONTENTS ANALOG OUTPUT

1111 1111 1111

1000 0000 0001

1000 0000 0000 0

0111 1111 1111

0000 0000 0001

0000 0000 0000 VREF

14096

−VREF

+

VREF20472048

+

VREF1

2048

−VREF1

2048

−VREF20472048

Table 3. Unipolar Code Table Table 4. Bipolar Code Table

Chip InformationTRANSISTOR COUNT: 14,458

PROCESS: BiCMOS

VREF40954096

VREF20494096

VREF2

VREF20474096

MA

X5

74

2


14 ______________________________________________________________________________________

DACREGISTER A

DACREGISTER B

DACREGISTER C

DACREGISTER D

12-BIT DAC AOUTPUTBUFFER

OUTPUTBUFFER

OUTPUTBUFFER

OUTPUTBUFFER

INPUT CONTROLLOGIC AND SHIFT

REGISTER

POWER-DOWNCONTROL LOGIC

RESISTORNETWORK

CS SCLK DIN GND

OUTB

OUTA

VDD REF

OUTD

OUTC

INPUTREGISTER A

INPUTREGISTER B

INPUTREGISTER C

INPUTREGISTER D

RESISTORNETWORK

RESISTORNETWORK

RESISTORNETWORK

12-BIT DAC B

12-BIT DAC C

12-BIT DAC D

MAX5742

Functional Diagram

MA

X5

74

2


Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15

© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

10LU

MA

X.E

PS

PACKAGE OUTLINE, 10L uMAX/uSOP

11

21-0061 IREV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

TOP VIEW

FRONT VIEW

1

0.498 REF0.0196 REFS6∞

SIDE VIEW

α

BOTTOM VIEW

0∞ 0∞ 6∞

0.037 REF

0.0078

MAX

0.006

0.043

0.118

0.120

0.199

0.0275

0.118

0.0106

0.120

0.0197 BSC

INCHES

1

10

L1

0.0035

0.007

e

c

b

0.187

0.0157

0.114

H

L

E2

DIM

0.116

0.114

0.116

0.002

D2

E1

A1

D1

MIN

-A

0.940 REF

0.500 BSC

0.090

0.177

4.75

2.89

0.40

0.200

0.270

5.05

0.70

3.00

MILLIMETERS

0.05

2.89

2.95

2.95

-

MIN

3.00

3.05

0.15

3.05

MAX

1.10

10

0.6±0.1

0.6±0.1

ÿ 0.50±0.1

H

4X Se

D2

D1

b

A2 A

E2

E1L

L1

c

α

GAGE PLANE

A2 0.030 0.037 0.75 0.95

A1

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

http://www.maxim-ic.com/packages

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