MEWS26 October 24, 2013

IR HiRel Space Product update

Tiva Bussarakons Max Zafrani

2

International Rectifier Globally

El Segundo, CA

TS16949,

ISO9001, JANS,

ISO14001

Newport, Wales, UK

TS16949

ISO14001

ISO9001

Temecula, CA

TS16949

JANS

ISO14001

San Jose, CA

ISO9001

MILPRF38534

Mesa, AZ

TS16949

ISO9001

ISO14001

Leominster, MA

ISO14001

ISO9001

MILPRF38534

MILPRF19500

JANS

Tijuana,

Mexico

TS16949,

ISO9001

ISO14001

• 8 Manufacturing Centers, ► 11 Design Centers

■ Global Service and Technical Assistance Centers

St Paul, MN

Pavia, Italy

Provence, France

Rhode Island

Reigate, U.K.

Irvine, CA

Japan

Skovlunde,

Denmark

Durham, NC

Singapore

Shanghai,

China

Shenzen,

China Frankfurt,

Germany

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HiRel Product Technologies

• DC/DC converters

o 5W to >250W output power, higher power with parallel operations

o Converter efficiency of up to 92%

o PCB assembly style and enclosed aluminum housing available

o DSCC class H and K SMDs

o Single, dual, triple, and quad outputs

• Hybrids/Modules

o Application specific hybrids ie: Solid State Relays, AC Switches, etc

o Custom packaging ie: hermetic and near hermetic

o Extended temperature range, extensive screening operation

o Rad Hard Low Drop Out Regulators

o Half bridges

o H-bridges

o 3-Phase bridges

• Discrete Semiconductors

o RAD-Hard MOSFETs and MOSFET Drivers

o Logic Level RAD-Hard MOSFETs

o Hermetic MOSFETs and IGBTs

o Schottky Rectifiers

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1st generation rad-hard MOSFETs with excellent total dose performance

2nd generation • Reduced RDS(on) • Reduced QG • Improved SEGR/SEB

3rd generation • Best in class RDS(on) • Improved SEE SOA • Shape die to better fit

packages for optimum RDS(on)/QG performance

1st logic level gate drive • Developed specifically

for POL buck regulators and synchronous rectification to improve efficiency

• Comparable TID/SEE to R6

Logic level gate drive Developed with further reduction in RDS(on) and gate charge for low voltage POL and synchronous rectification designs with comparable TID and SEE performance to R6

N: 100 to 500V P: 60 to 200V

N: 30V to 250V P: 60 to 200V

N: 100 to 600V N: 60 to 250V P: 60V

N: 20V to 60V

Hexagon cells 5 µm feature size

Stripe planar technology 1.5 µm feature size

Stripe planar technology 0.6 µm feature size

Stripe planar technology 0.6 µm feature size

Trench technology 0.5 µm feature size

1989 1998 2002 2005 2013

R5 , R6 AND R7 TECHNOLOGY

(Stripe planar technology)

Development History of IR’s Rad-Hard MOSFETs

R8 R7

5 µm 1.5 µm 0.6 µm 0.5 µm

5 5

Rad-Hard MOSFET Voltage vs Generation

Gen4

• -60V to -200V

• 100K to 1000K Rads

R5

• -30V to -200V

• 100K to 1000K Rads

BVDSS

- 200V

- 100V

- 60V

- 30V

‘89 ‘02 >> ‘06 ‘08 ‘13

Gen4 R5

R7

BVDSS

600V

500V

400V

250V

100V

60V

30V

‘89 ‘02 >> ‘06 ‘08 ‘13

Gen4

R5

R6

R7

R8

Gen4

• 30V to 500V

• 100K to 1000K Rads

R5

• 30V to 250V

• 100K to 1000K Rads

R6

• 100V to 600V

• 100K to 300K Rads

N-Channel P-Channel

R6 (Dev)

• -60V to -200V

• 100K to 300K Rads

R7 Logic Level

• -60V to -100V

• 100K to 300K Rads

R7 Logic Level

• 60V to 250V

• 100K to 300K Rads

R8 Trench

• 20V to 60V

• 100K to 300K Rads

Three New Discrete Products from IR

• R8 - New Rad-Hard MOSFETs

• SMD 0.2 - New Low Power Package

• SupIR SMD-2 - New High Power Package

Radiation Hardened MOSFETs

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Extended Performance Characterization

• Extended SOA curves for linear applications

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FEATURES:

20 V BVDSS

±12V BVGSS

100 Krads to 300 Krads TID

SEE immune with LET of 81 MeV-cm2/mg

Logic level gate drive similar to R7

RDS(on) -- 12 mΩ typ./15 mΩ max.

QG -- 18 nC typ./24 nC max.

Available in SMD 0.2, the industry’s smallest surface-mount power package and TO-39

o IRHLNM87Y20

o IRHLF87Y20

Rad-Hard N Channel MOSFET Trench Technology

R8 New Rad-Hard MOSFET for POL Applications

Part Number TID Package BVDSS ID RDS(on) max QG max ƟJC

IRHNM87Y20SCS 100Krads SMD 0.2 20V 17A 15 mΩ 24 nC 3.5 °C/W

IRHNM83Y20SCS 300Krads SMD 0.2 20V 17A 15 mΩ 24 nC 3.5 °C/W

IRHLF87Y20SCS 100Krads TO-39 20V 12A 32 mΩ 27 nC 8.0 °C/W

IRHLF83Y20SCS 300Krads TO-39 20V 12A 32 mΩ 27 nC 8.0 °C/W

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R8 Typical Single Event Effects (SEE) Performance

0

5

10

15

20

25

0 2 4 6 8 10 12

VD

S (V

)

VGS (V)

IRHLC87Y20 Typical SEE SOA

BR

I

AU

ION LET Energy Range VDS (V)

MeV/(mg/ cm2)

MeV µm VGS = 0V VGS = -1V VGS = -3V VGS = -5V VGS =-10V

Br 36.93 298 38.2 18 18 8 4

I 59.72 320 31 18 18 12 8

Au 81.43 332 27.5 18 18 12 6

• Tests performed at Brookhaven National Laboratory

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R8 Typical POL Application

• Designed for Point of Load (POL) voltage regulators, general purpose switching and linear

voltage regulator applications

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• R8 offers efficiency improvement over R5 (refer to efficiency plots below)

o 1.2V output: 3.9 to 6.0%

o 3.3V output: 1.5 to 3.1%

• R5: IRHNJ57Z30, 30V - RDS(on) = 20 mΩ max, QG = 65 nC max

• R8: IRHNM87Y20, 20V - RDS(on) = 15 mΩ max, QG = 24 nC max

R8 Increases Efficiency Performance, R8 vs. R5

3.9%

6.0%

1.5% 3.1%

Selection of Hermetic Packages

Low Power: 0.6W to 29W

High Power: 75W to 300W

TO-39 UB LCC-6 LCC-18 LCC-28

SMD-0.5 TO-257

Also: Low Ohmic/Tab-less

SMD-1 SMD-2 TO-254

Also: Low Ohmic/Tab-less

MO-036

NEW

NEW

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SMD-0.2

SupIR SMD-2™

(NX)

(NM/U8)

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• Industry’s smallest surface mount power package

• 50% smaller than SMD 0.5

• 75% lighter (only 0.25 g)

• Aluminum nitride (AlN) case

• R5 and R7 250V devices are in qualification

• Patented design (U.S. Patent No. 7,508,506 B2)

0.2” (5 mm)

0.3” (8 mm)

0.25g

0.3” (8 mm)

0.4” (10 mm)

1.0 g

SMD 0.2

SMD 0.5 NEW

New SMD 0.2 Package for Low Power MOSFETs

A space qualified compact surface mount package only from IR for low power applications

DLA JANS Qualified Devices

• JANSR2N7503U8 (IRHNM57110SCS), R5, 100V, N Channel

• JANSR2N7506U8 (IRHNM597110SCS), R5, 100V, P Channel

• IRHNM77110SCS (JANSR2N7609U8), R7, 100V, N Channel – in process

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New SMD 0.2 Package Construction

Internal View Top View Bottom View

Lid – Kovar or ceramic Cu Metalization O-Ring - Kovar

Wall/Bottom - AlN

0.305”L x0.21”W x 0.10”H

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SupIR SMD-2™ - Latest packaging Innovation

from International Rectifier for Space Grade Rad-Hard Power MOSFETs and Power Rectifiers

FEATURES: • JANS qualified IAW MIL-PRF-19500

• Improved performances compared to the nearest packaging solutions, SMD-2 package with a carrier

35% smaller, 0.376 in2 vs. 0.583 in2

45% lighter. 2.8 g vs. 5.1 g

Lower thermal resistance by 0.25°C/W

Lower package resistances by 30%, 0.68 Ω vs. 0.97 Ω

Lower parasitic inductance by 76%, 0.52 µH vs. 2.19 µH

Yield a higher current rating, 82A vs. 56A

• Facilitates assembly design and reduces costs

• Accommodates the largest IR’s size 6 die

New SupIR SMD-2™ Package

SupIR SMD-2™

SMD-2

NEW

1.127”

0.710” 0.417” (37%)

Carrier

0.530”

0.528”

37% Foot Print Reduction

SMD-2 with Carrier

= +

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SupIR SMD-2™ - Package Construction/Qualification

JANS Qualified IAW MIL-PRF-19500

• X-ray, Wire Bond Pull, Die shear, Leak testing

• PIND

• RGA

• Salt atmosphere

• 300C bake

• Barometric pressure (500V @ 33 Torr)

• 500 temperature cycles (-55C to 150C, air to air)

• Solderability

• Thermal shock 15 cycle (-55C to 125C, liquid to liquid)

• Terminal strength

• Moisture resistance

• Shock, vibration, constant acceleration

• Resistance to soldering heat

• S level qualified – HFB60HNX20SCS

• Available soon

Frame – Alumina, 94%

Seal Ring - Kovar

Base – 85% W/ 15% Cu Lead – OFHC Cu

Lid - Kovar

Products Qualification

• HFB60HNX20SCS, 35ns, 200V, 60A -- released

• IRHNX67160SCS, R6, 100V – in process

• IRHNX67164SCS, R6, 150V – in process

• IRHNX67260SCS, R6, 200V – in process

• IRHNX67264SCS, R6, 250V – in process

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SupIR SMD-2™ In-Circuit Benefits Example

• Primary H-bridge with four MOSFETs and a secondary Hy-Bridge (current doubler) stage with two MOSFETs for synchronous rectification

• SMD-2 with leads can only dissipate about 2W

• SMD-2 would require parallelling MOSFETs which has a penalty in switching losses and in the snubber size needed to dampen the energy from the stray inductance of the transformer that may cause excess stress to the MOSFET due to their output capacitance

• SupIR SMD-2™ can dissipate 4W, no need for

parallel:

6 MOSFETs instead of 12

IR DC-DC converter EGA Series High efficiency 300W EPC for GaN SSPA SupIR-SMD-2™

Benefits of SupIR SMD-2™

Load condition: V1: 50V, V2: +8V 0A, V3: -8V 0A

EGA Efficiency (Vin 50V, V1=50V)

75.0%

80.0%

85.0%

90.0%

95.0%

0 1 2 3 4 5 6 7

V1 Current [A]

Efficiency

+25°C

-40°C

-20°C

+75°C

Benefits of SupIR SMD-2™

• 2x power dissipation

• 6 MOSFETs instead of 12

• 1.4% increase in efficiency lower cost

• 18 cm² smaller

• 40 g lighter PCB-area

• less circuit complexity

• higher reliability

SupIR SMD-2™ vs. SMD 2 with Leads

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GIDEP SYSTEM

Failure Experience Data (FED)

Diminishing Manufacturing

Sources & Material

Shortages (DMSMS)

Product Information Data

GIDEP DATABASE STRUCTURE

CENTRAL DATABASE for Information and Data Exchange

Systems

- Product Alert - Product Advisory

- EOL - Last Time Buy

- Product Change Notice - Process Change Notice

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GIDEP SYSTEM

Issued GIDEP INFORMATION AND DATA records are posted and accessible on IR Web Site:

http://www.irf.com/product-info/hi-rel/alerts.html

Systems

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Where is it safe to operate the MOSFET in the Id, Vds and pulse width domain? The straight SOA lines assume that power dissipation is uniform under all power conditions However power dissipation is not uniform in the MOSFET under all power conditions Local thermal runaway in the MOSFET’s linear mode of operation limits the SOA

SOA Curve and Linear Mode Operation

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Better method of assigning SOA Dr. P. Spirito [1] et. Al. suggest —

As transconductance increases (e.g. in shorter channel lengths, from planar to trench devices [2]): 1. the drain current temperature

dependence can become positive like power BJTs

2. the likelihood of hot spots (thermal instability) increases

3. and the SOA degrades

How is the new method done?

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Transfer Curves Per Generation

Shorter Channel Length Stronger Temperature Dependence of Drain Current

Greater Propensity for Severe Thermal Instability

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R5 200V P-Channel Spirito versus Actual (new DC curves)

Measured

Curve

Spirito Curve

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Preventing Linear Mode failure

• Use older generation MOSFETs with lower gain when possible

• Select devices with low ZTC point

• Make sure that the MOSFET Zero Temperature Coefficient (ZTC) point is low or operate above it

• Avoid operation near the SOA boundary

• Choose smaller of two devices as it will be less sensitive to thermal current focusing

ZTC

Safe

Un-Safe