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Solid-State Electronics 49 (2005) 1833–1840

Investigation of SiO2/HfO2 gate stacksfor application to non-volatile memory devices

J. Buckley a,*, B. De Salvo a, G. Ghibaudo b, M. Gely a, J.F. Damlencourt a,F. Martin a, G. Nicotra c, S. Deleonibus a

a CEA-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, Franceb IMEP-CNRS/INPG, 23 av. des Martyrs, Grenoble, 38016 Grenoble Cedex 1, France

c Microsystems and Microelectronics Institute (CNR—IMM), Stradale Primosole, 50, 95121 Catania, Italy

Available online 15 November 2005

The review of this paper was arranged by E. Gerritsen, P. Masson and P. Mazoyer

Abstract

Engineering of the tunnel barrier of non-volatile memories is addressed in this paper. The strong potential of multilayer stacks forreducing the programming times of these devices, without altering their retention characteristics, is studied. To this aim, experimentalresults showing the improved field sensitivity of the gate current of MOS devices with SiO2/HfO2 gate stacks compared to SiO2 ofidentical electrical thickness (EOT) are presented. Simulations of the corresponding tunnelling currents are also reported. Our electri-cal measurements suggest that it is of great interest to investigate the use of SiO2/HfO2 stacks as tunnel barriers for NVMs. Theseexperimental results on double-layer stacks allow to confirm experimentally a conduction principal that could be used in symmetricaltriple-layer SiO2/high-k/SiO2 tunnel barriers, thus allowing an advantageous behaviour in both conduction directions. Further simu-lations are presented in order to evaluate the best parameters that the high-k layer should have in order to lead to better performancethan a SiO2 tunnel barrier. They suggest that if the high-k has 1.5–2.0 eV conduction band offset compared to Si its relative effectivemass and dielectric constant should meet the constraint: ehigh-k �

ffiffiffiffiffiffiffiffiffiffiffiffiffiffimhigh�k

p P 5 (mhigh-k, relative electron mass; ehigh-k, relative dielectricconstant).� 2005 Elsevier Ltd. All rights reserved.

Keywords: High-k; HfO2; Tunnel oxide

1. Introduction

In current flash non-volatile memory (NVM) devices,the tunnel oxide thickness is of about 7–8 nm and wouldbe difficult to downscale in the future if 10 year data reten-tion is still wanted [1]. This requirement limits furtherimprovement of device performance in terms of program-ming speed and operating voltages. It is therefore necessaryto find innovative solutions in order to bypass this restric-tion. A promising one is the use of multilayer dielectricstacks to practice tunnel barrier engineering. The main

0038-1101/$ - see front matter � 2005 Elsevier Ltd. All rights reserved.

doi:10.1016/j.sse.2005.10.005

* Corresponding author. Tel.: +33 438 78 23 29; fax: +33 438 78 54 59.E-mail address: julien.buckley@cea.fr (J. Buckley).

potential of these stacks would be to allow shorter writ-ing/erasing times and/or smaller operating voltages thanthe ones obtained using conventional SiO2 without alteringthe 10 year data retention constraint.Multi-layer tunnel barriers for flash memory applica-

tions were first introduced by Likharev [2] in 1998 withthe concept of ‘‘Crested Barriers’’ (CBs). In Ref. [3] hedemonstrated through tunnelling current simulations thatthe use of a triple-layer stack (using a Si3N4(4 nm)/AlN(5 nm)/Si3N4(4 nm) combination) would enable farbetter performance than today�s single layer SiO2 barriers,in terms of programming speed and data retention. Theseimprovements were due to the high slope of the simulatedcurrent–voltage characteristic of such a stack compared to

Fig. 1. Conduction band edge diagrams of three different tunnel barrierfor low and high fields corresponding respectively to the cases ofprogramming and retention. (a) SiO2 barrier (b) Crested Barrier (c-top)k-Crested Barrier (c-bottom) crested profile of the dielectric constant of ak-Crested Barrier.

Fig. 2. Samples developed in this work, i.e. single- and double-layertransistors with thermal SiO2 and ALD HfO2.

1834 J. Buckley et al. / Solid-State Electronics 49 (2005) 1833–1840

one layer of silicon oxide. This can be understood bycomparing the conduction band edge diagrams of Fig. 1aand b. The transparency of a SiO2 barrier changes slowlywith an applied field because its highest point is close tothe electron source and remains unaffected (Fig. 1a). Inthe case of a barrier with a ‘‘crested’’ conduction band edgeprofile, the maximum height of the barrier can be lowered(barrier lowering in Fig. 1b) and allows the transparencyand thus the current to change much faster between lowand high fields.Other authors have shown the possibility of achieving

high performance by using barriers consisting of low-k/high-k/low-k combinations. In these cases, the low-k oxidegenerally presented was SiO2, which has the importantadvantage of guaranteeing a good quality interface withthe Si channel. Experimental data for SiO2/ZrO2 stackswas shown in Ref. [4]. It was also shown experimentally[5] that the use of a SiO2/HfO2 tunnel barrier in a NVMmemory cell favoured low programming voltages. Thiscan be understood by the fact that between low and highfields, the tunnelling distance for electrons is stronglyshortened as illustrated in Fig. 1c. We have decided to callsuch a barrier a k-crested barrier (k for relative dielectricconstant) because it is characterized by the presence of ahigh-k in its central layer and lower-k dielectrics on thesides as shown in the graph Fig. 1c (bottom).In Ref. [6], we presented a theoretical analysis of both

‘‘Conduction Band–Crested Barriers’’ and ‘‘Dielectric

Constant–Crested Barriers’’ in view of their applicationto floating-gate non-volatile memory devices. The mainconclusion was that low-k/high-k/low-k dielectric stackcombinations are very good candidates as a tunnel dielec-tric for NVMs.In this paper, we present experimental results that

clearly show the improved field sensitivity of the gate cur-rent of MOS devices with SiO2/HfO2 gate stacks comparedto SiO2 of identical EOT. These measurements suggest thepossibility of using similar structures for replacing the tun-nelling dielectric of NVMs. Simulations of the correspond-ing tunnelling currents are also reported.Further calculations were done as well in order to eval-

uate the best parameters that the high-k layer should havein order to lead to better performance than a SiO2 tunnelbarrier. They allow to show that if the high-k has 1.5–2.0 eV conduction band offset compared to Si its relativeeffective mass and dielectric constant only need to meetthe constraint: ehigh�k �

ffiffiffiffiffiffiffiffiffiffiffiffiffiffimhigh�k

p P 5 (mhigh-k, relative elec-tron mass; ehigh-k, relative dielectric constant).

2. Device description and experimental results

Very large (250 lm · 160 lm gate surfaces) single anddouble-layer high-k n-MOS transistors have been fabri-cated, using HfO2 and thermal SiO2 (see Fig. 2). Interfacial1.65 nm, 2.2 nm and 2.6 nm thick SiO2 layers were ther-mally grown on p-doped (1017/cm3) silicon substrates.Three nanometre thick hafnium oxide was deposited byatomic layer deposition (ALD) in a PulsarTM 2000 toolfrom ASM Microchemistry Ltd., using HfCl4 as a precur-sor. All transistor gates were fabricated with TiN coated byn+ degenerated poly-Si. High resolution TEM pictures of

-2 -1 0 2

0.005

0.01

C(F/m²)

Vg (V)-2 -1 0 2

0.005

0.01

C(F/m²) ref. A

ref. B

1Vg (V)

1

sample 2

sample 1

a b

Fig. 5. Fitting of experimental (empty circles) and simulated (solid lines)C–V curves for samples 1–2 in (a) and references A–B in (b).

Fig. 3. High resolution TEM analyses of samples 1 and 2 (corresponding to Fig. 5).

J. Buckley et al. / Solid-State Electronics 49 (2005) 1833–1840 1835

all fabricated samples are available in Fig. 3. The extractedEOTs of samples 1 and 2, are respectively, 2.3 nm and2.7 nm, allowing them to be comparable with referencesA and B.Experimental transport curves are shown in Fig. 4a for

both samples and the reference. These plots represent tun-nelling currents versus oxide field. The oxide field at a givengate voltage (Vg) was obtained by integration of the C–Vcurves of the samples between flat-band voltage and Vg(see Eqs. (1) and (2)). The EOTs of the stacks were

10-8

10-6

10-4

10-2

100

0 2 64 8 1010-8

10-6

10-4

10-2

100

10-8

10-6

10-4

10-2

0

10-6

10-4

10-2

0

0 2 64 8 100 22 64 8 10Fox (MV/cm)

Sample 2

Reference B

Reference A

Sample 1

Data

10-8

10-6

10-4

10-2

100

0 2 64 8 1010-8

10-6

10-4

10-2

100

10-8

10-6

10-4

10-2

100

10-6

10-4

10-2

100

0 2 64 8 100 2 64 8 10Fox (MV/cm)

Jg(A

/cm

² )Jg

(A/c

m² )

Simulations

Reference A

Sample 1

Sample 2

Reference B

a

b

Fig. 4. (a) Experimental transport curves (current versus equivalent oxideelectric field) for the stacks drawn in Fig. 1. (b) Corresponding simulatedtransport curves using the current model described in paragraph 3(parameters: U1 = 1.5 eV, meff = 0.17m0, k = 20 for HfO2, andU2 = 3.15 eV, meff = 0.5m0, k = 3.9 for SiO2).

obtained by fitting the C–V curves (Fig. 5a and b) with aquantum simulator

QG ¼Z V g

V FB

CðV ÞdV ð1Þ

F ox ¼QGeSiO2

ð2Þ

where QG is the gate charge; VFB is the flatband voltageand VG is the gate voltage.We can observe that samples 1 and 2 have higher levels

of current than their corresponding references for electricfields Fox > 7 MV/cm, therefore allowing a higher writingspeed if integrated in a device. For smaller fields (2–3 MV/cm), devices 1 and 2 have smaller leakage currentsthan the references, allowing better retention. The reasonfor this is illustrated in Fig. 6. For low fields the direct-tun-nelling current through the double-layer stacks is smallerthan the one through the reference SiO2 layer, due to itslarger physical thickness, as illustrated by the conductionband diagrams in Fig. 6a and c. For higher fields, the volt-age drop across the barrier is mainly applied to the interfa-cial SiO2, because of its low dielectric constant compared toa high-k. This leads to direct tunnelling through the inter-facial layer (Fig. 6b), which is shorter to cross than in thecase of the single layer sample (Fig. 6d). This principalwas already described in [5] by using tunnelling currentsimulations. It was noticed that there was an importantbarrier thinning of the stack at large fields which wasnamed VARIOT (VARIable Oxide Thickness). The resultsthat we presented here were for double-layer stacks andallowed to confirm experimentally the VARIOT principal.

Fig. 7. Simulation of a current–voltage (J–V) curve of a triple-layerbarrier compared to SiO2, (of same EOT) made by using the escapefrequency model described previously. In graph (a), simulations have beendone with a transfer matrix formalism for the transparency (inset: banddiagram of the SiO2/HfO2/SiO2 stack) and in graph (b) the Wentzel–Kramers–Brillouin approximation is used.

Fig. 6. (a) Conduction band diagram of electrons tunneling through aSiO2/high-k stack in the case of a small electric field. (b) Conduction banddiagram of electrons direct tunneling through the SiO2 layer of a SiO2/high-k stack and entering directly into the conduction band of the high-kin the case of large electric fields. (c) Conduction band diagram ofelectrons tunneling through SiO2 in the case of a small electric field. (d)Conduction band diagram of electrons direct tunneling through SiO2 inthe case of large electric fields.

1836 J. Buckley et al. / Solid-State Electronics 49 (2005) 1833–1840

A further step will be to design symmetrical stacks thatshould allow advantageous operation in both directions.

3. Gate tunnelling current simulations

Tunnelling current calculations are developed here fortriple-layer stacks for which simulation examples areshown. The model is then applied to the cases of thedouble-layer devices presented in Section 2.In this paper, the tunnelling probability of electrons is

determined by using a Wentzel–Kramers–Brillouin (WKB)formalism for the transparency of the involved dielectricstacks, which does not take into account electron reflections.In our case we used it for 2 and 3 layer stacks. Amethod thatincludes electron reflections is the Transfer Matrix formal-ism [7]. Such oscillations are difficult to observe experimen-tally because of electron scattering, so we did not findnecessary to include such a refinement at this level of inves-tigation. In Fig. 7a and b we show simulations for twodifferent stacks:

• SiO2 (5 nm).• SiO2 (1.5 nm)/HfO2(10 nm)/SiO2(1.5 nm).

The characteristics of 5 nm SiO2 are used in Fig. 7 as areference. The reason for this is that 5 nm SiO2 is consid-ered as being the smallest thickness that allows 10 year dataretention if direct tunneling is taken into account and SILCis neglected. According to [4] the maximal acceptable leak-age current for a given tunnel barrier is 10�16 A/cm2 for 10year data retention and 100 ls writing times are achievedfor a 10�2 A/cm2 tunneling current. In the case of 5 nm

SiO2, the tunneling current is worth 10�16 A/cm2 for a

1.5 V disturb voltage across the oxide and of about10�2 A/cm2 for a 5.5 V voltage drop. We will thereforedefine a retention voltage Vret = 1.5 V and a programmingvoltage Vprog = 5.5 V. They indicate that the WKB currentsimulations give results that are very close to the ones thatare obtained with transfer matrix, but without any oscilla-tions. Details on these simulations, when a WKB formal-ism is used, are explained hereafter.In the case of a triple-layer symmetrical dielectric stack

(see conduction band diagram in the inset of Fig. 7a) forwhich the middle layer has parameters m2, e2, U2 and t2,and both side layers parameters m1, e1, U1 and t1 (with:m1, m2: electron effective masses—e1, e2: permittivities—U1, U2: electron barrier heights compared to Si—t1, t2:layer thicknesses), the corresponding WKB transparencycan be expressed analytically as follows:

J. Buckley et al. / Solid-State Electronics 49 (2005) 1833–1840 1837

TWKBðm1;2;U1;2; t1;2; e1;2;E; V TBÞ

¼ exp �2ffiffiffi2

p

�h½I1ð1;E; V TBÞ þ I2ð1; 2;E; V TBÞ þ I3ð1; 2;E; V TBÞ

!

ð3Þwhere �h is the reduced Planck constant, E the electron en-ergy and VTB the voltage drop across the dielectric stacktunnel barrier and where

I1ð1;E;V TBÞ¼ I1ðm1;U1; t1;e1;E;V TBÞ

¼Z t1

0

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffim1 U1�qV TBCTB

xe1�E

� �H U1�qV TBCTB

xe1�E

� �sdx

ð4Þ

I2ð1;2;E;V TBÞ¼ I2ðm2;U2; t1;2;e1;2;E;V TBÞ¼Z t1þt2

t1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffim2 U2�qV TBCTB

t1e1þx� t1

e2

� ��E

� �H U2�qV TBCTB

t1e1þx� t1

e2

� ��E

� �sdx ð5Þ

I3ðm1;U1; t1;2; e1;2;E; V TBÞ ¼Z 2t1þt2

t1þt2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffim1 U1 � qV TBCTB

t2e2þ x� t2

e1

� �� E

� �H U1 � qV TBCTB

t2e2þ x� t2

e1

� �� E

� �sdx ð6Þ

where H is the Heaviside function and CTB is the tunnelbarrier capacitor per surface unit.In the case of electron injection from n-doped or p-

doped silicon, corresponding respectively to an accumula-tion or inversion layer, and if tunneling through SiO2 isconsidered, the current can be expressed as being [8]

JðV oxÞ ¼ fescQTWKB mSiO2 ;USiO2 ; tSiO2 ; eSiO2 ;EfundðQÞ; V oxð Þð7Þ

where fesc is the escape frequency; Q the inversion (electroninjection from p-type Si case) or accumulation (electroninjection from n-type Si case) charge; Vox the voltage dropacross the oxide; mSiO2 the electron effective mass in SiO2;eSiO2 ; the SiO2 permittivity; USiO2 ; the SiO2 electron barrierheight compared to Si; tSiO2 the oxide thickness; Vox theoxide voltage drop and Efund the electron fundamentalenergy in the silicon accumulation/inversion layer.The same formula can also be used for triple-layer

stacks

JSTACKðV STACKÞ¼ fescQTWKBðm1;2;U1;2; t1;2; e1;2;EfundðQÞ; V STACKÞ ð8Þ

where VSTACK is the voltage drop across the stack.The escape frequency of the electrons is calculated by

taking into account the electron reflections in the potentialwell at the Si/SiO2 interface. Because of these reflectionsthe electron wave function is stationary. According toRef. [9], the escape frequency for electrons can be expressedas being:

fesc ¼2

3

2Efundh

� �ð9Þ

where h is the Planck constant.

As described in Refs. [9,10], a variational approach canbe used to model the energy well at a Si/dielectric interface.The method of this approach consists in approximating thewave function of the electrons in the fundamental level byan analytical expression which is regarded as being a sta-tionary solution of the Hamiltonian at the Si/SiO2 inter-face. Efund is found by solving the derived equation andhas the following expression:

Efund ¼3�h2

q2mSi4�h2eSi

Q2�

ð10Þ

where �h is the reduced Planck constant; mSi the electronmass in Si and eSi the Si permittivity.

Current simulations of our samples based on the herepresented model are shown in Fig. 4b. They were carriedout by setting

I3 ¼ 0 ð11Þ

in order to adapt the calculations for dielectric stacks thatcontain only two layers. We can observe that they are veryclose to the measurements in the case of the SiO2 layers.For the SiO2/HfO2 stacks (samples 1 and 2), the transi-

tion of the current characteristics between direct tunnellingthrough both layers of the stack (Fox < 5 MV/cm) anddirect tunnelling through the SiO2 layer only (Fox >7 MV/cm) is a little sharper in the simulations than in theexperiments. This can be explained by the fact that theSiO2/HfO2 interface is in practice not as good quality asconsidered in the model. As a result, the electronic poten-tial transition at this interface isn�t as sharp for our devicesas in the simulation.

4. Study of SiO2/high-k/SiO2 tunnel barriers

We presented in the previous paragraphs experimentalresults that clearly showed the improved field sensitivityof the gate current of MOS devices with SiO2/HfO2 gatestacks compared to SiO2 of identical EOT. Simulationsof the corresponding tunnelling currents were alsoreported. These results suggest the possibility of using sim-ilar structures for replacing the tunnelling dielectric ofNVMs. As already reported in [5], a further step is to con-sider symmetrical SiO2/HfO2/SiO2 or SiO2/high-k/SiO2combinations. Such stacks should have a similar behaviourthan SiO2/HfO2 (respectively, SiO2/high-k) but in bothdirections and thus allow short erasing and programmingtimes.

a b

c d

Fig. 8. Simulations of current–voltage (J–V) curves of SiO2/high-k/SiO2stacks for different values of Uhigh-k and hhigh-k ranging from 3 to 14(respectively worth 3, 4, 5, 7, 10 and 14). (a) Uhigh-k = 1.0 eV (b) Uhigh-k =1.5 eV (c) Uhigh-k = 2.0 eV (d) Uhigh-k = 2.5 eV.

1838 J. Buckley et al. / Solid-State Electronics 49 (2005) 1833–1840

In this paragraph we present calculations that weredeveloped in order to evaluate the influence of the high-klayer properties (barrier height, dielectric constant andelectron effective mass) in SiO2/high-k/SiO2 stacks. As afirst approach, we address here the case of substrate injec-tion and thus retention in the case of a positive disturbvoltage as well as programming.For the stacks that we evaluate, the EOT of the middle

layer is fixed to 2 nm and each of the thicknesses of theSiO2 layers to 1.5 nm.A similar current formula to (8) can also be used for

SiO2/high-k/SiO2 stacks. Since the thicknesses of the SiO2layers are fixed at 1.5 nm the WKB stack transparencycan only vary with the parameters of the high-k

JSTACKðV STACKÞ¼ fescQTWKB mhigh�k;Uhigh�k; thigh�k; ehigh�k; V TB;E

�ð12Þ

where VTB is the voltage drop across the stack; mhigh-k theelectron effective masses; ehigh-k the permittivity; Uhigh-k theelectron barrier height compared to Si thigh-k, layerthickness.The TWKB term in (12) can then be developed as

TWKB mhigh�k;Uhigh�k; thigh�k; ehigh�k; V TB;E �

¼ exp �2

ffiffiffi2

p

�hISiO2ðV TB;EÞ þ Ihigh�k

mhigh�k;Uhigh�k; thigh�k; ehigh�k; V TB;EÞ �!

ð13Þ

ISiO2ðV TB;EÞ

¼ K � hSiO2V TB

��

USiO2 � Eð Þ3=2 � USiO2 � E � 0:3 � V TBð Þ3=2

�HðUSiO2 � E � 0:3 � V TBÞ þ ðUSiO2 � E � 0:7 � V TBÞ3=2

�H USiO2 � E � 0:7 � V TBð Þ� ðUSiO2 � E � V TBÞ3=2

�HðUSiO2 � E � V TBÞ

ð14Þ

Ihigh�kðhhigh�k;Uhigh�k ; V TB;EÞ

¼ K � hhigh�k

V TB��ðUhigh�k � E � 0:3 � V TBÞ3=2

�HðUhigh�k � E � 0:3 � V TBÞ � ðUhigh�k � E � 0:7 � V TBÞ3=2

�HðUhigh�k � E � 0:7 � V TBÞ

ð15Þ

K ¼ 4

3 � �h �ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2 � q � me

p� e0CTB

ð16Þ

hhigh�k ¼ erhigh�k �ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffimrhigh�k

p ð17Þ

where H is the Heaviside function, �h the reduced Planckconstant, E the electron energy, VTB the voltage dropacross the dielectric stack tunnel barrier, CTB the tunnelbarrier capacitor per surface unit, me the vacuum electron

mass, er the relative dielectric constant, mr the relativeelectron mass and e0 the vacuum permittivity.Because of the considerations on the EOTs of the layers

involved in the barrier, it is possible to express the ISiO2 andIhigh-k terms in (14) and (15) and thus the stack transpar-ency, only as a function of hhigh-k, Uhigh-k, VTB and E.The hhigh-k term is defined in (17) and contains the relativedielectric constant and electron mass of the high-k layer.We can thus express TWKB in (18) as a function of fewerparameters than in (12)

TWKBðmhigh�k;Uhigh�k; thigh�k; ehigh�k; V TB;EÞ¼ TWKBðhhigh�k;Uhigh�k; V TB;EÞ ð18Þ

Eq. (18) combined with (8) allowed us to plot the SiO2/high-k/SiO2 tunneling current as a function of the tunnelbarrier stack voltage drop VTB in Fig. 8.In the graphs of Fig. 8a–d, we plotted J(VTB) curves for

different values of Uhigh-k (1.0 eV, 1.5 eV, 2.0 eV and2.5 eV) with hhigh-k as a parameter, varying from 3 to 14.This corresponds to materials that have a relative permit-tivity worth up to about 20 if there electron mass doesn�texceed 0.5 me or 31 for 0.2 me.These plots allow to evaluate the ranges in which the

parameters of the high-k layer should be situated in orderto allow the best performance. The goal is to select a mate-rial that leads to a sufficiently low leakage current atVRET 1.5 V (10�16 A/cm2 at the most) and high enoughat VPROG 5.5 V (above 10�2 A/cm2 in order to allowfaster programming than SiO2).

SiO

2

SiO

2

Φ1

high-k

VTB-1

SiO

2

SiO

2

Φ2

high-k

VTB-1

SiO

2

SiO

2

Φ2

high-k

VTB-2

a

cb

Fig. 9. Conduction band edge diagrams of two different SiO2/high-k/SiO2stacks. (a) Stack with a VTB�1 voltage drop and a high-k layer with barrierheight U1. (b) Stack with a VTB�1 voltage drop and a high-k layer withbarrier height U2 > U1. (c) Stack with a VTB�2 > VTB�1 voltage drop and ahigh-k layer with barrier height U2 > U1.

J. Buckley et al. / Solid-State Electronics 49 (2005) 1833–1840 1839

4.1. Preliminary remarks

We can see that for each of the four graphs (Fig. 8a–d)and for VTB sufficiently high, the values of the tunnelingcurrents are identical, regardless the value of hhigh-k. Forexample, when Uhigh-k = 1.0 eV (Fig. 8a) the currents areidentical for VTB > 3 V and if Uhigh-k = 2.5 eV forVTB > 7 V.This is because in these cases, the electric field in the

tunnel barrier is sufficiently high to allow the electronsto tunnel directly into the high-k conduction band andthus not view its influence (Fig. 9a). The value of VTB thatallows to be in this configuration increases with Uhigh-kbecause stronger band bending is necessary in order tolower the high-k barrier below the electron injection level.If we compare Fig. 9a and b, we see that U1 is sufficientlylow to not influence the tunneling for a VTB�1 voltagedrop. In Fig. 9b however, U2 is high enough to influencethe tunneling at VTB�1. This influence is suppressed start-ing at VTB�2 > VTB�1 (Fig. 9c).

4.2. Discussion of the results

In this section we will discuss the results of the graphsplotted in Fig. 8a–b and derive the properties that thehigh-k in a SiO2/high-k/SiO2 barrier should have in orderto lead to the best writing/erasing and retention perfor-mance. Let us first discuss both of the most extreme casesthat we simulatedCase a: where Uhigh-k = 1 eV (Fig. 8a)We can see that for this case, the current is always larger

than 10�2 A/cm2 at VPROG and identical for all values ofhhigh-k. At VRET, however, it is only for hhigh-k > 10 thatthe leakage current is low enough to ensure sufficientretention.

Case d: where Uhigh-k = 2.5 eV (Fig. 8d)In this situation, at VRET, the current is always low

enough to ensure sufficient retention for all of the simu-lated values of hhigh-k. At VPROG, the tunneling currentdecreases as hhigh-k increases.The best situation that can be desired is to work with

values of Uhigh-k that allow hhigh-k to not have any influenceon the tunneling current at VPROG, and for which the larg-est range of values of hhigh-k are compatible with the max-imal 10�16 A/cm2 leakage current at VRET. This is the casefor 1.5 eV < Uhigh-k < 2 eV (see Fig. 8b–c), which allow tohave sufficient data retention for hhigh-k P 5.

5. Conclusions

We have shown in this paper experimental results thatare promising for improving the field sensitivity of the tun-nel dielectric of NVMs, by using stacks made of SiO2 andHfO2 rather than only SiO2.We also developed calculations on SiO2/high-k/SiO2

structures. Best results were obtained for a high-klayer with a 1.5–2.0 eV conduction band offset comparedto Si and a relative effective mass and dielectric constantthat should meet the constraint: ehigh-k �

ffiffiffiffiffiffiffiffiffiffiffiffiffimhigh-k

p P 5(mhigh-k, relative electron masse; ehigh-k, relative dielectricconstant).Indeed, these results are encouraging and will have to be

carried out in a near future for larger high-k thicknessesand symmetrical stacks for which the conduction for gateinjection as well as substrate injection could be studied,before being integrated in NVM devices.

Acknowledgements

This work has been partly carried out with the supportof Freescale. The author would like to thank Ramachan-dran Muralidhar, Bob Steimle, Rajesh Rao and BruceWhite from Free scale for fruitful discussions.

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