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Process Flow: 1. Multiple layers (Ni/SiO2/HfO2) deposition on InGaAs/InP substrate Modified Figure: 2. Bonding at 400’C, followed by lapping and HCl etching Modified Figure: 3. Write global/chip marks, and location numbers in the 1 st EBL step , followed by evaporation of Au/Ni sorry, I don’t not quit get the idea of the orientation mark? 4. Write Ni Lines in the 2 nd EBL step , with 2um width and 3um space. These Ni line are used as support for InGaAs membrane as well as the source for alloy reaction Need also larger spacing than 3 um in order to first learn how to control the reaction and reach steady state while still you have unreacted InGaAs layers in the center. Yes, I think I can vary the spacing larger or smaller by put some anchors in between the Fins.

Process Flow: - University of California, San Diegoweb.eng.ucsd.edu/ece/groups/iebl/Internal/Chen/Weekl… · Web viewProcess Flow: Multiple layers (Ni/SiO2/HfO2) deposition on InGaAs/InP

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Page 1: Process Flow: - University of California, San Diegoweb.eng.ucsd.edu/ece/groups/iebl/Internal/Chen/Weekl… · Web viewProcess Flow: Multiple layers (Ni/SiO2/HfO2) deposition on InGaAs/InP

Process Flow: 1. Multiple layers (Ni/SiO2/HfO2) deposition on InGaAs/InP substrate

Modified Figure: 2. Bonding at 400’C, followed by lapping and HCl etching

Modified Figure: 3. Write global/chip marks, and location numbers in the 1 st EBL step , followed by

evaporation of Au/Ni

sorry, I don’t not quit get the idea of the orientation mark?

4.[2.] Write Ni Lines in the 2 nd EBL step , with 2um width and 3um space. These Ni line are used as support for InGaAs membrane as well as the source for alloy reaction Need also larger spacing than 3 um in order to first learn how to control the reaction and reach steady state while still you have unreacted InGaAs layers in the center. Yes, I think I can vary the spacing larger or smaller by put some anchors in between the Fins.

5.[3.] Write Fin structures in the 3 rd EBL step , with two different orientations: (111) and (100)

Minh Nguyen, 05/05/86,
SiO2 is missing in the drawing.
Minh Nguyen, 05/05/86,
Didn’t Shadi want to have the Ni pads perpendicular to the fin in all cases? Since you can control where to put fins and Ni lines, this should be very straight forward to do, and I agree with Shadi that we should make sure (100) fins have perpendicular pads for comparison with (110) ones.
Minh Nguyen, 07/25/13,
I agree with Shadi that for the first experiment, you need some larger than 3um spacing to have an idea on reaction rate. However, by experience, we normally increase temperature very slowly, and stop increasing when we see a sign or reaction, at this point, the rate is still extremely slow. We then wait for temperature stabilization so that the sample stops moving ( due to thermal expansion), then depending on case, increase the temperature a little bit from there. The rate is still very small, and it took hours to finish my 700 nm channel, so in the future, you might want to have small spacing to avoid waste time, and avoid chance of Ni precipitation that accumulate as the bulb along the wires (I don’t really know what it is, some papers say it is Ni precipitation, but we saw a big change of diameter in some parts along the wires).However, I would not recommend to write small spacings for all the big Ni pads. It will cause issue with EBL and lift off. Your “membrane” is still thick, but for my case, I notice a very pronounced wobbling on the membrane, which is the causes for EBL difficulties in comparison to standard flat surface. I suggest that you write about 2um spacing at the minimum, then write some smaller anchors at where you put the fins. That will also give you the chance to make sure pads are perpendicular to the (100) fins as per my comment below.
Daisy, 07/25/13,
Au/Ni won’t stick well to the substrate, probably go with Ni/Au/Ni. Don’t put Ti in this case.
Minh Nguyen, 07/25/13,
You might want to have some special marks for orientation.
Page 2: Process Flow: - University of California, San Diegoweb.eng.ucsd.edu/ece/groups/iebl/Internal/Chen/Weekl… · Web viewProcess Flow: Multiple layers (Ni/SiO2/HfO2) deposition on InGaAs/InP

6.[4.] After Cl-ICP etching and HSQ removal, protect the top surface with photoresist, and etch the Si aperture grid from the backside, in order to remove Ni (with diluted HNO3), and SiO2 (with diluted BOE) Where is the SiO2? . It’s corrected in the schematic figures. After these etching steps, there will be only a 15nm HfO2 layer underneath the InGaAs.

Problems to be discussed: In step 3, the alignment marks need to be written according to the center of bonded

membrane. However, because of the InGaAs/HfO2/SiO2/Ni multiple stacks, it’s hard to find the open window in SEM. How shall I locate the center of the TEM grid?In SEM mode, go to the 4 corners of the TEM grid, write down the coordinates, and then take the average value to be the center of the TEM grid. Write your pattern there. Previously, I was trying to generate the mask to pattern the Ni for the TEM grid bonding, in order to leave the open window without Ni. I checked with the TEM company with the specific dimension. They told me that the Si frame is not always regularly cut and the window might be slightly off center. I also check with the microscope with x-y coordination, and realize that sometimes the edge cutting is not parallel with the window edge. So that’s the reason I’m worried about the marker position.

This is the optical and SEM images of the window, it’s quite blur from the normal SEM, so I think the EBL’s SEM will be even hard to find it.

This morning, I tried to write the markers on the TEM grid. It looks good after spin coating. But after 180’C bake, the window broke. I’m not sure whether it’s due to the thermal stress or the stress from the resist? I will bond more samples today for these tests.

Ni Pad

Ni Pad

Ni Pad

(110) Fin

(100) Fin

Minh Nguyen, 07/25/13,
Did you experimentally try to look for the window in EBL’s SEM. I am curious to hear the results, and try to understand why. In my case, the membrane appear very dark, may be because the SiN membrane is e-beam transparent, but in your case, multiple thick layer might not allow you to see?
Daisy, 07/25/13,
The 200 nm insulating layer below HfO2
Page 3: Process Flow: - University of California, San Diegoweb.eng.ucsd.edu/ece/groups/iebl/Internal/Chen/Weekl… · Web viewProcess Flow: Multiple layers (Ni/SiO2/HfO2) deposition on InGaAs/InP

In step 4, as Minh pointed out, this process will keep the InGaAs underneath the Ni pads non-attacked during RIE etching, which will consume the Ni during annealing. Can this be counteracted by a thicker Ni evaporation? and is this ok for TEM observation? Yes, it will be Ok to deposit thicker Ni layers there and it should be Ok for TEM observation.

In step 6, I’m not sure whether wet BOE etching is so controllable. However, if RIE dry etch is introduced here, I haven’t think out thought of a good way to arrange the dielectric layers: (1) F-etch will also attack HfO2 I don’t think so, didn’t Daisy found out that the etch rate

for HfO2 by also F-etch is slow?(2) If change SiO2 with Al2O3 and use Cl-ICP etch, the HfO2 layer can probably

survive, but Al2O3 cannot stand the BOE dip during HSQ removal correct(3) If use HfO2 as BOE stop layer, then thin layer of Al2O3 as F-etch stop layer, and

bulk dielectric of SiO2 at the bottom, F-etch is ok for this process. But the F-ICP etches Si grid even faster than SiO2.

So, maybe still use BOE wet etching at this moment? Yes, I think so too. We should be able to control the etch rate of PECVD SiO2 or thermal SiO2 with BOE. Here, PECVD SiO2 grown at 180 C could be etched ok…I think I need to test the etching rate with our own recipe here, and see how different dielectric layers can be used.

As Daisy previously found that the HfO2 will change to crystalline during bonding annealing, is this 15nm crystalline HfO2 will affect the TEM observation? Maybe. We will be able to see contrast change in the stack a Ni eats through the InGaAs, so I wouldn’t worry too much about it for now.

Minh Nguyen, 05/05/86,
I second Shadi’s opinion. Let’s try with whatever dielectric thickness that gives you controllable bonding. I used to do 10HfO2 and still could see the reaction, the contrast was not so great, but acceptable.
Daisy, 07/25/13,
I did the wet etch calibration of PECVD SiN. It’s totally not controllable…-_- So I don’t believe the etch rate of PECVD SiO2 will be controllable.
Daisy, 07/25/13,
Did you do the Si and SiO2 etch rate calibration or just from the literature? Different recipes have different selectivity. I doubt Si is etched faster with SiO2 etch recipe.
Daisy, 07/25/13,
Didn’t get the meaning here. Cl will etch both HfO2 and Al2O3….
Daisy, 07/25/13,
Both F and Cl etch will attach HfO2, just depends on the recipe. As I told Renjie, 70s SiO2 etch recipe will overetch 75 cycles HfO2. But I am not sure the etch rate in the Cl recipe which we are using for InGaAs etch.
Daisy, 07/25/13,
Why not do HfO2/Al2O3/SiO2, 10/5/200nm. Al2O3 is resistant to F etch, so one can dry etch SiO2 and stop there. Then you just need to go a short BOE, the Al2O3 will be removed.