Investigation of Comparator Topologies and their Usage in a Technology Independent Flash-ADC Testbed

Cand.-Ing. Öner B. Ergin

Prof. Dr.-Ing. Klaus SolbachDepartment of Microwave and RF-Technology

University of Duisburg-Essen

Dipl.-Ing. Harald Bothe and Dipl.-Ing. Reimund WittmannNokia Research Center Bochum

Prof. Dr.-Ing. Werner SchardeinUniversity of Applied Sciences and Arts Dortmund

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs)‏

•Flash ADC

•Comparators

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

Introduction: Generic Engineering Model

•Variety of process technologies increases

•Circuits have to be rebuilt for every process

•The Generic Engineering Model (GEM)‏

· Circuits are portable to all technologies

· Automatical symbol, schematic, layout and testbench generation

•During this thesis, all circuits were developed using the GEM approach

Introduction: Selection methodology

•Selection methodology on top of GEM implementation allows parameterizable layout solutions•Main high level design constraints:

· Power· Supply voltage· Area· Bit resolution· Speed (clock rate) ‏

•Comparator topologies are investigated with respect to the above

listed constraints for flash ADC implementation

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs) ‏•Flash ADC

•Comparators

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion ‏

State-of-the-Art ADCs

•ADCs are developed for high speed or high resolution

•High resolution and high speed leads to high die size (high costs and implementation effort)‏

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs)‏

•Flash ADC•Comparators

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

Flash ADC

•Fastest ADC structure

•2N

resistors , 2N-1 comparators, thermometer-code to binary encoder

•Single-ended or differential type (wider intensity range) ‏

•Drawbacks (bit wise increase):

· Area and power double approximately

· Resistor matching becomes more critical

· Input bandwidth limited by increasing input capacitance

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs) ‏

•Flash ADC

•Comparators· Comparator Specifications· Latch-Type Topologies

· SC-Type Topologies

· Simulation Results in 65 nm Technology

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

Comparators: Specifications

• Widely used components, especially in ADCs

• Comparator as 1-bit ADC

• Important specifications for implementation in flash ADCs:

· Bit resolution ( ≈

maximum bit resolution of flash ADC)‏

· Input common mode range (ICMR) ( ≈

maximum flash ADC approximation range)‏

· Speed ( ≈ maximum speed of flash ADC)‏

· Power ( ≈ minimum power dissipation of flash ADC (after division by the number of comparators))‏

• No Sample & Hold block needed when clocked comparators are implemented e.g.· Latch-type comparators· SC-type comparators

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs) ‏

•Flash ADC

•Comparators· Comparator Specifications

· Latch-Type Topologies· SC-Type Topologies

· Simulation Results in 65 nm Technology

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

·Advantages:·High and rapid amplification·Low area·Low power

·Disadvantages:·Kickback noise is the main challenge (Charge transfer between the input and the positive-feedback circuit when the amplification phase is active)‏·Mismatch and parasitic sensitivity are additional drawbacks·Output changes to opposed digital state in the regeneration phase

· Solution: SR-Latch at the output

Latch-type topologies

Dynamic latched

4-inputsClass AB latched

4-inputsStatic latched

2-inputs 4-inputs

Comparators: Latch-Type Topologies

·Principle: Positive-feedback circuit·Phases: regeneration (latch=0) and amplification

+

High speed+

Low power+

Low area

− High parasitic sensitivity− Limited ICMR

Comparators: Latch-Type: 2-inputs Dynamic Latched

Latch-type topologies

Dynamic latched

2-inputs 4-inputs

4-inputs Class AB latched

4-inputs static latched

+

High speed+

Low power+

Low area+

Rail-to-rail ICMR

−

Not equal resolution at different references

Comparators: Latch-Type: 4-inputs Class AB Latched

Latch-type topologies

4-inputs Class AB latched

4-inputs static latched

Dynamic latched

Contents

•Introduction

•State-of-the-Art analog-to-digital converters (ADCs) ‏

•Flash ADC

•Comparators· Comparator Specifications

· Latch-Type Topologies

· SC-Type Topologies· Simulation Results in 65 nm Technology

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

SC-type topologies

2-inputs IOS

2-inputs OOS

4-inputsOOS

Single-

stage Multistage

Comparators: SC-Type Topologies

·Principle: Periodically sense and store the offset on capacitors·Phases: Offset cancellation, amplification and latch·A PMOS-input differential amplifier is used as the preamplifier·The latch part is represented by the 2-inputs dynamic latched comparator·Advantages

•High Resolution·Disadvantages

•High area•High power

+

Rail-to-rail ICMR+

High resolution

− High area− High power

Comparators: SC-Type: 2-inputs IOS

SC-type topologies

2-inputs IOS

2-inputs OOS

Single-

stage Multistage

4-inputs OOS

·IOS: Input offset storage

+

Rail-to-rail ICMR+

High resolution

− High area− High power

Comparators: SC-Type: 4-inputs OOS

SC-type topologies

2-inputs OOS

4-inputs OOS

2-inputs IOS

·OOS: Output offset storage

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs) ‏

•Flash ADC

•Comparators· Comparator Specifications

· Latch-Type Topologies

· SC-Type Topologies

· Simulation Results in 65 nm Technology•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

Comparators: Results: Area and Resolution

2-input dynamic latched layoutClass AB latched layout

IOS layoutOOS 4in layout

050

100150

200250

300350

400450

500

Area [µm²]

2-input dynamic latched layoutClass AB latched layout

IOS layoutOOS 4in layout

01

23456789

10

Resolution [bits] for layouted Comparators

0,811,2

·Latch-type comparators·Low area·Parasitic sensitivity degrades maximum resolution

·SC-type comparators·High area·Less parasitic sensitivity

·Conclusion:·Lower area leads to less area consumption

Comparators: Results: Speed and Power

2-input dynamic latched2-input dynamic latched layout

4-input dynamic latchedClass AB latched

Class AB latched layoutStatic latched

IOSIOS layout

Multi IOSOOS 2in

OOS 4inOOS 4in layout

0

500

1000

1500

2000

2500

Speed [MHz]

0,811,2

2-input dynamic latched2-input dynamic latched layout

4-input dynamic latchedClass AB latched

Class AB latched layoutStatic latched

IOSIOS layout

Multi IOSOOS 2in

OOS 4inOOS 4in layout

0,00

10,00

20,00

30,00

40,00

50,00

60,00

70,00

Power [µW] at 10 MHz

0,811,2

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs)‏

•Flash ADC

•Comparators

•Comparator Selection Procedure•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

Comparator selection routine

Flash ADC testbed GEM

Comparator GEM

ParametersTechnology

Bit resolutionSpeed

Approximation rangeSupply voltage

2-inputs / 4-inputs

FAT tree encoder with single bubble

error correction array GEM

Poly resistor array GEM

OutputRelevant topologiesArea consumptionsPower dissipations

Comparator Selection Procedure

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs)‏

•Flash ADC

•Comparators

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology· Layouts· DNL/INL Results

•Conclusion

Flash ADC Testbed: Layouts: 4bit-flash ADC

•Checked and verified for resolutions between 4 and 10 bit (DRC & LVS) ‏

• Compatible for all analyzed comparators

• Dimension scalability: (x-y distribution of comparators &

resistors is adjustable) ‏

4bit Flash ADC layout; Implemented comparator: 2-inputs dynamic latched

Flash ADC Testbed: Layouts: Dimension Scalability with 8bit-Flash ADC

· Scalable X-Y distribution of resistors & comparators· Left: 32 blocks with each 8 comparators & resistors· Right: 16 blocks with each 16 comparators & resistors· Implemented Comparator: 4-inputs Class AB latched

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs)‏

•Flash ADC

•Comparators

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology· Layouts

· DNL/INL Results•Conclusion

Flash ADC Testbed: DNL / INL Results

2-input dynamic latched layoutClass AB latched layout

IOS layoutOOS 4in layout

0

0,02

0,04

0,06

0,08

0,1

0,12

0,14

0,16

DNL / INL Results 4 bits, 10 MHz

DNLINL

2-input dynamic latched layoutClass AB latched layout

IOS layoutOOS 4in layout

0

0,05

0,1

0,15

0,2

0,25

DNL / INL Results 5 bits, 10 MHz

DNLINL

Contents

•Introduction

•State-of-the-Art Analog-to-Digital Converters (ADCs)‏

•Flash ADC

•Comparators

•Comparator Selection Procedure

•Flash ADC Testbed Verification in 65 nm Technology

•Conclusion

Conclusion•Investigation of relevant comparator topologies:

· Latch-type comparators:+ high speed, + low area, + low power, -

high parasitic sensitivity

· SC-type comparators: -

low speed, -

high area, -

high power, + low parasitic sensitivity

•Investigation and implementation of comparator selection procedure for the flash ADC testbed

•A flash ADC GEM testbed has been developed, which is compatible to all analyzed comparators

· Checked and verified (DRC, LVS) for resolutions between 4 and 10

bits

· Integration of x-y dimension scalability

· Complex FAT tree encoder with single bubble error correction array implemented

· Functional verification (simulation of schematic and extracted layout view) has been done in 65 nm technology

· Selection methodology verified for all analyzed comparators

•Main advantage of the selection methodology:

· Simplification of selection and implementation of flash ADCs referring to high-level demands

Thank you for your attention!