Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Properties of Complementary CMOS Gates

Introduction to VLSI Design © Steven P. Levitan 1998IntroductionIntroduction

Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively.

No static power consumption:

There never exists a direct path between VDD and

VSS (GND) in steady-state mode.

Comparable rise and fall times:

(under the appropriate scaling conditions)


Transistor Sizing

VDD

A

B

C

D

D

A

B C

1

2

22

6

6

12

12

F

• for symmetrical response (dc, ac)• for performance

Focus on worst-case

Input Dependent


Propagation Delay Analysis - The Switch Model

VDDVDDVDD

CL

F CL

CL

F

F

RpRp Rp

Rp

Rp

Rn

Rn

RnRn Rn

A

AA

AA

A

B B

B

B

(a) Inverter (b) 2-input NAND (c) 2-input NOR

tp = 0.69 Ron CL

(assuming that CL dominates!)

= RON


What is the Value of Ron?


Numerical Examples of Resistances for 1.2m CMOS


Analysis of Propagation Delay

VDD

CL

F

Rp Rp

Rn

Rn

A

A B

B

2-input NAND

1. Assume Rn=Rp= resistance of minimum sized NMOS inverter

2. Determine “Worst Case Input” transition(Delay depends on input values)

3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pulls

up the output node

- For 2 PMOS devices in parallel, the resistance is lower

4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in series

tpLH = 0.69RpCL

tpHL = 0.69(2Rn)CL


Design for Worst Case

VDD

CL

F

A

A B

B

2

2

1 1

VDD

A

B

C

D

DA

B C

12

22

2

24

4

F

Here it is assumed that Rp = Rn


Influence of Fan-In and Fan-Out

on Delay VDD

A B

A

B

C

D

C D

tp a1FI a2FI2 a3FO+ +=

Fan-Out: Number of Gates Connected2 Gate Capacitances per Fan-Out

FanIn: Quadratic Term due to:

1. Resistance Increasing2. Capacitance Increasing(tpHL)


tp as a function of Fan-In

1 3 5 7 9fan-in

0.0

1.0

2.0

3.0

4.0t p

(ns

ec)

tpHL

tp

tpLHlinear

quadratic

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)


Fast Complex Gate - Design Techniques

• Transistor Sizing: As long as Fan-out Capacitance dominates

• Progressive Sizing:

CL

In1

InN

In3

In2

Out

C1

C2

C3

M1 > M2 > M3 > MN

M1

M2

M3

MN

Distributed RC-line

Can Reduce Delay with more than 30%!


Fast Complex Gate - Design Techniques (2)

In1

In3

In2

C1

C2

CL

M1

M2

M3

In3

In1

In2

C3

C2

CL

M3

M2

M1

(a) (b)

• Transistor Ordering

critical pathcritical path



• Improved Logic Design



• Buffering: Isolate Fan-in from Fan-out

CLCL


Example: Full Adder

VDD

VDD

VDD

VDD

A B

Ci

S

Co

X

B

A

Ci A

BBA

Ci

A B Ci

Ci

B

A

Ci

A

B

BA

Co = AB + Ci(A+B)

28 transistors


A Revised Adder Circuit

VDD

Ci

A

BBA

B

A

A BKill

Generate"1"-Propagate

"0"-Propagate

VDD

Ci

A B Ci

Ci

B

A

Ci

A

BBA

VDD

SCo

24 transistors


Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively.

No static power consumption:

There never exists a direct path between VDD and

VSS (GND) in steady-state mode.

Comparable rise and fall times:

(under the appropriate scaling conditions)


Transistor Sizing

VDD

A

B

C

D

D

A

B C

1

2

22

6

6

12

12

F

• for symmetrical response (dc, ac)• for performance

Focus on worst-case

Input Dependent


Propagation Delay Analysis - The Switch Model

VDDVDDVDD

CL

F CL

CL

F

F

RpRp Rp

Rp

Rp

Rn

Rn

RnRn Rn

A

AA

AA

A

B B

B

B

(a) Inverter (b) 2-input NAND (c) 2-input NOR

tp = 0.69 Ron CL

(assuming that CL dominates!)

= RON


What is the Value of Ron?


Numerical Examples of Resistances for 1.2m CMOS


Analysis of Propagation Delay

VDD

CL

F

Rp Rp

Rn

Rn

A

A B

B

2-input NAND

1. Assume Rn=Rp= resistance of minimum sized NMOS inverter

2. Determine “Worst Case Input” transition(Delay depends on input values)

3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pulls

up the output node

- For 2 PMOS devices in parallel, the resistance is lower

4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in series

tpLH = 0.69RpCL

tpHL = 0.69(2Rn)CL


Design for Worst Case

VDD

CL

F

A

A B

B

2

2

1 1

VDD

A

B

C

D

DA

B C

12

22

2

24

4

F

Here it is assumed that Rp = Rn


Influence of Fan-In and Fan-Out

on Delay VDD

A B

A

B

C

D

C D

tp a1FI a2FI2 a3FO+ +=

Fan-Out: Number of Gates Connected2 Gate Capacitances per Fan-Out

FanIn: Quadratic Term due to:

1. Resistance Increasing2. Capacitance Increasing(tpHL)


tp as a function of Fan-In

1 3 5 7 9fan-in

0.0

1.0

2.0

3.0

4.0t p

(ns

ec)

tpHL

tp

tpLHlinear

quadratic

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)


Fast Complex Gate - Design Techniques

• Transistor Sizing: As long as Fan-out Capacitance dominates

• Progressive Sizing:

CL

In1

InN

In3

In2

Out

C1

C2

C3

M1 > M2 > M3 > MN

M1

M2

M3

MN

Distributed RC-line

Can Reduce Delay with more than 30%!



In1

In3

In2

C1

C2

CL

M1

M2

M3

In3

In1

In2

C3

C2

CL

M3

M2

M1

(a) (b)

• Transistor Ordering

critical pathcritical path



• Improved Logic Design



• Buffering: Isolate Fan-in from Fan-out

CLCL


Example: Full Adder

VDD

VDD

VDD

VDD

A B

Ci

S

Co

X

B

A

Ci A

BBA

Ci

A B Ci

Ci

B

A

Ci

A

B

BA

Co = AB + Ci(A+B)

28 transistors


A Revised Adder Circuit

VDD

Ci

A

BBA

B

A

A BKill

Generate"1"-Propagate

"0"-Propagate

VDD

Ci

A B Ci

Ci

B

A

Ci

A

BBA

VDD

SCo

24 transistors


Ratioed Logic

VDD

VSS

PDNIn1In2In3

F

RLLoad

VDD

VSS

In1In2In3

F

VDD

VSS

PDNIn1In2In3

F

VSS

PDN

Resistive DepletionLoad

PMOSLoad

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

VT < 0

Goal: to reduce the number of devices over complementary CMOS


Ratioed Logic

VDD

VSS

PDN

In1

In2

In3

F

RLLoad

ResistiveN transistors + Load

• VOH = VDD

• VOL = RPN

RPN + RL

• Assymetrical response

• Static power consumption

•

• tpL= 0.69 RLCL


Active Loads

VDD

VSS

In1In2In3

F

VDD

VSS

PDN

In1In2In3

F

VSS

PDN

Depletion

LoadPMOSLoad

depletion load NMOS pseudo-NMOS

VT < 0


Load Lines of Ratioed Gates

0.0 1.0 2.0 3.0 4.0 5.0Vout (V)

0

0.25

0.5

0.75

1

I L(N

orm

aliz

ed)

Resistive load

Pseudo-NMOS

Depletion load

Current source


Pseudo-NMOS

VDD

A B C D

FCL

VOH = VDD (similar to complementary CMOS)

kn VDD VTn– VOL

VOL2

2-------------–

kp

2------ VDD VTp– 2=

VOL VDD VT– 1 1kpkn------–– (assuming that VT VTn VTp )= = =

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!


Psudo-NMOS– N+1 transistors (small) One pull-up P transistor – Ratio based logic: Sizes Matter – Sensitive to power supply – Static power dissipation: Slow and/or power hungry


Pseudo-NMOS NAND Gate

VDD

GND


Improved Loads

A B C D

F

CL

M1M2 M1 >> M2Enable

VDD

Adaptive Load


Improved Loads (2)

VDD

VSS

PDN1

Out

VDD

VSS

PDN2

Out

AABB

M1 M2

Dual Cascode Voltage Switch Logic (DCVSL)


Example

B

A A

B B B

Out

Out

XOR-NXOR gate


Pass-Transistor LogicIn

puts

Switch

Network

OutOut

A

B

B

B

• N transistors

• No static consumption


NMOS-only switch

A = 5 V

B

C = 5 V

CL

A = 5 V

C = 5 V

BM2

M1

Mn

Threshold voltage loss causesstatic power consumption

VB does not pull up to 5V, but 5V - VTN


Solution 1: Transmission Gate

A B

C

C

A B

C

C

B

CL

C = 0 V

A = 5 V

C = 5 V


Pass Gate StructuresBad

– Can be slow – Complementary layout is

hard to do well – Well plugs are a problem

(no vdd/gnd) – Non-standard

minimization techniques – True and complement

inputs typically needed.

Good– Can be very small – Complementary layout

not always used– Non-Boolean logic

functions– True switching

functions supported– Storage integrated into

logic structures


Pass Logic

NMOS style - accept weak "1"'s – restore good 1's with an inverter

CMOS style -- messy to lay out – wells and well plugs

Precharged / feedback / pseudo-pullup


Resistance of Transmission Gate

(W/L)p=(W/L)n =

1.8/1.2

0.0 1.0 2.0 3.0 4.0 5.0Vout

0.0

10000.0

20000.0

30000.0

R (

Ohm

)

Rn

Req

Rp


Pass-Transistor Based Multiplexer

AM2

M1

B

S

S

S F

VDD

GND

VDD

In1

In2

S S

S S


Transmission Gate XOR

A

B

F

B

A

B

B

M1

M2

M3/M4


Delay in Transmission Gate Networks

V1 Vi -1

C

5 5

0 0

Vi Vi+1

CC

5

0

Vn-1 Vn

CC

5

0

In

V1 Vi Vi+1

C

Vn-1 Vn

CC

In

ReqReq Req Req

CC

(a)

(b)

C

Req Req

C C

Req

C C

Req Req

C C

Req

C

In

m

(c)


Elmore Delay (Chapter 8)

R1

C1

R2

C2

Ri-1

Ci-1

Ri

Ci

RN

CN

Vin N1 2 i-1 i

Assume All internal nodes are precharged to VDD and a step voltage is

applied at the input Vin

N Ri Cj

j i=

N

i 1=

N Ci Rj

j 1=

i

i 1=

N= =


Delay Optimization


Transmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup


(2) NMOS Only Logic: Level Restoring Transistor

M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

• Advantage: Full Swing

• Disadvantage: More Complex, Larger Capacitance

• Other approaches: reduced threshold NMOS


Level Restoring Transistor

(a) Output node (b) Intermediate node X

0 2 4 6t (nsec)

-1.0

1.0

3.0

5.0

Vo

ut (

V)

0 2 4t (nsec)

-1.0

1.0

3.0

5.0

VX

with

without

VB

with

without

6


Solution 3: Single Transistor Pass Gate with VT=0

Out

VDD

VDD

5V

VDD

0V 5V

0V

WATCH OUT FOR LEAKAGE CURRENTS


Complimentary Pass Transistor Logic

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=AÝ

F=AÝ

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-Transistor

Network

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)


Pass Gate Logic


4 Input NAND in CPL

Documents

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Properties of Complementary CMOS Gates