Introduction to CMOS [Compatibility Mode]

8/6/2019 Introduction to CMOS [Compatibility Mode]

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Introduction to CMOS

Introduction to Circuit Design

Lecture Series by Intel


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2009 Intel India Pvt Limited. All rights reserved. The

information provided in this presentation is intended for the sole

use of the recipient and is for educational purposes only. No part of

this presentation may be reproduced or transmitted in any form or

by any means, including photocopying and recording, without

written permission. Permission must also be obtained before any

part of this presentation is stored in a retrieval system in any

nature. No responsibility can be accepted by Intel India Pvt

Limited, the Editorial Board or contributors for action taken as a

result of information contained in this presentation. The views

expressed in this presentation by the presenter are not necessarily

those of the Editorial Board or Intel India Pvt Limited.


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Lecture Series

Introduction to CMOS APR 30th

Static CMOS Design APR 30th

CMOS Logic Styles MAY 21st

Sequentials & Memory MAY 21st


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Lecture Series

Introduction to CMOS APR 30th

Static CMOS Design APR 30th

CMOS Logic Styles MAY 21st

Sequentials & Memory MAY 21st


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What will we learn?

Evolution of Integrated Circuits

Scaling trends

MOS transistor fundamentals

CMOS Inverter characteristics


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The Journey

First transistor

Bell Labs, 1948


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The Journey

First Integrated Circuit

Fairchild Semi, 1961


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The Journey

Intel 4004 Microprocessor

Intel, 1971* ~2.3K transistors

* ~700 Khz

* 10um technology


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The Journey

Intel Pentium 4 Processor

Intel, 2005* ~125,000K transistors

* ~3.8 Ghz

* 90nm technology


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The Journey

Intel Core i7 Processor

Intel, 2008* ~730,000K transistors

* ~3.5 Ghz

* 45nm technology


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Moores Law

1965, Gordon Moore # of transistors

on a chip doubledevery 2 years

This trend has held

true for more thanhalf a century


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Why Scaling?

Technology shrinks by 0.7 every generation

We can integrate 2x more devices

Translates into ~2x cost reduction of a function

Hence semiconductors is one of those rare

industries which gives us more for the same costas time goes by

There have been design challenges as we have

scaled down technology


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Design Abstraction Levels

SYSTEM

MODULE

+

CIRCUIT

VoutVin

CIRCUIT

VoutVin

DEVICE

n+

S D

n+

G


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MOS Transistor


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NMOS & PMOSSymbols

p-ch

n-ch

Physical Structure

n+ n+

p-sub

DrainSource Gate

Substrate

channel

n-ch MOS

p+ p+

n-sub

DrainSource Gate

Substrate

channel

p-ch MOS


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Threshold Voltage


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Modes of Operation

Drain 0VSourceGate

Vgs > Vt ; Vds=0V

p-sub

Substraten-type channel

n-ch MOS

depletion layer


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Modes of Operation

n+ n+

Drain (Vds)SourceGate

Linear region: Vgs - Vt > Vds > 0V

p-sub


n-ch MOS

depletion layer


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Modes of Operation

n+ n+

Drain (Vds)SourceGate

Saturation region: Vds > Vgs - Vt

p-sub


n-ch MOS

pinch-off region

depletion layer


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IV Curve

3

4

5

6X 10

-4

VGS = 2.0V

VGS = 2.5V

Linear Saturation

VDS = VGS - VT

2.07V

1.57V

0

1

2

0 0.5 1 1.5 2 2.5

VDS (V)

VGS = 1.0V

VGS = 1.5V

cut-off

0.57V

1.07V


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Short Channel Effects

Short channel device behavior is mainly due tovelocity saturation

105

10

0

0 1.5 3

(V/m)

c=

0


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CMOS Inverter

VDD

Vout

CL

Vin


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CMOS Inverter Load LinesX 10-4

Vin = 2.0V

Vin = 2.5VVin = 0V

Vin = 0.5V

PMOS NMOS

Vout (V)

Vin = 1.0V

Vin = 1.5VVin = 1.0V

Vin = 1.5V

Vin = 0.5VVin = 2.0V

Vin = 2.5V

Vin = 2VVin = 1.5V

Vin = 1V

Vin = 0.5V

Vin = 0V


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1.5

2

2.5

CMOS Inverter VTC

(V)

NMOS offPMOS res

NMOS satPMOS res

NMOS satPMOS sat

0

0.5

1

0 0.5 1 1.5 2 2.5

Vin (V)

Vou

NMOS resPMOS sat NMOS res

PMOS off


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What did we learn?

Evolution of Integrated Circuits

Scaling trends

MOS transistor fundamentals

CMOS Inverter characteristics

Documents

Introduction to CMOS [Compatibility Mode]