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Document # 320834-004 Intel ® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel ® Core™ i7-900 Desktop Processor Series Datasheet, Volume 1 February 2010

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Document#320834- 004I nt el Cor e i 7- 900 Desk t op Pr ocessorEx t r eme Edi t i on Ser i es and I nt el Cor e i 7- 900 Desk t op Pr ocessorSer i esDat asheet , Vol ume 1Febr uar y20102 Dat asheetI NFORMATI ON I N THI S DOCUMENT I S PROVI DED I N CONNECTI ON WI TH I NTEL PRODUCTS.NO LI CENSE,EXPRESS OR I MPLI ED,BY ESTOPPEL OR OTHERWI SE,TO ANY I NTELLECTUAL PROPERTY RI GHTS I S GRANTED BY THI S DOCUMENT.EXCEPT AS PROVI DED I N I NTEL' S TERMS AND CONDI TI ONS OF SALE FOR SUCH PRODUCTS,I NTEL ASSUMES NO LI ABI LI TY WHATSOEVER,AND I NTEL DI SCLAI MS ANY EXPRESS OR I MPLI ED WARRANTY,RELATI NG TO SALE AND/ OR USE OF I NTEL PRODUCTS I NCLUDI NG LI ABI LI TY OR WARRANTI ES RELATI NG TO FI TNESS FOR A PARTI CULAR PURPOSE,MERCHANTABI LI TY,OR I NFRI NGEMENT OF ANY PATENT,COPYRI GHT OR OTHER I NTELLECTUAL PROPERTY RI GHT.I NTEL PRODUCTS ARE NOT I NTENDED FOR USE I N MEDI CAL,LI FE SAVI NG,OR LI FE SUSTAI NI NG APPLI CATI ONS.I nt el may make changes t o specificat ions and productdescript ions atany t ime,wit houtnot ice.Designers mustnotrely on t he absence or charact erist ics of any feat ures or inst ruct ions marked "reserved" or "undefined. " I nt el reserves t hese for fut ure definit ion and shall have no responsibilit y what soever for conflict s or incompat ibilit ies arising from fut ure changes t o t hem.The I nt el Core i7- 900 deskt op processor Ext reme Edit ion series and I nt el Core i7- 900 deskt op processor series may cont ain design defect s or errors known as errat a which may cause t he productt o deviat e from published specificat ions.AI nt el processor numbers are nota measure of performance.Processor numbers diff erent iat e feat ures wit hin each processor family,notacross differentprocessor families.See ht t p: / / www. int el. com/ product s/ processor_number for det ails.Over t ime processor numbers will incrementbased on changes in clock,speed,cache,FSB,or ot her feat ures,and increment s are notint ended t o representproport ional or quant it at ive increases in any part icular feat ure.Currentroadmap processor number progression is notnecessarily represent at ive of fut ure roadmaps.See www. int el. com/ product s/ processor_number for det ails.Hyper-Threading Technology requires a comput er syst em wit h a processor support ing HT Technology and an HT Technology-enabled chipset ,BI OS and operat ing syst em.Performance will vary depending on t he specific hardware and soft ware you use.For more informat ion including det ails on which processors supportHT Technology,see ht t p: / / www. int el. com/ product s/ ht / hypert hreading_more. ht mI nt el 64 requires a comput er syst em wit h a processor,chipset ,BI OS,operat ing syst em,device drivers and applicat ions enabled for I nt el 64.Processor will notoperat e( including 32- bitoperat ion)wit houtan I nt el 64- enabled BI OS.Performance will vary depending on your hardware and soft ware configurat ions.See www.int el. com/ info/ em64tfor more informat ion including det ails on which processors supportI nt el 64 or consultwit h your syst em vendor for more informat ion.I nt el Virt ualizat ion Technology requires a comput er syst em wit h a processor,chipset ,BI OS,virt ual machine monit or ( VMM)and for some uses,cert ain plat form soft ware,enabled for it .Funct ionalit y,performance or ot her benefitwill vary depending on hardware and soft ware configurat ions.I nt el Virt ualizat ion Technology- enabled VMM applicat ions are current ly in development .Enabling Execut e Disable Bitfunct ionalit y requires a PC wit h a processor wit h Execut e Disable Bitcapabilit y and a support ing operat ing syst em.Check wit h your PC manufact urer on whet her your syst em delivers Execut e Disable Bitfunct ionalit y.Enhanced I nt elSpeedSt ep Technology.See t he Processor Spec Finder or cont actyour I nt el represent at ive for more informat ion.I nt elTurbo BoostTechnology requires a PC wit h a processor wit h I nt el Turbo BoostTechnology capabilit y.I nt el Turbo BoostTechnology performance varies depending on hardware,soft ware and overall syst em configurat ion.Check wit h your PC manufact urer on whet her your syst em delivers I nt el Turbo BoostTechnology.For more informat ion,see www. int el. com.Cont actyour local I nt el sales office or your dist ribut or t o obt ain t he lat estspecificat ions and before placing your productor der.I nt el,I nt el SpeedSt ep,I nt el Core,and t he I nt el logo are t rademarks or regist ered t rademarks of I nt el Corporat ion or it s subsidiaries in t he Unit ed St at es and ot her count ries.* Ot her names and brands may be claimed as t he propert y of ot hers.Copyright20082010 I nt el Corporat ion.Dat asheet 3Cont ent s1 I nt r oduct i on .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 91. 1 Terminology . .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 101. 2 References . .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 112 El ect r i calSpeci f i cat i ons .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 132. 1 I nt el QPIDifferent ial Signaling .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 132. 2 Power and Ground Lands. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 132. 3 Decoupling Guidelines. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 132. 3.1 VCC,VTTA,VTTD, VDDQ Decoupling. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 142. 4 Processor Clocking ( BCLK_DP, BCLK_DN) . .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 142. 4.1 PLL Power Supply .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 142. 5 Volt age I dent ificat ion ( VI D) . .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 142. 6 Reserved or Unused Signals. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 172. 7 Signal Groups . .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 182. 8 TestAccess Port( TAP)Connect ion. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 192. 9 Plat form Environment al Cont rol I nt erface ( PECI )DC Specificat ions. .. .. .. .. .. . .. .. .. .. .. .. .. . 202. 9.1 DC Charact erist ics . .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 202. 9.2 I nputDevice Hyst eresis .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 212. 10 Absolut e Maximum and Minimum Rat ings . .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 212. 11 Processor DC Specificat ions . .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 222. 11. 1 DC Volt age and CurrentSpecificat ion .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 232. 11. 2 VCC OvershootSpecificat ion .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 292. 11. 3 Die Volt age Validat ion .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 303 Pack age Mechani calSpeci f i cat i ons .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 313. 1 Package Mechanical Drawing.. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 313. 2 Processor ComponentKeep- OutZones. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 343. 3 Package Loading Specificat ions . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 343. 4 Package Handling Guidelines.. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 343. 5 Package I nsert ion Specificat ions.. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 343. 6 Processor Mass Specificat ion .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 353. 7 Processor Mat erials. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 353. 8 Processor Markings. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 353. 9 Processor Land Coordinat es . .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 364 Land Li st i ng . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 375 Si gnalDescr i pt i ons .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 676 Ther malSpeci f i cat i ons . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 716. 1 Package Thermal Specificat ions. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 716. 1.1 Thermal Specificat ions . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 716. 1.2 Thermal Met rology .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 756. 2 Processor Thermal Feat ures. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 766. 2.1 Processor Temperat ure . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 766. 2.2 Adapt ive Thermal Monit or .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 766. 2.3 THERMTRI P#Signal .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 796. 3 Plat form EnvironmentCont rol I nt erface ( PECI ) . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 796. 3.1 I nt roduct ion . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 796. 3.2 PECISpecificat ions .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 816. 4 St orage Condit ions Specificat ions . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 824 Dat asheet7 Feat ur es . .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 837.1 Power- On Configurat ion ( POC) .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 837.2 Clock Cont rol and Low Power St at es. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 837.2.1 Thread and Core Power St at e Descript ions .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 847.2.2 Package Power St at e Descript ions. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 857.3 Sleep St at es . .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 867.4 ACPIP- St at es ( I nt el Turbo BoostTechnology) . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 867. 5 Enhanced I nt el SpeedSt ep Technology . .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 878 Box ed Pr ocessorSpeci f i cat i ons . .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 898.1 I nt roduct ion .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 898.2 Mechanical Specificat ions. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 908.2.1 Boxed Processor Cooling Solut ion Dimensions.. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 908.2.2 Boxed Processor Fan Heat sink Weight . .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 928. 2.3 Boxed Processor Ret ent ion Mechanism and Heat sink At t ach Clip Assembly . . . . . 928.3 Elect rical Requirement s . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 928.3.1 Fan Heat sink Power Supply .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 928.4 Thermal Specificat ions. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 938.4.1 Boxed Processor Cooling Requirement s.. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 938.4.2 Variable Speed Fan .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 95Fi gur es1- 1 High- Level View of Processor I nt erfaces .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. 92- 1 Act ive ODT for a Different ial Link Example .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 132- 2 I nputDevice Hyst eresis . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 212- 3 VCC St at ic and TransientTolerance Load Lines .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 252- 4 VTT St at ic and TransientTolerance Load Line . . .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 272- 5 VCC OvershootExample Waveform .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 303- 1 Processor Package Assembly Sket ch. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 313- 2 Processor Package Drawing ( Sheet1 of 2) .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 323- 3 Processor Package Drawing ( Sheet2 of 2) .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 333- 4 Processor Top- side Markings .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 353- 5 Processor Land Coordinat es and Quadrant s ( Bot t om View) . .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 366- 1 Processor Thermal Profile. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 736- 2 Thermal TestVehicle ( TTV)Case Temperat ure ( TCASE)MeasurementLocat ion . .. .. .. .. . 756- 3 Frequency and Volt age Ordering . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 777- 1 Power St at es. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 848- 1 Mechanical Represent at ion of t he Boxed Processor .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 898- 2 Space Requirement s for t he Boxed Processor ( side view) . .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 908- 3 Space Requirement s for t he Boxed Processor ( t op view) .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 918- 4 Space Requirement s for t he Boxed Processor ( overall view) . .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 918- 5 Boxed Processor Fan Heat sink Power Cable Connect or Descript ion.. .. .. .. .. .. .. . .. .. .. .. .. .. . 928- 6 Baseboard Power Header PlacementRelat ive t o Processor Socket . .. .. .. .. .. .. .. . .. .. .. .. .. .. . 938- 7 Boxed Processor Fan Heat sink Airspace KeepoutRequirement s ( t op view) . .. . .. .. .. .. .. .. . 948- 8 Boxed Processor Fan Heat sink Airspace KeepoutRequirement s ( side view) .. . .. .. .. .. .. .. . 948- 9 Boxed Processor Fan Heat sink SetPoint s .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 95Dat asheet 5Tabl es1- 1 References . .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 112- 1 Volt age I dent ificat ion Definit ion. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 152- 2 MarketSegmentSelect ion Trut h Table for MS_I D[ 2: 0] .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 172- 3 Signal Groups . .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 182- 4 Signals wit h ODT. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 192- 5 PECIDC Elect rical Limit s . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 202- 6 Processor Absolut e Minimum and Maximum Rat ings .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 222- 7 Volt age and CurrentSpecificat ions. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 232- 8 VCC St at ic and TransientTolerance . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 242- 9 VTT Volt age I dent ificat ion ( VI D)Definit ion .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 252- 10 VTT St at ic and TransientTolerance .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 262- 11 DDR3 Signal Group DC Specificat ions. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 272- 12 RESET#Signal DC Specificat ions. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 282- 13 TAP Signal Group DC Specificat ions . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 282- 14 PWRGOOD Signal Group DC Specificat ions.. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 282- 15 Cont rol Sideband Signal Group DC Specificat ions .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 292- 16 VCC OvershootSpecificat ions. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 293- 1 Processor Loading Specificat ions . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 343- 2 Package Handling Guidelines.. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 343- 3 Processor Mat erials. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 354- 1 Land List ing by Land Name.. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 374- 2 Land List ing by Land Number . .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 525- 1 Signal Definit ions . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 676- 1 Processor Thermal Specificat ions . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 726- 2 Processor Thermal Profile .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 736- 3 Thermal Solut ion Performance above TCONTROL .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 746- 4 Support ed PECICommand Funct ions and Codes . . . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 816- 5 Get Temp0( )Error Codes . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 816- 6 St orage Condit ions . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 827- 1 Power On Configurat ion Signal Opt ions. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 837- 2 Coordinat ion of Thread Power St at es att he Core Level .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 847- 3 Processor S- St at es . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 868- 1 Fan Heat sink Power and Signal Specificat ions. . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 938- 2 Fan Heat sink Power and Signal Specificat ions. . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 956 Dat asheetDat asheet 7I nt el Cor e i 7- 900 Desk t op Pr ocessorEx t r eme Edi t i on Ser i es and I nt el Cor e i 7- 900 Desk t op Pr ocessorSer i es Feat ur es Available at3. 20 GHz,3. 06 GHz,2. 93 GHz,2. 80 GHz,and 2. 66 GHz ( I nt el Core i7- 900 deskt op deskt op processor series) Available at3. 33 GHz and 3. 20 GHz ( I nt el Core i7- 900 deskt op processor Ext reme Edit ion series) Enhanced I nt el Speedst ep Technology Support s I nt el 64u Archit ect ure Support s I nt elVirt ualizat ion Technology I nt el Turbo BoostTechnology Support s Execut e Disable Bitcapabilit y Binary compat ible wit h applicat ions running on previous members of t he I nt el microprocessor line I nt el Wide Dynamic Execut ion Very deep out - of- order execut ion Enhanced branch predict ion Opt imized for 32- bitapplicat ions running on advanced 32- bitoperat ing syst ems I nt el SmartCache 8 MB Level 3 cache I nt el Advanced Digit al Media Boost Enhanced float ing pointand mult imedia unitfor enhanced video, audio, encrypt ion, and 3D performance New accelerat ors for improved st ring and t extprocessing operat ions Power Managementcapabilit ies Syst em Managementmode Mult iple low- power st at es 8- way cache associat ivit y provides improved cache hitrat e on load/ st ore operat ions Syst em Memory I nt erface Memory cont roller int egrat ed in processor package 3 channels 2 DI MMs/ channel support ed ( 6 t ot al) 24 GB maximum memory support ed Supportunbuffered DI MMs only Single Rank and Dual Rank DI MMs support ed DDR3 speeds of 800/ 1066 MHz support ed 512Mb, 1Gb,2Gb,Technologies/ Densit ies support ed I nt el QuickPat h I nt erconnect( QPI ) Fast / narrow unidirect ional links Concurrentbi- direct ional t raffic Error det ect ion using CRC Error correct ion using Link level ret ry Packetbased prot ocol Pointt o pointcache coherentint erconnect I nt el I nt erconnectBuiltI n Self Test( I nt el I BI ST)t oolbox built - in 1366- land Package8 Dat asheetRevi si on Hi st or yRevi si on NumberDescr i pt i on Dat e- 001 I nit ial releaseNovember 2008- 002 Added I nt el Core i7 processor i7- 950 Added I nt el Core i7 processor Ext reme Edit ion i7- 975June 2009- 003 Added I nt el Core i7- 900 deskt op processor i7- 960 Oct ober 2009- 004 Added I nt el Core i7- 900 deskt op processor i7- 930 February 2010Dat asheet 9I nt r oduct i on1 I nt r oduct i onThe I nt el Core i7- 900 deskt op processor Ext reme Edit ion series and I nt el Core i7- 900 deskt op processor series are int ended for high performance high- end deskt op,Uni- processor ( UP)server,and workst at ion syst ems.Several archit ect ural and microarchit ect ural enhancement s have been added t o t his processor including four processor cores in t he processor package and increased shared cache.The I nt el Core i7- 900 deskt op processor Ext reme Edit ion series and I nt el Core i7- 900 deskt op processor series are t he firstdeskt op mult i- core processor t o implementkey new t echnologies: I nt egrat ed memory cont roller Point - t o- pointlink int erface based on I nt el QPIFigure 1- 1 shows t he int erfaces used wit h t hese new t echnologies.Not e: I n t his documentt he I nt el Core i7- 900 deskt op processor Ext reme Edit ion series and I nt el Core i7- 900 deskt op processor series will be referred t o as t he processor.Not e: The I nt el Core i7- 900 deskt op processor series refers t o t he I nt el Core i7- 900 deskt op processors i7- 960,i7- 950,i7- 940,i7- 930,and i7- 920.Not e: The I nt el Core i7- 900 deskt op processor Ext reme Edit ion series refers t o t he I nt el Core i7- 900 deskt op processor Ext reme Edit ion i7- 975 and i7- 965.The processor is opt imized for performance wit h t he power efficiencies of a low- power microarchit ect ure.This documentprovides DC elect rical specificat ions,different ial signaling specificat ions,pinoutand signal definit ions,package mechanical specificat ions and t hermal requirement s,and addit ional feat ures pert inentt o t he implement at ion and operat ion of t he processor. For informat ion on regist er descript ions,refer t o t he I nt el Core i7-900 Deskt op Processor Ext reme Edit ion Series and I nt el Core i7- 900 Deskt op Processor Series Dat asheet ,Volume 2.Fi gur e 1- 1. Hi gh- Lev elVi ewofPr ocessorI nt er f acesProcessorIntel QuickPath Interconnect (Intel QPI)CH 0CH 1CH 2System Memory (DDR3)I nt r oduct i on10 Dat asheetThe processor is a mult i- core processor builton t he 45 nm process t echnology,t hatuses up t o 130 W t hermal design power ( TDP) .The processor feat ures an I nt el QPIpoint - t o- pointlink capable of up t o 6. 4 GT/ s,8 MB Level 3 cache, and an int egrat ed memory cont roller.The processor support s all t he exist ing St reaming SI MD Ext ensions 2 ( SSE2) ,St reaming SI MD Ext ensions 3 ( SSE3)and St reaming SI MD Ext ensions 4 ( SSE4) .The processor support s several Advanced Technologies:I nt el 64 Technology ( I nt el 64) ,Enhanced I nt el SpeedSt ep Technology,I nt el Virt ualizat ion Technology ( I nt el VT) ,I nt el Turbo BoostTechnology,and I nt el Hyper-Threading Technology.1. 1 Ter mi nol ogyA # symbol aft er a signal name refers t o an act ive low signal,indicat ing a signal is in t he act ive st at e when driven t o a low level.For example, when RESET#is low, a resethas been request ed. Conversely,when VTTPWRGOOD is high,t he VTT power rail is st able._N and _P aft er a signal name refers t o a different ial pair.Commonly used t erms are explained here for clarificat ion: I nt el Cor e i 7- 900 Desk t op Pr ocessorEx t r eme Edi t i on Ser i es and I nt el Cor e i 7- 900 Desk t op Pr ocessorSer i es The ent ire product , including processor subst rat e and int egrat ed heatspreader ( I HS) . 1366- l and LGA pack age The I nt el Core i7- 900 deskt op processor Ext reme Edit ion series and I nt el Core i7- 900 deskt op processor series are available in a Flip- Chip Land Grid Array ( FC- LGA)package,consist ing of t he processor mount ed on a land grid array subst rat e wit h an int egrat ed heatspreader ( I HS) . LGA1366 Sock et The processor ( in t he LGA 1366 package)mat es wit h t he syst em board t hrough t his surface mount ,1366- cont actsocket . DDR3 Double Dat a Rat e 3 Synchronous Dynamic Random Access Memory ( SDRAM)is t he name of t he new DDR memory st andard t hatis being developed as t he successor t o DDR2 SRDRAM. I nt el Qui ck Pat h I nt er connect( I nt elQPI ) I nt el QPIis a cache- coherent ,point - t o- pointlink based elect rical int erconnectspecificat ion for I nt el processors and chipset s. I nt egr at ed Memor yCont r ol l er A memory cont roller t hatis int egrat ed int o t he processor die. I nt egr at ed HeatSpr eader( I HS) A componentof t he processor package used t o enhance t he t hermal performance of t he package.Componentt hermal solut ions int erface wit h t he processor att he I HS surface. Funct i onalOper at i on Refers t o t he normal operat ing condit ions in which all processor specificat ions,including DC,AC,signal qualit y, mechanical,and t hermal,are sat isfied. Enhanced I nt elSpeedSt ep Technol ogy Enhanced I nt el SpeedSt ep Technology allows t he operat ing syst em t o reduce power consumpt ion when performance is notneeded. Ex ecut e Di sabl e Bi t Execut e Disable allows memory t o be marked as execut able or non- execut able,when combined wit h a support ing operat ing syst em.I f code at t empt s t o run in non- execut able memory t he processor raises an error t o t he operat ing syst em.This feat ure can preventsome classes of viruses or worms t hatexploitbuffer overrun vulnerabilit ies and can t hus help improve t he overall Dat asheet 11I nt r oduct i onsecurit y of t he syst em.See t he I nt el Archit ect ure Soft ware Developer' s Manual for more det ailed informat ion.Refer t o ht t p: / / developer. int el. com/for fut ure reference on up t o dat e nomenclat ures. I nt el 64 Ar chi t ect ur e An enhancementt o I nt el' s I A- 32 archit ect ure,allowing t he processor t o execut e operat ing syst ems and applicat ions writ t en t o t ake advant age of I nt el64.Furt her det ails on I nt el 64 archit ect ure and programming model can be found atht t p: / / developer. int el. com/ t echnology/ int el64/ . I nt el Vi r t ual i zat i on Technol ogy ( I nt el VT) A setof hardware enhancement s t o I nt el server and clientplat forms t hatcan improve virt ualizat ion solut ions.I nt el VT provides a foundat ion for widely- deployed virt ualizat ion solut ions and enables a more robusthardware assist ed virt ualizat ion solut ion.More informat ion can be found at :ht t p: / / www. int el. com/ t echnology/ virt ualizat ion/ Uni tI nt er v al( UI ) Signaling convent ion t hatis binary and unidirect ional.I n t his binary signaling, one bitis sentfor every edge of t he forwarded clock,whet her itis a rising edge or a falling edge.I f a number of edges are collect ed atinst ances t1, t2,tn, .. ..,tk t hen t he UIatinst ance nis defined as:UIn= tn tn1 Ji t t er Any t iming variat ion of a t ransit ion edge or edges from t he defined UnitI nt erval. St or age Condi t i ons Refers t o a non- operat ional st at e. The processor may be inst alled in a plat form,in a t ray,or loose.Processors may be sealed in packaging or exposed t o free air. Under t hese condit ions,processor lands should notbe connect ed t o any supply volt ages,have any I / Os biased,or receive any clocks. OEM Original EquipmentManufact urer.1. 2 Ref er encesMat erial and concept s available in t he following document s may be beneficial when reading t his document .Tabl e 1- 1. Ref er encesDocument Locat i onI nt el Core i7- 900 Deskt op Processor Ext reme Edit ion Series and I nt el Core i7- 900 Deskt op Processor Series Specificat ion Updat eht t p: / / download. int el. com/ design/processor/ specupdt / 320836. pdfI nt el Core i7- 900 Deskt op Processor Ext reme Edit ion and I nt el Core i7- 900 Deskt op Processor Series Dat asheetVolume 2ht t p: / / download. int el. com/ design/processor/ dat asht s/ 320835. pdfI nt el Core i7- 900 Deskt op Processor Ext reme Edit ion Series and I nt el Core i7- 900 Deskt op Processor Series and LGA1366 SocketThermal and Mechanical Design Guideht t p: / / download. int el. com/ design/processor/ designex/ 320837. pdfI nt el X58 Express ChipsetDat asheet ht t p: / / www. int el. com/ Asset s/ PDF/dat asheet / 320838. pdfAP- 485,I nt elProcessor I dent ificat ion and t he CPUI D I nst ruct ion ht t p: / / www. int el. com/ design/ processor/ applnot s/ 241618. ht m I A- 32 I nt el Archit ect ure Soft ware Developer' s Manual Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide, Part 1 Volume 3B: Systems Programming Guide, Part 2ht t p: / / www. int el. com/ product s/ processor/ manuals/I nt r oduct i on12 Dat asheetDat asheet 13El ect r i calSpeci f i cat i ons2 El ect r i calSpeci f i cat i ons2. 1 I nt el QPIDi f f er ent i alSi gnal i ngThe processor provides an I nt el QPIportfor high speed serial t ransfer bet ween ot her I nt el QPI - enabled component s.The I nt el QPIportconsist s of t wo unidirect ional links ( for t ransmitand receive) .I nt el QPIuses a different ial signalling scheme where pairs of opposit e- polarit y ( D_P,D_N)signals are used.On- die t erminat ion ( ODT)is provided on t he processor silicon and t erminat ion is t o VSS.I nt el chipset s also provide ODT;t hus,eliminat ing t he need t o t erminat e t he I nt el QPIlinks on t he syst em board.I nt el st rongly recommends performing analog simulat ions of t he I nt el QPIint erface.Figure 2- 1 illust rat es t he act ive ODT. Signal list ings are included in Table 2- 3 and Table 2- 4.See Chapt er 5 for t he pin signal definit ions.All I nt el QPIsignals are in t he different ial signal group.2. 2 Pow erand Gr ound LandsFor clean on- chip processor core power dist ribut ion,t he processor has 210 VCC pads and 119 VSS pads associat ed wit h VCC;8 VTTA pads and 5 VSS pads associat ed wit h VTTA;28 VTTD pads and 17 VSS pads associat ed wit h VTTD,28 VDDQ pads and 17 VSS pads associat ed wit h VDDQ;and 3 VCCPLL pads.All VCCP,VTTA,VTTD,VDDQ and VCCPLL lands mustbe connect ed t o t heir respect ive processor power planes,while all VSS lands mustbe connect ed t o t he syst em ground plane.The processor VCC lands mustbe supplied wit h t he volt age det ermined by t he processor Volt age I Dent ificat ion ( VI D)signals.Table 2- 1 specifies t he volt age level for t he various VI Ds.2. 3 Decoupl i ng Gui del i nesDue t o it s large number of t ransist ors and high int ernal clock speeds,t he processor is capable of generat ing large currentswings bet ween low and full power st at es.This may cause volt ages on power planes t o sag below t heir minimum values if bulk decoupling is notadequat e.Larger bulk st orage ( CBULK) ,such as elect rolyt ic capacit ors,supply currentduring longer last ing changes in currentdemand;such as,coming outof an idle condit ion.Similarly, capacit ors actas a st orage well for currentwhen ent ering an idle condit ion from a running condit ion.Care mustbe t aken in t he baseboard design t o Fi gur e 2- 1. Act i ve ODT f ora Di f f er ent i alLi nkEx ampl eTXRXRTTRTTRTTRTTSignalSignalEl ect r i calSpeci f i cat i ons14 Dat asheetensure t hatt he volt age provided t o t he processor remains wit hin t he specificat ions list ed in Table 2- 7.Failure t o do so can resultin t iming violat ions or reduced lifet ime of t he processor.2.3.1 VCC, VTTA, VTTD,VDDQ Decoupl i ngVolt age regulat or solut ions need t o provide bulk capacit ance and t he baseboard designer mustassure a low int erconnectresist ance from t he regulat or t o t he LGA1366 socket .Bulk decoupling mustbe provided on t he baseboard t o handle large currentswings.The power delivery solut ion mustinsure t he volt age and currentspecificat ions are met( as defined in Table 2- 7) .2. 4 Pr ocessorCl ock i ng ( BCLK_DP,BCLK_DN)The processor core,I nt el QPI ,and int egrat ed memory cont roller frequencies are generat ed from BCLK_DP and BCLK_DN.Unlike previous processors based on frontside bus archit ect ure,t here is no directlink bet ween core frequency and I nt el QPIlink frequency ( such as,no core frequency t o I nt el QPImult iplier) .The processor maximum core frequency,I nt el QPIlink frequency and int egrat ed memory cont roller frequency,are setduring manufact uring.I tis possible t o override t he processor core frequency set t ing using soft ware.This permit s operat ion atlower core frequencies t han t he fact ory setmaximum core frequency. The processor s maximum non- t urbo core frequency is configured during power- on resetby using values st ored int ernally during manufact uring.The st ored value set s t he highestcore mult iplier atwhich t he part icular processor can operat e.I f lower max non-t urbo speeds are desired,t he appropriat e rat io can be configured using t he CLOCK_FLEX_MAX MSR.The processor uses different ial clocks ( BCLK_DP,BCLK_DN) .Clock mult iplying wit hin t he processor is provided by t he int ernal phase locked loop ( PLL) ,which requires a const antfrequency BCLK_DP,BCLK_DN input , wit h except ions for spread spect rum clocking.The processor core frequency is det ermined by mult iplying t he rat io by 133 MHz.2.4.1 PLL Pow erSuppl yAn on- die PLL filt er solut ion is implement ed on t he processor.Refer t o Table 2- 7 for DC specificat ions.2. 5 Vol t age I dent i f i cat i on ( VI D)The volt age setby t he VI D signals is t he reference volt age regulat or out putvolt age t o be delivered t o t he processor VCC pins.VI D signals are CMOS push/ pull drivers.Refer t o Table 2- 15 for t he DC specificat ions for t hese signals.The VI D codes will change due t o t emperat ure and/ or currentload changes in order t o minimize t he power of t he part .A volt age range is provided in Table 2- 7.The specificat ions have been setsuch t hatone volt age regulat or can operat e wit h all support ed frequencies.I ndividual processor VI D values may be setduring manufact uring such t hatt wo devices att he same core frequency may have differentdefaultVI D set t ings.This is reflect ed by t he VI D range values provided in Table 2- 1.Dat asheet 15El ect r i calSpeci f i cat i onsThe processor uses eightvolt age ident ificat ion signals,VI D[ 7: 0] ,t o supportaut omat ic select ion of volt ages.Table 2- 1 specifies t he volt age level corresponding t o t he st at e of VI D[ 7: 0] .A 1 in t his t able refers t o a high volt age level and a 0 refers t o a low volt age level.I f t he processor socketis empt y ( VI D[ 7: 0]=11111111) ,or t he volt age regulat ion circuitcannotsupply t he volt age t hatis request ed,t he volt age regulat or mustdisable it self.The processor provides t he abilit y t o operat e while t ransit ioning t o an adj acentVI D and it s associat ed processor core volt age ( VCC) .This will representa DC shiftin t he loadline.I tshould be not ed t hata low- t o- high or high- t o- low volt age st at e change will resultin as many VI D t ransit ions as necessary t o reach t he t argetcore volt age.Transit ions above t he maximum specified VI D are notpermit t ed.Table 2- 8 includes VI D st ep sizes and DC shiftranges.Minimum and maximum volt ages mustbe maint ained as shown in Table 2- 8.The VR used mustbe capable of regulat ing it s out putt o t he value defined by t he new VI D. DC specificat ions for dynamic VI D t ransit ions are included in Table 2- 7 and Table 2- 8Tabl e 2- 1. Vol t age I dent i f i cat i on Def i ni t i on ( Sheet1 of3)VI D7VI D6VI D5VI D4VI D3VI D2VI D1VI D0VCC_MAXVI D7VI D6VI D5VI D4VI D3VI D2VI D1VI D0VCC_MAX0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1. 043750 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1. 037500 0 0 0 0 0 1 0 1. 60000 0 1 0 1 1 1 0 1 1. 031250 0 0 0 0 0 1 1 1. 59375 0 1 0 1 1 1 1 0 1. 025000 0 0 0 0 1 0 0 1. 58750 0 1 0 1 1 1 1 1 1. 018750 0 0 0 0 1 0 1 1. 58125 0 1 1 0 0 0 0 0 1. 012500 0 0 0 0 1 1 0 1. 57500 0 1 1 0 0 0 0 1 1. 006250 0 0 0 0 1 1 1 1. 56875 0 1 1 0 0 0 1 0 1. 000000 0 0 0 1 0 0 0 1. 56250 0 1 1 0 0 0 1 1 0. 993750 0 0 0 1 0 0 1 1. 55625 0 1 1 0 0 1 0 0 0. 987500 0 0 0 1 0 1 0 1. 55000 0 1 1 0 0 1 0 1 0. 981250 0 0 0 1 0 1 1 1. 54375 0 1 1 0 0 1 1 0 0. 975000 0 0 0 1 1 0 0 1. 53750 0 1 1 0 0 1 1 1 0. 968750 0 0 0 1 1 0 1 1. 53125 0 1 1 0 1 0 0 0 0. 962500 0 0 0 1 1 1 0 1. 52500 0 1 1 0 1 0 0 1 0. 956260 0 0 0 1 1 1 1 1. 51875 0 1 1 0 1 0 1 0 0. 950000 0 0 1 0 0 0 0 1. 51250 0 1 1 0 1 0 1 1 0. 943750 0 0 1 0 0 0 1 1. 50625 0 1 1 0 1 1 0 0 0. 937500 0 0 1 0 0 1 0 1. 50000 0 1 1 0 1 1 0 1 0. 931250 0 0 1 0 0 1 1 1. 49375 0 1 1 0 1 1 1 0 0. 925000 0 0 1 0 1 0 0 1. 48750 0 1 1 0 1 1 1 1 0. 918750 0 0 1 0 1 0 1 1. 48125 0 1 1 1 0 0 0 0 0. 912500 0 0 1 0 1 1 0 1. 47500 0 1 1 1 0 0 0 1 0. 906250 0 0 1 0 1 1 1 1. 46875 0 1 1 1 0 0 1 0 0. 900000 0 0 1 1 0 0 0 1. 46250 0 1 1 1 0 0 1 1 0. 893750 0 0 1 1 0 0 1 1. 45625 0 1 1 1 0 1 0 0 0. 887500 0 0 1 1 0 1 0 1. 45000 0 1 1 1 0 1 0 1 0. 881250 0 0 1 1 0 1 1 1. 44375 0 1 1 1 0 1 1 0 0. 875000 0 0 1 1 1 0 0 1. 43750 0 1 1 1 0 1 1 1 0. 868750 0 0 1 1 1 0 1 1. 43125 0 1 1 1 1 0 0 0 0. 862500 0 0 1 1 1 1 0 1. 42500 0 1 1 1 1 0 0 1 0. 85625El ect r i calSpeci f i cat i ons16 Dat asheet0 0 0 1 1 1 1 1 1. 41875 0 1 1 1 1 0 1 0 0. 850000 0 1 0 0 0 0 0 1. 41250 0 1 1 1 1 0 1 1 0. 843740 0 1 0 0 0 0 1 1. 40625 0 1 1 1 1 1 0 0 0. 837500 0 1 0 0 0 1 0 1. 40000 0 1 1 1 1 1 0 1 0. 831250 0 1 0 0 0 1 1 1. 39375 0 1 1 1 1 1 1 0 0. 825000 0 1 0 0 1 0 0 1. 38750 0 1 1 1 1 1 1 1 0. 818750 0 1 0 0 1 0 1 1. 38125 1 0 0 0 0 0 0 0 0. 812500 0 1 0 0 1 1 0 1. 37500 1 0 0 0 0 0 0 1 0. 806250 0 1 0 0 1 1 1 1. 36875 1 0 0 0 0 0 1 0 0. 800000 0 1 0 1 0 0 0 1. 36250 1 0 0 0 0 0 1 1 0. 793750 0 1 0 1 0 0 1 1. 35625 1 0 0 0 0 1 0 0 0. 787500 0 1 0 1 0 1 0 1. 35000 1 0 0 0 0 1 0 1 0. 781250 0 1 0 1 0 1 1 1. 34375 1 0 0 0 0 1 1 0 0. 775000 0 1 0 1 1 0 0 1. 33750 1 0 0 0 0 1 1 1 0. 768750 0 1 0 1 1 0 1 1. 33125 1 0 0 0 1 0 0 0 0. 762500 0 1 0 1 1 1 0 1. 32500 1 0 0 0 1 0 0 1 0. 756250 0 1 0 1 1 1 1 1. 31875 1 0 0 0 1 0 1 0 0. 750000 0 1 1 0 0 0 0 1. 31250 1 0 0 0 1 0 1 1 0. 743750 0 1 1 0 0 0 1 1. 30625 1 0 0 0 1 1 0 0 0. 737500 0 1 1 0 0 1 0 1. 30000 1 0 0 0 1 1 0 1 0. 731250 0 1 1 0 0 1 1 1. 29375 1 0 0 0 1 1 1 0 0. 725000 0 1 1 0 1 0 0 1. 28750 1 0 0 0 1 1 1 1 0. 718750 0 1 1 0 1 0 1 1. 28125 1 0 0 1 0 0 0 0 0. 712500 0 1 1 0 1 1 0 1. 27500 1 0 0 1 0 0 0 1 0. 706250 0 1 1 0 1 1 1 1. 26875 1 0 0 1 0 0 1 0 0. 700000 0 1 1 1 0 0 0 1. 26250 1 0 0 1 0 0 1 1 0. 693750 0 1 1 1 0 0 1 1. 25625 1 0 0 1 0 1 0 0 0. 687500 0 1 1 1 0 1 0 1. 25000 1 0 0 1 0 1 0 1 0. 681250 0 1 1 1 0 1 1 1. 24375 1 0 0 1 0 1 1 0 0. 675000 0 1 1 1 1 0 0 1. 23750 1 0 0 1 0 1 1 1 0. 668750 0 1 1 1 1 0 1 1. 23125 1 0 0 1 1 0 0 0 0. 662500 0 1 1 1 1 1 0 1. 22500 1 0 0 1 1 0 0 1 0. 656250 0 1 1 1 1 1 1 1. 21875 1 0 0 1 1 0 1 0 0. 650000 1 0 0 0 0 0 0 1. 21250 1 0 0 1 1 0 1 1 0. 643750 1 0 0 0 0 0 1 1. 20625 1 0 0 1 1 1 0 0 0. 637500 1 0 0 0 0 1 0 1. 20000 1 0 0 1 1 1 0 1 0. 631250 1 0 0 0 0 1 1 1. 19375 1 0 0 1 1 1 1 0 0. 625000 1 0 0 0 1 0 0 1. 18750 1 0 0 1 1 1 1 1 0. 618750 1 0 0 0 1 0 1 1. 18125 1 0 1 0 0 0 0 0 0. 612500 1 0 0 0 1 1 0 1. 17500 1 0 1 0 0 0 0 1 0. 606250 1 0 0 0 1 1 1 1. 16875 1 0 1 0 0 0 1 0 0. 600000 1 0 0 1 0 0 0 1. 16250 1 0 1 0 0 0 1 1 0. 593750 1 0 0 1 0 0 1 1. 15625 1 0 1 0 0 1 0 0 0. 587500 1 0 0 1 0 1 0 1. 15000 1 0 1 0 0 1 0 1 0. 581250 1 0 0 1 0 1 1 1. 14375 1 0 1 0 0 1 1 0 0. 575000 1 0 0 1 1 0 0 1. 13750 1 0 1 0 0 1 1 1 0. 568750 1 0 0 1 1 0 1 1. 13125 1 0 1 0 1 0 0 0 0. 562500 1 0 0 1 1 1 0 1. 12500 1 0 1 0 1 0 0 1 0. 55625Tabl e 2- 1. Vol t age I dent i f i cat i on Def i ni t i on ( Sheet2 of3)VI D7VI D6VI D5VI D4VI D3VI D2VI D1VI D0VCC_MAXVI D7VI D6VI D5VI D4VI D3VI D2VI D1VI D0VCC_MAXDat asheet 17El ect r i calSpeci f i cat i ons2. 6 Reser v ed orUnused Si gnal sAll Reserved ( RSVD)signals mustremain unconnect ed.Connect ion of t hese signals t o VCC,VTTA,VTTD,VDDQ, VCCPLL,VSS,or t o any ot her signal ( including each ot her)can resultin componentmalfunct ion or incompat ibilit y wit h fut ure processors.See Chapt er 4 for a land list ing of t he processor and t he locat ion of all Reserved signals.For reliable operat ion,always connectunused input s or bi- direct ional signals t o an appropriat e signal level,exceptfor unused int egrat ed memory cont roller input s,out put s,and bi- direct ional pins which may be leftfloat ing.Unused act ive high input s should be connect ed t hrough a resist or t o ground ( VSS) . Unused out put s maybe leftunconnect ed;however,t his may int erfere wit h some TestAccess Port( TAP)funct ions,complicat e debug probing, and preventboundary scan t est ing.A resist or mustbe used when t ying bi- direct ional signals t o power or ground.When t ying any signal t o power or ground,a resist or will also allow for syst em t est abilit y. 0 1 0 0 1 1 1 1 1. 11875 1 0 1 0 1 0 1 0 0. 550000 1 0 1 0 0 0 0 1. 11250 1 0 1 0 1 0 1 1 0. 543750 1 0 1 0 0 0 1 1. 10625 1 0 1 0 1 1 0 0 0. 537500 1 0 1 0 0 1 0 1. 10000 1 0 1 0 1 1 0 1 0. 531250 1 0 1 0 0 1 1 1. 09375 1 0 1 0 1 1 1 0 0. 525000 1 0 1 0 1 0 0 1. 08750 1 0 1 0 1 1 1 1 0. 518750 1 0 1 0 1 0 1 1. 08125 1 0 1 1 0 0 0 0 0. 512500 1 0 1 0 1 1 0 1. 07500 1 0 1 1 0 0 0 1 0. 506250 1 0 1 0 1 1 1 1. 06875 1 0 1 1 0 0 1 0 0. 500000 1 0 1 1 0 0 0 1. 06250 1 1 1 1 1 1 1 0 OFF0 1 0 1 1 0 0 1 1. 05625 1 1 1 1 1 1 1 1 OFF0 1 0 1 1 0 1 0 1. 05000Tabl e 2- 2. Mar k etSegmentSel ect i on Tr ut h Tabl e f orMS_I D[ 2: 0]MSI D2 MSI D1 MSI D0 Descr i pt i on1Not es:1. TheMSI D[ 2: 0] signalsareprovidedt oindicat et heMarket Segment fort heprocessorandmaybeusedforfut ure processor compat ibilit y or for keying.0 0 0 Reser ved0 0 1 Reser ved0 1 0 Reser ved0 1 1 Reser ved1 0 0 Reser ved1 0 1 Reser ved1 1 0 I nt el Core i7- 900 deskt op processor Ext reme Edit ion series and I nt el Core i7- 900 deskt op processor series1 1 1 Reser vedTabl e 2- 1. Vol t age I dent i f i cat i on Def i ni t i on ( Sheet3 of3)VI D7VI D6VI D5VI D4VI D3VI D2VI D1VI D0VCC_MAXVI D7VI D6VI D5VI D4VI D3VI D2VI D1VI D0VCC_MAXEl ect r i calSpeci f i cat i ons18 Dat asheet2. 7 Si gnalGr oupsSignals are grouped by buffer t ype and similar charact erist ics as list ed in Table 2- 3.The buffer t ype indicat es which signaling t echnology and specificat ions apply t o t he signals.All t he different ial signals,and select ed DDR3 and Cont rol Sideband signals have On-Die Terminat ion ( ODT)resist ors. There are some signals t hatdo nothave ODT and need t o be t erminat ed on t he board.The signals t hathave ODT are list ed in Table 2- 4.Tabl e 2- 3. Si gnalGr oups ( Sheet1 of2)Si gnal Gr oup Type Si gnal s1, 2Syst em Ref er ence Cl ockDifferent ial Clock I nput BCLK_DP,BCLK_DNI nt el QPISi gnalGr oupsDifferent ial I nt el QPII nput QPI _DRX_D[ N/ P] [ 19: 0] ,QPI _CLKRX_DP,QPI _CLKRX_DNDifferent ial I nt el QPIOut put QPI _DTX_D[ N/ P] [ 19: 0] ,QPI _CLKTX_DP,QPI _CLKTX_DNDDR3 Ref er ence Cl ock sDifferent ialDDR3 Out put DDR{ 0/ 1/ 2} _CLK[ D/ P] [ 3: 0]DDR3 Command Si gnal sSingle ended CMOS Out put DDR{ 0/ 1/ 2} _RAS# ,DDR{ 0/ 1/ 2} _CAS# ,DDR{ 0/ 1/ 2} _WE# ,DDR{ 0/ 1/ 2} _MA[ 15: 0] ,DDR{ 0/ 1/ 2} _BA[ 2: 0]Single ended Asynchronous Out put DDR{ 0/ 1/ 2} _RESET#DDR3 Cont r olSi gnal sSingle ended CMOS Out put DDR{ 0/ 1/ 2} _CS# [ 5: 4] ,DDR{ 0/ 1/ 2} _CS# [ 1: 0] ,DDR{ 0/ 1/ 2} _ODT[ 3: 0] ,DDR{ 0/ 1/ 2} _CKE[ 3: 0]DDR3 Dat a Si gnal sSingle ended CMOS Bi- direct ional DDR{ 0/ 1/ 2} _DQ[ 63: 0]Different ial CMOS Bi- direct ional DDR{ 0/ 1/ 2} _DQS_[ N/ P] [ 7: 0]TAPSingle ended TAP I nput TCK,TDI ,TMS,TRST#Single ended GTL Out put TDOCont r olSi debandSingle ended Asynchronous GTL Out put PRDY#Single ended Asynchronous GTL I nput PREQ#Single ended GTL Bi- direct ional CAT_ERR# ,BPM# [ 7: 0]Single Ended Asynchronous Bi- direct ional PECISingle Ended Analog I nput COMP0,QPI _CMP[ 0] ,DDR_COMP[ 2: 0]Single ended Asynchronous GTL Bi-direct ional PROCHOT#Single ended Asynchronous GTL Out put THERMTRI P#Single ended CMOS I nput / Out put VI D[ 7: 6]VI D[ 5: 3] / CSC[ 2: 0]VI D[ 2: 0] / MSI D[ 2: 0]VTT_VI D[ 4: 2]Dat asheet 19El ect r i calSpeci f i cat i onsNot es:1. Unless ot herwise specified,signals have ODT in t he package wit h 50 O pulldown t o VSS.2. PREQ# ,BPM[ 7: 0] ,TDI ,TMS and BCLK_I TP_D[ N/ P]have ODT in package wit h 35 O pullup t o VTT.3. VCCPWRGOOD,VDDPWRGOOD,and VTTPWRGOOD have ODT in package wit h a 10 kO t o 20 kO pulldown t o VSS.4. TRST#has ODT in package wit h a 1 kO t o 5 kO pullup t o VTT.5. All DDR signals are t erminat ed t o VDDQ/ 26. DDR{ 0/ 1/ 2}refers t o DDR3 Channel 0,DDR3 Channel 1,and DDR3 Channel 2.7. While TMS and TDIdo nothave On- Die Terminat ion,t hese signals are weakly pulled up using a 15 kO resist or t o VTT8. While TCK does nothave On- Die Terminat ion,t his signal is weakly pulled down using a 15 kO resist or t o VSS.All Cont rol Sideband Asynchronous signals are required t o be assert ed/ de- assert ed for atleasteightBCLKs for t he processor t o recognize t he proper signal st at e.See Sect ion 2. 11 for t he DC specificat ions.See Chapt er 6 for addit ional t iming requirement s for ent ering and leaving t he low power st at es.2. 8 TestAccess Por t( TAP)Connect i onDue t o t he volt age levels support ed by ot her component s in t he TestAccess Port( TAP)logic,itis recommended t hatt he processor be firstin t he TAP chain and followed by any ot her component s wit hin t he syst em.A t ranslat ion buffer should be used t o connectt o t he restof t he chain unless one of t he ot her component s is capable of accept ing an inputof t he appropriat e volt age. Two copies of each signal may be required wit h each driving a differentvolt age level. Single ended CMOS Out put VTT_VI D[ 4: 2]Single endedAnalog I nput I SENSEResetSi gnalSingle ended ResetI nput RESET#PWRGOOD Si gnal sSingle ended Asynchronous I nput VCCPWRGOOD,VTTPWRGOOD,VDDPWRGOODPow er / Ot herPower VCC,VTTA,VTTD,VCCPLL,VDDQAsynchronous CMOS Out put PSI #Sense Point s VCC_SENSE,VSS_SENSEOt her SKTOCC# ,DBR#Not es:1. Refer t o Chapt er 5 for signal descript ions.2. DDR{ 0/ 1/ 2}refers t o DDR3 Channel 0,DDR3 Channel 1,and DDR3 Channel 2.Tabl e 2- 4. Si gnal s w i t h ODT QPI _DRX_DP[ 19: 0] ,QPI _DRX_DN[ 19: 0] ,QPI _DTX_DP[ 19: 0] ,QPI _DTX_DN[ 19: 0] ,QPI _CLKRX_D[ N/ P] ,QPI _CLKTX_D[ N/ P] DDR{ 0/ 1/ 2} _DQ[ 63: 0] ,DDR{ 0/ 1/ 2} _DQS_[ N/ P] [ 7: 0] ,DDR{ 0/ 1/ 2} _PAR_ERR# [ 0: 2] ,VDDPWRGOOD BCLK_I TP_D[ N/ P] PECI BPM# [ 7: 0] ,PREQ# ,TRST# ,VCCPWRGOOD,VTTPWRGOODTabl e 2- 3. Si gnalGr oups ( Sheet2 of2)Si gnal Gr oup Ty pe Si gnal s1,2El ect r i calSpeci f i cat i ons20 Dat asheet2. 9 Pl at f or m Env i r onment alCont r olI nt er f ace ( PECI )DC Speci f i cat i onsPECIis an I nt el propriet ary int erface t hatprovides a communicat ion channel bet ween I nt el processors and chipsetcomponent s t o ext ernal t hermal monit oring devices. The processor cont ains a Digit al Thermal Sensor ( DTS)t hatreport s a relat ive die t emperat ure as an offsetfrom Thermal Cont rol Circuit( TCC)act ivat ion t emperat ure. Temperat ure sensors locat ed t hroughoutt he die are implement ed as analog- t o- digit al convert ers calibrat ed att he fact ory.PECIprovides an int erface for ext ernal devices t o read t he DTS t emperat ure for t hermal managementand fan speed cont rol.More det ailed informat ion may be found in t he Plat form EnvironmentCont rol I nt erface ( PECI )Specificat ion.2.9.1 DC Char act er i st i csThe PECIint erface operat es ata nominal volt age setby VTTD.The setof DC elect rical specificat ions shown inTable 2- 5 is used wit h devices normally operat ing from a VTTD int erface supply.VTTD nominal levels will vary bet ween processor families.All PECIdevices will operat e att he VTTD level det ermined by t he processor inst alled in t he syst em.For specific nominal VTTD levels,refer t o Table 2- 7.Not es:1. VTTD supplies t he PECIint erface.PECIbehavior does notaffectVTTD min/ max specificat ions.2. The leakage specificat ion applies t o powered devices on t he PECIbus.Tabl e 2- 5. PECIDC El ect r i calLi mi t sSy mbol Def i ni t i on and Condi t i ons Mi n Max Uni t s Not es1VinI nputVolt age Range - 0. 150 VTTDVVhyst eresisHyst eresis 0. 1 *VTTDN/ A VVnNegat ive- edge t hreshold volt age 0. 275 *VTTD0. 500 *VTTDVVpPosit ive- edge t hreshold volt age 0. 550 *VTTD0. 725 *VTTDVIsourceHigh level out putsource( VOH =0. 75 *VTTD)- 6.0 N/ A mAIsinkLow level out putsink( VOL =0. 25 *VTTD)0. 5 1. 0 mAIleak+High impedance st at e leakage t o VTTD ( Vleak =VOL)N/ A 100 A 2Ileak-High impedance leakage t o GND ( Vleak =VOH)N/ A 100 A 2CbusBus capacit ance per node N/ A 10 pFVnoiseSignal noise immunit y above 300 MHz 0. 1 *VTTDN/ A Vp- pDat asheet 21El ect r i calSpeci f i cat i ons2.9.2 I nputDevi ce Hy st er esi sThe inputbuffers in bot h clientand hostmodels mustuse a Schmit t - t riggered inputdesign for improved noise immunit y.Use Figure 2- 2 as a guide for inputbuffer design.2. 10 Absol ut e Max i mum and Mi ni mum Rat i ngsTable 2- 6 specifies absolut e maximum and minimum rat ings,which lie out side t he funct ional limit s of t he processor. Only wit hin specified operat ion limit s can funct ionalit y and long- t erm reliabilit y be expect ed.Atcondit ions out side funct ional operat ion condit ion limit s,butwit hin absolut e maximum and minimum rat ings,neit her funct ionalit y nor long- t erm reliabilit y can be expect ed.I f a device is ret urned t o condit ions wit hin funct ional operat ion limit s aft er having been subj ect ed t o condit ions out side t hese limit s,butwit hin t he absolut e maximum and minimum rat ings,t he device may be funct ional,butwit h it s lifet ime degraded depending on exposure t o condit ions exceeding t he funct ional operat ion condit ion limit s.Atcondit ions exceeding absolut e maximum and minimum rat ings,neit her funct ionalit y nor long- t erm reliabilit y can be expect ed.Moreover,if a device is subj ect ed t o t hese condit ions for any lengt h of t ime t hen,when ret urned t o condit ions wit hin t he funct ional operat ing condit ion limit s,itwill eit her notfunct ion or it s reliabilit y will be severely degraded.Alt hough t he processor cont ains prot ect ive circuit ry t o resistdamage from Elect ro-St at ic Discharge ( ESD) ,precaut ions should always be t aken t o avoid high st at ic volt ages or elect ric fields.Fi gur e 2- 2. I nputDevi ce Hy st er esi sMinimum VPMaximum VPMinimum VNMaximum VNPECI High RangePECI Low RangeValid InputSignal RangeMinimumHysteresisVTTDPECI GroundEl ect r i calSpeci f i cat i ons22 Dat asheet.Not es:1. For funct ional operat ion,all processor elect rical,signal qualit y,mechanical and t hermal specificat ions mustbe sat isfied.2. Excessive overshootor undershooton any signal will likely resultin permanentdamage t o t he processor.3. VTTA and VTTD should be derived from t he same VR.2.11 Pr ocessorDC Speci f i cat i onsThe pr ocessorDC speci f i cat i ons i n t hi s sect i on ar e def i ned att he pr ocessorpads,unl ess not ed ot her w i se. See Chapt er 4 for t he processor land list ings and Chapt er 5 for signal definit ions.Volt age and currentspecificat ions are det ailed in Table 2- 7.For plat form planning,refer t o Table 2- 8,which provides VCC st at ic and t ransientt olerances.This same informat ion is present ed graphically in Figure 2- 3.The DC specificat ions for t he DDR3 signals are list ed in Table 2- 11.Cont rol Sideband and TestAccess Port( TAP)are list ed in Table 2- 12 t hrough Table 2- 15.Table 2- 7 t hrough Table 2- 15 listt he DC specificat ions for t he processor and are valid only while meet ing specificat ions for case t emperat ure ( TCASE as specified in Chapt er 6, Thermal Specificat ions ) ,clock frequency, and inputvolt ages.Care should be t aken t o read all not es associat ed wit h each paramet er.Tabl e 2- 6. Pr ocessorAbsol ut e Mi ni mum and Max i mum Rat i ngsSy mbol Par amet er Mi n Max Uni t Not es1,2VCCProcessor Core volt age wit h respectt o VSS- 0. 3 1. 55 VVTTAVolt age for t he analog port ion of t he int egrat ed memory cont roller,QPIlink and Shared Cache wit h respectt o VSS 1. 35 V 3VTTDVolt age for t he digit al port ion of t he int egrat ed memory cont roller,QPIlink and Shared Cache wit h respectt o VSS 1. 35 V 3VDDQProcessor I / O supply volt age for DDR3 wit h respectt o VSS 1. 875 VVCCPLLProcessor PLL volt age wit h respectt o VSS1. 65 1. 89 VTCASEProcessor case t emperat ure See Chapt er 6See Chapt er 6CTSTORAGESt orage t emperat ur e See Chapt er 6See Chapt er 6CDat asheet 23El ect r i calSpeci f i cat i ons2. 11. 1 DC Vol t age and Cur r entSpeci f i cat i onTabl e 2- 7. Vol t age and Cur r entSpeci f i cat i ons Symbol Par amet er Mi n Typ Max Uni t Not es 1Not es:1. Unless ot herwise not ed,all specificat ions in t his t able are based on est imat es and simulat ions or empirical dat a.These specificat ions will be updat ed wit h charact erized dat a from silicon measurement s ata lat er dat eVI D VI D range 0. 8 1. 375 V22. Each processor is programmed wit h a maximum valid volt age ident ificat ion value ( VI D) ,which is setatmanufact uring and can notbe alt ered.I ndividual maximum VI D values are calibrat ed during manufact uring such t hatt wo processors att he same frequency may have differentset t ings wit hin t he VI D range.Please not e t his differs from t he VI D employed by t he processor during a power managementevent( Adapt ive Thermal Monit or,Enhanced I nt el SpeedSt ep Technology,or Low Power St at es) .VCCProcessor Numberi7- 975i7- 965i7- 960i7- 950i7- 940i7- 930i7- 920VCC for processor core3. 33 GHz3. 20 GHz3. 20 GHz3. 06 GHz2. 93 GHz2. 80 GHz2. 66 GHzSee Table 2- 8 and Figure 2- 3 V3, 43. The volt age specificat ion requirement s are measured across VCC_SENSE and VSS_SENSE lands att he socketwit h a 100 MHz bandwidt h oscilloscope,1.5 pF maximum probe capacit ance,and 1 MO minimum impedance.The maximum lengt h of ground wire on t he probe should be less t han 5 mm. Ensure ext ernal noise from t he syst em is notcoupled int o t he oscilloscope probe.4. Refer t o Table 2- 8 and Figure 2- 3 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.VTTAVolt age for t he analog port ion of t he int egrat ed memory cont roller,QPIlink and Shared CacheSee Table 2- 10 and Figure 2- 4 V55. See Table 2- 9 for det ails on VTT Volt age I dent ificat ion and Table 2- 9 and Figure 2- 4 for det ails on t he VTT Loadline.VTTDVolt age for t he digit al port ion of t he int egrat ed memory cont roller,QPIlink and Shared CacheSee Table 2- 9 and Figure 2- 4 V 5VDDQProcessor I / O supply volt age for DDR31. 425 1. 5 1. 575 VVCCPLLPLL supply volt age ( DC +AC specificat ion)1. 71 1. 8 1. 89VICCProcessor Numberi7- 975i7- 965i7- 960i7- 950i7- 940i7- 930i7- 920ICC for processor3. 33 GHz3. 20 GHz3. 20 GHz3. 06 GHz2. 93 GHz2. 80 GHz2. 66 GHz 145145145145145145145A66. ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 2- 3 for details. ITTACurrentfor t he analog port ion of t he int egrat ed memory cont roller,QPIlink and Shared Cache 5 AITTDCurrentfor t he digit al port ion of t he int egrat ed memory cont roller,QPIlink and Shared Cache 23 AIDDQProcessor I / O supply currentfor DDR3 6 AIDDQS3 Processor I / O supply currentfor DDR3 while in S3 1 A77. This specificat ion is based on a processor t emperat ure,as report ed by t he DTS,of less t han or equal t o TCONTROL25.ICC_VCCPLLPLL supply current( DC +AC specificat ion) 1. 1 AEl ect r i calSpeci f i cat i ons24 Dat asheetNot es:1. The VCC_MI N and VCC_MAX loadlines representst at ic and t ransientlimit s.See Sect ion 2. 11. 2 for VCC overshootspecificat ions.2. This t able is int ended t o aid in reading discret e point s on Figure 2- 3.3. The loadlines specify volt age limit s att he die measured att he VCC_SENSE and VSS_SENSE lands.Volt age regulat ion feedback for volt age regulat or circuit s mustalso be t aken from processor VCC_SENSE and VSS_SENSE lands.Tabl e 2- 8. VCC St at i c and Tr ansi entTol er anceICC ( A) VCC_Max( V) VCC_Ty p ( V) VCC_Mi n ( V) Not es0 VI D -0. 000 VI D -0. 019 VI D -0. 038 1,2,35 VI D -0. 004 VI D -0. 023 VI D -0. 042 1,2,310 VI D -0. 008 VI D -0. 027 VI D -0. 046 1,2,315 VI D -0. 012 VI D -0. 031 VI D -0. 050 1,2,320 VI D -0. 016 VI D -0. 035 VI D -0. 054 1,2,325 VI D -0. 020 VI D -0. 039 VI D -0. 058 1,2,330 VI D -0. 024 VI D -0. 043 VI D -0. 062 1,2,335 VI D -0. 028 VI D -0. 047 VI D -0. 066 1,2,340 VI D -0. 032 VI D -0. 051 VI D -0. 070 1,2,345 VI D -0. 036 VI D -0. 055 VI D -0. 074 1,2,350 VI D -0. 040 VI D -0. 059 VI D -0. 078 1,2,355 VI D -0. 044 VI D -0. 063 VI D -0. 082 1,2,360 VI D -0. 048 VI D -0. 067 VI D -0. 086 1,2,365 VI D -0. 052 VI D -0. 071 VI D -0. 090 1,2,370 VI D -0. 056 VI D -0. 075 VI D -0. 094 1,2,375 VI D -0. 060 VI D -0. 079 VI D -0. 098 1,2,378 VI D -0. 062 VI D -0. 081 VI D -0. 100 1,2,385 VI D -0. 068 VI D -0. 087 VI D -0. 106 1,2,390 VI D -0. 072 VI D -0. 091 VI D -0. 110 1,2,395 VI D -0. 076 VI D -0. 095 VI D -0. 114 1,2,3100 VI D -0. 080 VI D -0. 099 VI D -0. 118 1,2,3105 VI D -0. 084 VI D -0. 103 VI D -0. 122 1,2,3110 VI D -0. 088 VI D -0. 107 VI D -0. 126 1,2,3115 VI D -0. 092 VI D -0. 111 VI D -0. 130 1,2,3120 VI D -0. 096 VI D -0. 115 VI D -0. 134 1,2,3125 VI D -0. 100 VI D -0. 119 VI D -0. 138 1,2,3130 VI D -0. 104 VI D -0. 123 VI D -0. 142 1,2,3135 VI D -0. 108 VI D -0. 127 VI D -0. 146 1,2,3140 VI D -0. 112 VI D -0. 131 VI D -0. 150 1,2,3Dat asheet 25El ect r i calSpeci f i cat i onsNot e:1. This is a t ypical volt age,see Table 2- 10 for VTT_Max and VTT_Min volt age.Fi gur e 2- 3. VCC St at i c and Tr ansi entTol er ance Load Li nesTabl e 2- 9. VTT Vol t age I dent i f i cat i on ( VI D)Def i ni t i onVTT VR -VI D I nput VTT_Typ VI D7 VI D6 VI D5 VI D4 VI D3 VI D2 VI D1 VI D00 1 0 0 0 0 1 0 1. 220 V0 1 0 0 0 1 1 0 1. 195 V0 1 0 0 1 0 1 0 1. 170 V0 1 0 0 1 1 1 0 1. 145 V0 1 0 1 0 0 1 0 1. 120 V0 1 0 1 0 1 1 0 1. 095 V0 1 0 1 1 0 1 0 1. 070 V0 1 0 1 1 1 1 0 1. 045 VVID - 0.000VID - 0.013VID - 0.025VID - 0.038VID - 0.050VID - 0.063VID - 0.075VID - 0.088VID - 0.100VID - 0.113VID - 0.125VID - 0.138VID - 0.150VID - 0.163VID - 0.1750 10 20 30 40 50 60 70 80 90 100 110 120 130 140VccVIcc [A]Vcc MaximumVcc TypicalVcc MinimumEl ect r i calSpeci f i cat i ons26 Dat asheetTabl e 2- 10. VTT St at i c and Tr ansi entTol er anceITT ( A) VTT_Max( V) VTT_Ty p ( V) VTT_Mi n ( V) Not es1Not es:1. The ITT list ed in t his t able is a sum of ITTA and ITTD.2.The loadlines specify volt age limit s att he die measured att he VTT_SENSE and VSS_SENSE_VTT lands.Volt ageregulat ionfeedbackforvolt ageregulat orcircuit smust alsobet akenfromprocessorVTT_SENSEandVSS_SENSE_VTT lands.0 VI D +0. 0315 VI D 0. 0000 VI D 0. 03151 VI D +0. 0255 VI D 0. 0060 VI D 0. 03752 VI D +0. 0195 VI D 0. 0120 VI D 0. 04353 VI D +0. 0135 VI D 0. 0180 VI D 0. 04954 VI D +0. 0075 VI D 0. 0240 VI D 0. 05555 VI D +0. 0015 VI D 0. 0300 VI D 0. 06156 VI D 0. 0045 VI D 0. 0360 VI D 0. 06757 VI D 0. 0105 VI D 0. 0420 VI D 0. 07358 VI D 0. 0165 VI D 0. 0480 VI D 0. 07959 VI D 0. 0225 VI D 0. 0540 VI D 0. 085510 VI D 0. 0285 VI D 0. 0600 VI D 0. 091511 VI D 0. 0345 VI D 0. 0660 VI D 0. 097512 VI D 0. 0405 VI D 0. 0720 VI D 0. 103513 VI D 0. 0465 VI D 0. 0780 VI D 0. 109514 VI D 0. 0525 VI D 0. 0840 VI D 0. 115515 VI D 0. 0585 VI D 0. 0900 VI D 0. 121516 VI D 0. 0645 VI D 0. 0960 VI D 0. 127517 VI D 0. 0705 VI D 0. 1020 VI D 0. 133518 VI D 0. 0765 VI D 0. 1080 VI D 0. 139519 VI D 0. 0825 VI D 0. 1140 VI D 0. 145520 VI D 0. 0885 VI D 0. 1200 VI D 0. 151521 VI D 0. 0945 VI D 0. 1260 VI D 0. 157522 VI D 0. 1005 VI D 0. 1320 VI D 0. 163523 VI D 0. 1065 VI D 0. 1380 VI D 0. 169524 VI D 0. 1125 VI D 0. 1440 VI D 0. 175525 VI D 0. 1185 VI D 0. 1500 VI D 0. 181526 VI D 0. 1245 VI D 0. 1560 VI D 0. 187527 VI D 0. 1305 VI D 0. 1620 VI D 0. 193528 VI D 0. 1365 VI D 0. 1680 VI D 0. 1995Dat asheet 27El ect r i calSpeci f i cat i onsNot es:1. Unless ot herwise not ed,all specificat ions in t his t able apply t o all processor frequencies.2. VI L is defined as t he maximum volt age level ata receiving agentt hatwill be int erpret ed as a logical low value.3. VI H is defined as t he minimum volt age level ata receiving agentt hatwill be int erpret ed as a logical high value.Fi gur e 2- 4. VTT St at i c and Tr ansi entTol er ance Load Li neTabl e 2- 11. DDR3 Si gnalGr oup DC Speci f i cat i onsSy mbol Par amet er Mi n Ty p Max Uni t s Not es1VI LI nputLow Volt age 0. 43* VDDQV 2, 4VI HI nputHigh Volt age 0. 57* VDDQ V 3VOLOut putLow Volt age( VDDQ /2) *( RON /( RON+ RVTT_TERM) ) VVOHOut putHigh Volt ageVDDQ ( ( VDDQ /2) *( RON/ ( RON+ RVTT_TERM) ) V 4RONDDR3 Clock Buffer On Resist ance21 31 ORONDDR3 Command Buffer On Resist ance16 24 ORONDDR3 ResetBuffer On Resist ance25 75 ORONDDR3 Cont rol Buffer On Resist ance21 31 ORONDDR3 Dat a Buffer On Resist ance21 31 OILII nputLeakage Current N/ A N/ A 1 mADDR_COMP0COMP Resist ance 99 100 101 O 5DDR_COMP1COMP Resist ance 24. 65 24. 9 25. 15 O 5DDR_COMP2COMP Resist ance 128. 7 130 131. 30 O 5-0.2125-0.2000-0.1875-0.1750-0.1625-0.1500-0.1375-0.1250-0.1125-0.1000-0.0875-0.0750-0.0625-0.0500-0.0375-0.0250-0.01250.00000.01250.02500.03750.05000 5 10 15 20 25VttVItt [A](sum of Ittaand Ittd)Vtt MaximumVtt TypicalVtt MinimumEl ect r i calSpeci f i cat i ons28 Dat asheet4. VI H and VOH may experience excursions above VDDQ.However,inputsignal drivers mustcomply wit h t he signal qualit y specificat ions.5. COMP resist ance mustbe provided on t he syst em board wit h 1% resist ors.Not es:1. Unless ot herwise not ed,all specificat ions in t his t able apply t o all processor frequencies.2. The VTTA referred t o in t hese specificat ions refers t o inst ant aneous VTTA.3. For Vin bet ween 0 V and VTTA.Measured when t he driver is t rist at ed.4. VI H and VOH may experience excursions above VTT.Not es:1. Unless ot herwise not ed,all specificat ions in t his t able apply t o all processor frequencies.2. The VTTA referred t o in t hese specificat ions refers t o inst ant aneous VTTA.3. For Vin bet ween 0 V and VTTA.Measured when t he driver is t rist at ed.4. VI H and VOH may experience excursions above VTT.Not es:1. Unless ot herwise not ed,all specificat ions in t his t able apply t o all processor frequencies.2. The VTTA referred t o in t hese specificat ions refers t o inst ant aneous VTTA.3. For Vin bet ween 0 V and VTTA.Measured when t he driver is t rist at ed.4. VI H and VOH may experience excursions above VTT.5. This specificat ion applies t o VCCPWRGOOD and VTTPWRGOOD6. This specificat ion applies t o VDDPWRGOODTabl e 2- 12. RESET#Si gnalDC Speci f i cat i onsSy mbol Par amet er Mi n Typ Max Uni t s Not es1VI LI nputLow Volt age 0. 40 *VTTA V 2VI HI nputHigh Volt age 0. 80 * VTTA 2, 4ILII nputLeakage Current 200 uA 3Tabl e 2- 13. TAP Si gnalGr oup DC Speci f i cat i onsSy mbol Par amet er Mi n Typ Max Uni t s Not es1VI LI nputLow Volt age 0. 40 *VTTA V 2VI HI nputHigh Volt age0. 75 *VTTA 2, 4VOLOut putLow Volt age VTTA *RON /( RON +Rsys_t erm)V 2VOHOut putHigh Volt age VTTA V 2, 4Ron Buffer on Resist ance 10 18 OILII nputLeakage Current 200 uA 3Tabl e 2- 14. PWRGOOD Si gnalGr oup DC Speci f i cat i onsSy mbol Par amet er Mi n Ty p Max Uni t s Not es1VI LI nputLow Volt age for VCCPWRGOOD and VTTPWRGOOD Signals 0. 25 *VTTA V 2, 5VI LI nputLow Volt age for VDDPWRGOOD Signal 0. 29 V 6VI HI nputHigh Volt age for VCCPWRGOOD and VTTPWRGOOD Signals0. 75 *VTTA V 2, 5VI HI nputHigh Volt age for VDDPWRGOOD Signal0. 87 V 5Ron Buffer on Resist ance 10 18 OILII nputLeakage Current 200 uA 4Dat asheet 29El ect r i calSpeci f i cat i onsNot es:1. Unless ot herwise not ed,all specificat ions in t his t able apply t o all processor frequencies.2. The VTTA referred t o in t hese specificat ions refers t o inst ant aneous VTTA.3. For Vin bet ween 0 V and VTTA.Measured when t he driver is t rist at ed.4. VI H and VOH may experience excursions above VTT.5. COMP resist ance mustbe provided on t he syst em board wit h 1% resist ors.2.11.2 VCC Over shootSpeci f i cat i onThe processor can t olerat e shortt ransientovershootevent s where VCC exceeds t he VI D volt age when t ransit ioning from a high- t o- low currentload condit ion.This overshootcannotexceed VI D +VOS_MAX ( VOS_MAX is t he maximum allowable overshootabove VI D) .These specificat ions apply t o t he processor die volt age as measured across t he VCC_SENSE and VSS_SENSE lands.Tabl e 2- 15. Cont r olSi deband Si gnalGr oup DC Speci f i cat i onsSy mbol Par amet er Mi n Ty p Max Uni t s Not es1VI LI nputLow Volt age 0. 64 *VTTA V 2VI HI nputHigh Volt age 0. 76 *VTTA V 2VOLOut putLow Volt age VTTA *RON /( RON +Rsys_t erm)V 2, 4VOHOut putHigh Volt age VTTA V 2, 4Ron Buffer on Resist ance 10 18 ORonBuffer on Resist ance for VI D[ 7: 0] 100 OILII nputLeakage Current 200 uA 3COMP0 COMP Resist ance 49. 4 49. 9 50. 40 O 5Tabl e 2- 16. VCC Over shootSpeci f i cat i onsSy mbol Par amet er Mi n Max Uni t s Fi gur e Not esVOS_MAXMagnit ude of VCCP overshootabove VI D 50 mV 2- 5TOS_MAXTime durat ion of VCCP overshootabove VI D 25 s 2- 5El ect r i calSpeci f i cat i ons30 Dat asheet2.11. 3 Di e Vol t age Val i dat i onCore volt age ( VCC)overshootevent s att he processor mustmeett he specificat ions in Table 2- 16 when measured across t he VCC_SENSE and VSS_SENSE lands.Overshootevent s t hatare